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[Qemu-ppc] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP |
Date: |
Fri, 23 Sep 2016 17:15:19 +1000 |
From: Michael Walle <address@hidden>
Only the POWER[789] CPUs should have the ARCH_206 bit set. This is what the
linux kernel does. I guess this was also the intention of commit 0e019746.
We have to make sure all *206 bits are set.
Before this patch, the flags check in the GET_FEATURES2 macro returned true
if _any_ bit was set. This worked well as long as there was only one bit
set in the 'flag' parameter. But as explained before, we have to make sure
all bits in the 'flag' parameter are set.
Signed-off-by: Michael Walle <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
linux-user/elfload.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 3d751f8..816272a 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -741,8 +741,12 @@ static uint32_t get_elf_hwcap(void)
Altivec/FP/SPE support. Anything else is just a bonus. */
#define GET_FEATURE(flag, feature) \
do { if (cpu->env.insns_flags & flag) { features |= feature; } } while (0)
-#define GET_FEATURE2(flag, feature) \
- do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
+#define GET_FEATURE2(flags, feature) \
+ do { \
+ if ((cpu->env.insns_flags2 & flags) == flags) { \
+ features |= feature; \
+ } \
+ } while (0)
GET_FEATURE(PPC_64B, QEMU_PPC_FEATURE_64);
GET_FEATURE(PPC_FLOAT, QEMU_PPC_FEATURE_HAS_FPU);
GET_FEATURE(PPC_ALTIVEC, QEMU_PPC_FEATURE_HAS_ALTIVEC);
--
2.7.4
- [Qemu-ppc] [PULL 18/45] spapr_rtas: convert to trace framework instead of DPRINTF, (continued)
- [Qemu-ppc] [PULL 18/45] spapr_rtas: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 19/45] spapr_vio: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 20/45] spapr_llan: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 21/45] spapr_vscsi: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 24/45] target-ppc: convert ld[16, 32, 64]ur to use new macro, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 22/45] target-ppc: consolidate load operations, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 31/45] target-ppc: add xxspltib instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 36/45] target-ppc: add TLB_NEED_LOCAL_FLUSH flag, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 27/45] target-ppc: convert st[16, 32, 64]r to use new macro, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 30/45] target-ppc: consolidate store conditional, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP,
David Gibson <=
- [Qemu-ppc] [PULL 40/45] ppc/xics: account correct irq status, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 25/45] target-ppc: consolidate store operations, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 35/45] spapr: Introduce sPAPRCPUCoreClass, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 05/45] target-ppc: add vector count trailing zeros instructions, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 08/45] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 32/45] target-ppc: add lxsi[bw]zx instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 34/45] target-ppc: implement darn instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 44/45] monitor: fix crash for platforms without a CPU 0, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 06/45] target-ppc: add vector bit permute doubleword instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 28/45] target-ppc: consolidate load with reservation, David Gibson, 2016/09/23