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[Qemu-ppc] [PULL 22/44] target-ppc: consolidate load operations
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 22/44] target-ppc: consolidate load operations |
Date: |
Thu, 22 Sep 2016 16:37:20 +1000 |
From: Nikunj A Dadhania <address@hidden>
Implement macro to consolidate load operations using newer
tcg_gen_qemu_ld functions.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 58 +++++++++++++++++---------------------------------
1 file changed, 20 insertions(+), 38 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a27f455..6606969 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2462,50 +2462,32 @@ static inline void gen_align_no_le(DisasContext *ctx)
}
/*** Integer load ***/
-static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
-}
-
-static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
-}
-
-static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
-}
+#define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
-static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
+#define GEN_QEMU_LOAD_TL(ldop, op) \
+static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
+ TCGv val, \
+ TCGv addr) \
+{ \
+ tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
}
-static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
-{
- TCGv tmp = tcg_temp_new();
- gen_qemu_ld32u(ctx, tmp, addr);
- tcg_gen_extu_tl_i64(val, tmp);
- tcg_temp_free(tmp);
-}
+GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
+GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
+GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
+GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
+GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
-static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
+#define GEN_QEMU_LOAD_64(ldop, op) \
+static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
+ TCGv_i64 val, \
+ TCGv addr) \
+{ \
+ tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
}
-static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
-{
- TCGv tmp = tcg_temp_new();
- gen_qemu_ld32s(ctx, tmp, addr);
- tcg_gen_ext_tl_i64(val, tmp);
- tcg_temp_free(tmp);
-}
+GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
+GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
--
2.7.4
- [Qemu-ppc] [PULL 16/44] adb.c: prevent NO_KEY value from going to guest, (continued)
- [Qemu-ppc] [PULL 16/44] adb.c: prevent NO_KEY value from going to guest, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 15/44] adb.c: correct several key assignments, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 09/44] qtest: replace strtoXX() by qemu_strtoXX(), David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 33/44] target-ppc: add stxsi[bh]x instruction, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 34/44] target-ppc: implement darn instruction, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 42/44] ppc/kvm: Mark 64kB page size support as disabled if not available, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 43/44] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 26/44] target-ppc: convert st64 to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 23/44] target-ppc: convert ld64 to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 08/44] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 22/44] target-ppc: consolidate load operations,
David Gibson <=
- [Qemu-ppc] [PULL 27/44] target-ppc: convert st[16, 32, 64]r to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 14/44] adb.c: add support for QKeyCode, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 25/44] target-ppc: consolidate store operations, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 41/44] ppc/xics: An ICS with offset 0 is assumed to be uninitialized, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 24/44] target-ppc: convert ld[16, 32, 64]ur to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 30/44] target-ppc: consolidate store conditional, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 29/44] target-ppc: move out stqcx impementation, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 44/44] monitor: fix crash for platforms without a CPU 0, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 39/44] Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64., David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 03/44] target-ppc: add vector insert instructions, David Gibson, 2016/09/22