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[Qemu-ppc] [PULL 50/64] target-ppc: add vsrv instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 50/64] target-ppc: add vsrv instruction |
Date: |
Wed, 7 Sep 2016 20:29:29 +1000 |
From: Vivek Andrew Sha <address@hidden>
Adds Vector Shift Right Variable instruction.
Signed-off-by: Vivek Andrew Sha <address@hidden>
[ reverse the order of computation to avoid temporary array ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 17 +++++++++++++++++
target-ppc/translate/vmx-impl.c | 1 +
target-ppc/translate/vmx-ops.c | 1 +
4 files changed, 20 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9703f85..8eada2f 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_3(vsld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vsrv, void, avr, avr, avr)
DEF_HELPER_3(vslv, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 12fe144..552b2e0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1710,6 +1710,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t
*b)
}
}
+void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ unsigned int shift, bytes;
+
+ /* Use reverse order, as destination and source register can be same. Its
+ * being modified in place saving temporary, reverse order will guarantee
+ * that computed result is not fed back.
+ */
+ for (i = ARRAY_SIZE(r->u8) - 1; i >= 0; i--) {
+ shift = b->u8[i] & 0x7; /* extract shift value */
+ bytes = ((i ? a->u8[i - 1] : 0) << 8) + a->u8[i];
+ /* extract adjacent bytes */
+ r->u8[i] = (bytes >> shift) & 0xFF; /* shift and store result */
+ }
+}
+
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
{
int sh = shift & 0xf;
diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
index e979668..b984122 100644
--- a/target-ppc/translate/vmx-impl.c
+++ b/target-ppc/translate/vmx-impl.c
@@ -383,6 +383,7 @@ GEN_VXFORM(vsrab, 2, 12);
GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vsrad, 2, 15);
+GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
index 61e08b2..2a9f225 100644
--- a/target-ppc/translate/vmx-ops.c
+++ b/target-ppc/translate/vmx-ops.c
@@ -110,6 +110,7 @@ GEN_VXFORM(vsrab, 2, 12),
GEN_VXFORM(vsrah, 2, 13),
GEN_VXFORM(vsraw, 2, 14),
GEN_VXFORM_207(vsrad, 2, 15),
+GEN_VXFORM_300(vsrv, 2, 28),
GEN_VXFORM_300(vslv, 2, 29),
GEN_VXFORM(vslo, 6, 16),
GEN_VXFORM(vsro, 6, 17),
--
2.7.4
- [Qemu-ppc] [PULL 07/64] target-ppc: add modulo word operations, (continued)
- [Qemu-ppc] [PULL 07/64] target-ppc: add modulo word operations, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 11/64] target-ppc: add cmpeqb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 10/64] target-ppc: add cnttzw[.] instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 02/64] hw/ppc: include fdt helper routine in a common file, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 16/64] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 26/64] ppc: FP exceptions are always precise, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 50/64] target-ppc: add vsrv instruction,
David Gibson <=
- [Qemu-ppc] [PULL 37/64] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 13/64] target-ppc: add maddld instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 41/64] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 55/64] ppc: Fix macio ESCC legacy mapping, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 44/64] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 27/64] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 39/64] ppc: Speed up dcbz, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 58/64] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 62/64] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 45/64] target-ppc: implement branch-less divd[o][.], David Gibson, 2016/09/07