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From: | ckim |
Subject: | how to access 64bit register? only lower 32 bits are written in aarch64.. |
Date: | Thu, 27 May 2021 18:54:04 +0900 |
Hi, list members, I;m faced with a problem I can’t figure out how to solve. In a baremetal program running on aarch64, I have this test code, (*(volatile uint64_t *)(AXPU_BASE + AXPU_AXEMIS_IOCTL_ARG)) = 0x99aabbccddeeff00; // addr 0x1618 printf("read-back : cmd = %lx\n", (*(volatile uint64_t *)(AXPU_BASE + AXPU_AXEMIS_IOCTL_CMD))); (*(volatile uint64_t *)(AXPU_BASE + AXPU_AXEMIS_IOCTL_CMD)) = 0x1122334455667788; // addr 0x1610 printf("read-back : arg = %lx\n", (*(volatile uint64_t *)(AXPU_BASE + AXPU_AXEMIS_IOCTL_ARG))); So it writes 0x99aabbccddeeff00 at offset 0x1618 first, and then write 0x1122334455667788 at 0x1610. In the qemu MemoryRegionOps’s write function of the device, I added the registers with some prints and writing at IOCTL_CMD register calls a function. (this is only for a temporary test). static void ab21q_axpu_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { printf("# size = %d\n", size);…. …. case REG_IOCTL_CMD: // addr 0x1610 s->ioctl_cmd = value; fprintf(stderr, "qemu written %lx at %lx\n", value, offset); //axpu_ioctl(0, value, (size_t *)s->ioctl_arg); break; case REG_IOCTL_ARG: // addr 0x1618 s->ioctl_arg = value; fprintf(stderr, "qemu written %lx at %lx\n", value, offset); break; …. } And this is the print from the run. # size = 4 qemu written ddeeff00 at 1618 # size = 4 read-back : arg = ddeeff00 # size = 4 qemu written 55667788 at 1610 # size = 4 read-back : cmd = 55667788 I wanted to write two 64-bit values but it’s writing only two 32-bit values. (for the upper 32-bit values, it doesn’t write because the address mismatch – my address are only 8byte aligned) and it’s causing a problem. Where in the qemu code should I fix so that I can write 64 bit data? And can I place 32bit registers together with 64-bit registers in a peripheral? Any help will be deeply appreciated. Thanks! Chan Kim |
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