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[PULL 040/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn
From: |
Peter Maydell |
Subject: |
[PULL 040/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn |
Date: |
Mon, 30 May 2022 17:05:51 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Convert SVE translation functions using do_sve2_zzzz_fn
to use TRANS_FEAT and gen_gvec_fn_arg_zzzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-38-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 38 ++++++--------------------------------
1 file changed, 6 insertions(+), 32 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e0b083f8615..f89c78a23e9 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -491,14 +491,6 @@ static bool trans_XAR(DisasContext *s, arg_rrri_esz *a)
return true;
}
-static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
-{
- if (!dc_isar_feature(aa64_sve2, s)) {
- return false;
- }
- return gen_gvec_fn_arg_zzzz(s, fn, a);
-}
-
static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
{
tcg_gen_xor_i64(d, n, m);
@@ -525,10 +517,7 @@ static void gen_eor3(unsigned vece, uint32_t d, uint32_t
n, uint32_t m,
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
}
-static bool trans_EOR3(DisasContext *s, arg_rrrr_esz *a)
-{
- return do_sve2_zzzz_fn(s, a, gen_eor3);
-}
+TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_eor3, a)
static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
{
@@ -556,10 +545,7 @@ static void gen_bcax(unsigned vece, uint32_t d, uint32_t
n, uint32_t m,
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
}
-static bool trans_BCAX(DisasContext *s, arg_rrrr_esz *a)
-{
- return do_sve2_zzzz_fn(s, a, gen_bcax);
-}
+TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bcax, a)
static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
uint32_t a, uint32_t oprsz, uint32_t maxsz)
@@ -568,10 +554,7 @@ static void gen_bsl(unsigned vece, uint32_t d, uint32_t n,
uint32_t m,
tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz);
}
-static bool trans_BSL(DisasContext *s, arg_rrrr_esz *a)
-{
- return do_sve2_zzzz_fn(s, a, gen_bsl);
-}
+TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a)
static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
{
@@ -606,10 +589,7 @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t
n, uint32_t m,
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
}
-static bool trans_BSL1N(DisasContext *s, arg_rrrr_esz *a)
-{
- return do_sve2_zzzz_fn(s, a, gen_bsl1n);
-}
+TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a)
static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
{
@@ -653,10 +633,7 @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t
n, uint32_t m,
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
}
-static bool trans_BSL2N(DisasContext *s, arg_rrrr_esz *a)
-{
- return do_sve2_zzzz_fn(s, a, gen_bsl2n);
-}
+TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a)
static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
{
@@ -685,10 +662,7 @@ static void gen_nbsl(unsigned vece, uint32_t d, uint32_t
n, uint32_t m,
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
}
-static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
-{
- return do_sve2_zzzz_fn(s, a, gen_nbsl);
-}
+TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a)
/*
*** SVE Integer Arithmetic - Unpredicated Group
--
2.25.1
- [PULL 029/117] target/arm: Introduce gen_gvec_ool_arg_zpzz, (continued)
- [PULL 029/117] target/arm: Introduce gen_gvec_ool_arg_zpzz, Peter Maydell, 2022/05/30
- [PULL 024/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz, Peter Maydell, 2022/05/30
- [PULL 034/117] target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz, Peter Maydell, 2022/05/30
- [PULL 039/117] target/arm: Introduce gen_gvec_fn_arg_zzzz, Peter Maydell, 2022/05/30
- [PULL 026/117] target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi, Peter Maydell, 2022/05/30
- [PULL 031/117] target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool, Peter Maydell, 2022/05/30
- [PULL 033/117] target/arm: Move null function and sve check into gen_gvec_fn_zzz, Peter Maydell, 2022/05/30
- [PULL 032/117] target/arm: Merge gen_gvec_fn_zz into do_mov_z, Peter Maydell, 2022/05/30
- [PULL 035/117] target/arm: More use of gen_gvec_fn_arg_zzz, Peter Maydell, 2022/05/30
- [PULL 036/117] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz, Peter Maydell, 2022/05/30
- [PULL 040/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn,
Peter Maydell <=
- [PULL 028/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzp, Peter Maydell, 2022/05/30
- [PULL 041/117] target/arm: Introduce gen_gvec_fn_zzi, Peter Maydell, 2022/05/30
- [PULL 037/117] target/arm: Use TRANS_FEAT for do_sve2_fn_zzz, Peter Maydell, 2022/05/30
- [PULL 047/117] target/arm: Use TRANS_FEAT for do_shift_imm, Peter Maydell, 2022/05/30
- [PULL 053/117] target/arm: Use TRANS_FEAT for do_adr, Peter Maydell, 2022/05/30
- [PULL 055/117] target/arm: Use TRANS_FEAT for RDFFR, WRFFR, Peter Maydell, 2022/05/30
- [PULL 057/117] target/arm: Use TRANS_FEAT for do_EXT, Peter Maydell, 2022/05/30
- [PULL 038/117] target/arm: Use TRANS_FEAT for RAX1, Peter Maydell, 2022/05/30
- [PULL 044/117] target/arm: Introduce gen_gvec_fn_arg_zzi, Peter Maydell, 2022/05/30
- [PULL 048/117] target/arm: Introduce do_shift_zpzi, Peter Maydell, 2022/05/30