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[PULL 18/34] target/ppc: declare xxextractuw and xxinsertw helpers with
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From: |
Daniel Henrique Barboza |
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Subject: |
[PULL 18/34] target/ppc: declare xxextractuw and xxinsertw helpers with call flags |
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Date: |
Thu, 26 May 2022 18:37:59 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Move xxextractuw and xxinsertw to decodetree, declare both helpers with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-9-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/helper.h | 4 +-
target/ppc/insn32.decode | 9 +++-
target/ppc/int_helper.c | 6 +--
target/ppc/translate/vsx-impl.c.inc | 67 +++++++++++++----------------
target/ppc/translate/vsx-ops.c.inc | 2 -
5 files changed, 41 insertions(+), 47 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index aed1b24fdb..640a70cd5c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -528,9 +528,9 @@ DEF_HELPER_FLAGS_2(XXGENPCVDM_be_exp, TCG_CALL_NO_RWG,
void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVDM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVDM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVDM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
-DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
+DEF_HELPER_FLAGS_3(XXEXTRACTUW, TCG_CALL_NO_RWG, void, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXPERMX, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, tl)
-DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
+DEF_HELPER_FLAGS_3(XXINSERTW, TCG_CALL_NO_RWG, void, vsr, vsr, i32)
DEF_HELPER_FLAGS_2(XVXSIGSP, TCG_CALL_NO_RWG, void, vsr, vsr)
DEF_HELPER_FLAGS_5(XXEVAL, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXBLENDVB, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 483349ff6d..435cf1320c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -161,8 +161,10 @@
&XX2 xt xb
@XX2 ...... ..... ..... ..... ......... .. &XX2 xt=%xx_xt
xb=%xx_xb
-&XX2_uim2 xt xb uim:uint8_t
-@XX2_uim2 ...... ..... ... uim:2 ..... ......... .. &XX2_uim2
xt=%xx_xt xb=%xx_xb
+&XX2_uim xt xb uim:uint8_t
+@XX2_uim2 ...... ..... ... uim:2 ..... ......... .. &XX2_uim
xt=%xx_xt xb=%xx_xb
+
+@XX2_uim4 ...... ..... . uim:4 ..... ......... .. &XX2_uim
xt=%xx_xt xb=%xx_xb
&XX2_bf_xb bf xb
@XX2_bf_xb ...... bf:3 .. ..... ..... ......... . . &XX2_bf_xb
xb=%xx_xb
@@ -666,6 +668,9 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . .
@XX2_uim2
## VSX Permute Instructions
+XXEXTRACTUW 111100 ..... - .... ..... 010100101 .. @XX2_uim4
+XXINSERTW 111100 ..... - .... ..... 010110101 .. @XX2_uim4
+
XXPERM 111100 ..... ..... ..... 00011010 ... @XX3
XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3
XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ... @XX3_dm
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 8c1674510b..9a361ad241 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1647,8 +1647,7 @@ VSTRI(VSTRIHL, H, 8, true)
VSTRI(VSTRIHR, H, 8, false)
#undef VSTRI
-void helper_xxextractuw(CPUPPCState *env, ppc_vsr_t *xt,
- ppc_vsr_t *xb, uint32_t index)
+void helper_XXEXTRACTUW(ppc_vsr_t *xt, ppc_vsr_t *xb, uint32_t index)
{
ppc_vsr_t t = { };
size_t es = sizeof(uint32_t);
@@ -1663,8 +1662,7 @@ void helper_xxextractuw(CPUPPCState *env, ppc_vsr_t *xt,
*xt = t;
}
-void helper_xxinsertw(CPUPPCState *env, ppc_vsr_t *xt,
- ppc_vsr_t *xb, uint32_t index)
+void helper_XXINSERTW(ppc_vsr_t *xt, ppc_vsr_t *xb, uint32_t index)
{
ppc_vsr_t t = *xt;
size_t es = sizeof(uint32_t);
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index ca11e2c4b8..900c1a1ab2 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1585,7 +1585,7 @@ static bool trans_XXSEL(DisasContext *ctx, arg_XX4 *a)
return true;
}
-static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2_uim2 *a)
+static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2_uim *a)
{
int tofs, bofs;
@@ -1795,42 +1795,35 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_EXTRACT_INSERT(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr xt, xb; \
- TCGv_i32 t0; \
- TCGv_i64 t1; \
- uint8_t uimm = UIMM4(ctx->opcode); \
- \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xt = gen_vsr_ptr(xT(ctx->opcode)); \
- xb = gen_vsr_ptr(xB(ctx->opcode)); \
- t0 = tcg_temp_new_i32(); \
- t1 = tcg_temp_new_i64(); \
- /* \
- * uimm > 15 out of bound and for \
- * uimm > 12 handle as per hardware in helper \
- */ \
- if (uimm > 15) { \
- tcg_gen_movi_i64(t1, 0); \
- set_cpu_vsr(xT(ctx->opcode), t1, true); \
- set_cpu_vsr(xT(ctx->opcode), t1, false); \
- return; \
- } \
- tcg_gen_movi_i32(t0, uimm); \
- gen_helper_##name(cpu_env, xt, xb, t0); \
- tcg_temp_free_ptr(xb); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_i32(t0); \
- tcg_temp_free_i64(t1); \
-}
-
-VSX_EXTRACT_INSERT(xxextractuw)
-VSX_EXTRACT_INSERT(xxinsertw)
+static bool do_vsx_extract_insert(DisasContext *ctx, arg_XX2_uim *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i32))
+{
+ TCGv_i64 zero = tcg_constant_i64(0);
+ TCGv_ptr xt, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ /*
+ * uim > 15 out of bound and for
+ * uim > 12 handle as per hardware in helper
+ */
+ if (a->uim > 15) {
+ set_cpu_vsr(a->xt, zero, true);
+ set_cpu_vsr(a->xt, zero, false);
+ } else {
+ xt = gen_vsr_ptr(a->xt);
+ xb = gen_vsr_ptr(a->xb);
+ gen_helper(xt, xb, tcg_constant_i32(a->uim));
+ tcg_temp_free_ptr(xb);
+ tcg_temp_free_ptr(xt);
+ }
+
+ return true;
+}
+
+TRANS(XXEXTRACTUW, do_vsx_extract_insert, gen_helper_XXEXTRACTUW)
+TRANS(XXINSERTW, do_vsx_extract_insert, gen_helper_XXINSERTW)
#ifdef TARGET_PPC64
static void gen_xsxexpdp(DisasContext *ctx)
diff --git a/target/ppc/translate/vsx-ops.c.inc
b/target/ppc/translate/vsx-ops.c.inc
index 4524c5b02a..bff14bbece 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -320,5 +320,3 @@ VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
-GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
-GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
--
2.36.1
- [PULL 11/34] target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWG, (continued)
- [PULL 11/34] target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWG, Daniel Henrique Barboza, 2022/05/26
- [PULL 15/34] target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper, Daniel Henrique Barboza, 2022/05/26
- [PULL 16/34] target/ppc: declare xscvspdpn helper with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 17/34] target/ppc: declare xvxsigsp helper with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 22/34] target/ppc: declare vmsumsh[ms] helper with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 12/34] target/ppc: use TCG_CALL_NO_RWG in vector helpers without env, Daniel Henrique Barboza, 2022/05/26
- [PULL 14/34] target/ppc: use TCG_CALL_NO_RWG in VSX helpers without env, Daniel Henrique Barboza, 2022/05/26
- [PULL 19/34] target/ppc: introduce do_va_helper, Daniel Henrique Barboza, 2022/05/26
- [PULL 25/34] tcg/ppc: Optimize memory ordering generation with lwsync, Daniel Henrique Barboza, 2022/05/26
- [PULL 20/34] target/ppc: declare vmsum[um]bm helpers with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 18/34] target/ppc: declare xxextractuw and xxinsertw helpers with call flags,
Daniel Henrique Barboza <=
- [PULL 24/34] tcg/ppc: ST_ST memory ordering is not provided with eieio, Daniel Henrique Barboza, 2022/05/26
- [PULL 26/34] target/ppc: Implement lwsync with weaker memory ordering, Daniel Henrique Barboza, 2022/05/26
- [PULL 21/34] target/ppc: declare vmsumuh[ms] helper with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 23/34] target/ppc: Fix eieio memory ordering semantics, Daniel Henrique Barboza, 2022/05/26
- [PULL 27/34] target/ppc: Implement xxm[tf]acc and xxsetaccz, Daniel Henrique Barboza, 2022/05/26
- [PULL 28/34] target/ppc: Implemented xvi*ger* instructions, Daniel Henrique Barboza, 2022/05/26
- [PULL 29/34] target/ppc: Implemented pmxvi*ger* instructions, Daniel Henrique Barboza, 2022/05/26
- [PULL 30/34] target/ppc: Implemented xvf*ger*, Daniel Henrique Barboza, 2022/05/26
- [PULL 31/34] target/ppc: Implemented xvf16ger*, Daniel Henrique Barboza, 2022/05/26
- [PULL 32/34] target/ppc: Implemented pmxvf*ger*, Daniel Henrique Barboza, 2022/05/26