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[PULL 17/23] target/riscv: Fix csr number based privilege checking
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From: |
Alistair Francis |
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Subject: |
[PULL 17/23] target/riscv: Fix csr number based privilege checking |
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Date: |
Wed, 25 May 2022 08:44:22 +1000 |
From: Anup Patel <apatel@ventanamicro.com>
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0d5bc2f41d..6dbe9b541f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3139,7 +3139,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
int read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
#if !defined(CONFIG_USER_ONLY)
- int effective_priv = env->priv;
+ int csr_priv, effective_priv = env->priv;
if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
/*
@@ -3152,7 +3152,11 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
effective_priv++;
}
- if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
+ csr_priv = get_field(csrno, 0x300);
+ if (!env->debugger && (effective_priv < csr_priv)) {
+ if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
--
2.35.3
- [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike), (continued)
- [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike), Alistair Francis, 2022/05/24
- [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan), Alistair Francis, 2022/05/24
- [PULL 08/23] target/riscv: Fix coding style on "G" expansion, Alistair Francis, 2022/05/24
- [PULL 09/23] target/riscv: Disable "G" by default, Alistair Francis, 2022/05/24
- [PULL 10/23] target/riscv: Change "G" expansion, Alistair Francis, 2022/05/24
- [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters, Alistair Francis, 2022/05/24
- [PULL 12/23] target/riscv: Move/refactor ISA extension checks, Alistair Francis, 2022/05/24
- [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors, Alistair Francis, 2022/05/24
- [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize, Alistair Francis, 2022/05/24
- [PULL 16/23] target/riscv: Fix typo of mimpid cpu option, Alistair Francis, 2022/05/24
- [PULL 17/23] target/riscv: Fix csr number based privilege checking,
Alistair Francis <=
- [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode, Alistair Francis, 2022/05/24
- [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Alistair Francis, 2022/05/24
- [PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices, Alistair Francis, 2022/05/24
- [PULL 21/23] target/riscv: add zicsr/zifencei to isa_string, Alistair Francis, 2022/05/24
- [PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01, Alistair Francis, 2022/05/24
- [PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage, Alistair Francis, 2022/05/24
- [PULL 11/23] target/riscv: FP extension requirements, Alistair Francis, 2022/05/24
- Re: [PULL 00/23] riscv-to-apply queue, Richard Henderson, 2022/05/24