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[PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spi
From: |
Alistair Francis |
Subject: |
[PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike) |
Date: |
Wed, 25 May 2022 08:44:11 +1000 |
From: Tsukasa OI <research_trasio@irq.a4lg.com>
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU configuration more generous on
virt/spike machines. It now just prints error message and quits (without
coredumps and aborts).
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 068ba3493e..e41b6aa9f0 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -230,7 +230,7 @@ static void spike_board_init(MachineState *machine)
base_hartid, &error_abort);
object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
hart_count, &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
/* Core Local Interruptor (timer and IPI) for each socket */
riscv_aclint_swi_create(
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3326f4db96..244d6408b5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1351,7 +1351,7 @@ static void virt_machine_init(MachineState *machine)
base_hartid, &error_abort);
object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
hart_count, &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
if (!kvm_enabled()) {
if (s->have_aclint) {
--
2.35.3
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2022/05/24
- [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access, Alistair Francis, 2022/05/24
- [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store, Alistair Francis, 2022/05/24
- [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp, Alistair Francis, 2022/05/24
- [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string, Alistair Francis, 2022/05/24
- [PULL 05/23] target/riscv: Add short-isa-string option, Alistair Francis, 2022/05/24
- [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike),
Alistair Francis <=
- [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan), Alistair Francis, 2022/05/24
- [PULL 08/23] target/riscv: Fix coding style on "G" expansion, Alistair Francis, 2022/05/24
- [PULL 09/23] target/riscv: Disable "G" by default, Alistair Francis, 2022/05/24
- [PULL 10/23] target/riscv: Change "G" expansion, Alistair Francis, 2022/05/24
- [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters, Alistair Francis, 2022/05/24
- [PULL 12/23] target/riscv: Move/refactor ISA extension checks, Alistair Francis, 2022/05/24
- [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors, Alistair Francis, 2022/05/24
- [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize, Alistair Francis, 2022/05/24
- [PULL 16/23] target/riscv: Fix typo of mimpid cpu option, Alistair Francis, 2022/05/24
- [PULL 17/23] target/riscv: Fix csr number based privilege checking, Alistair Francis, 2022/05/24