Re: [PATCH v3 0/3] target/ppc: Fix FPSCR.FI bit

[Daniel Henrique Barboza]

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel

On 5/17/22 13:15, Víctor Colombo wrote:
> Hello everyone,
>
> According to Power ISA, the FI bit in FPSCR is non-sticky.
> This means that if an instruction is said to modify the FI bit, then
> it should be set or cleared depending on the result of the
> instruction. Otherwise, it should be kept as was before.
>
> This patch set fixes inconsistencies found in QEMU's handling of the
> FPSCR.FI bit, where it's treating as all instructions are supposed
> to change FI.
>
> Thanks!
>
> v2:
> - move the FI change from float_inexact_excp to do_float_check_status
> - remove the setting of FI from float_overflow_excp, making
>    do_float_check_status() the only responsible for it.
> - make float_overflow_excp() return float_flag_inexact if it should
>    update the inexact flags.
> - Add patch 3, moving the renaming of sfprf to sfifprf to it
>    (previously on patch 1)
>
> v3:
> - rewrite patch 1 commit message
> - fix missing comment change in patch 3
> - add all R-b
>
> Víctor Colombo (3):
>    target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't
>    target/ppc: Fix FPSCR.FI changing in float_overflow_excp()
>    target/ppc: Rename sfprf to sfifprf where it's also used as set fi
>      flag
>
>   target/ppc/cpu.h        |   2 +
>   target/ppc/fpu_helper.c | 223 +++++++++++++++++++++-------------------
>   2 files changed, 117 insertions(+), 108 deletions(-)