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[PULL 13/22] Fix aarch64 debug register names.
From: |
Peter Maydell |
Subject: |
[PULL 13/22] Fix aarch64 debug register names. |
Date: |
Thu, 19 May 2022 18:36:42 +0100 |
From: Chris Howard <cvz185@web.de>
Give all the debug registers their correct names including the
index, rather than having multiple registers all with the
same name string, which is confusing when viewed over the
gdbstub interface.
Signed-off-by: CHRIS HOWARD <cvz185@web.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 4127D8CA-D54A-47C7-A039-0DB7361E30C0@web.de
[PMM: expanded commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 073d6509c8c..91f78c91cea 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6554,14 +6554,16 @@ static void define_debug_regs(ARMCPU *cpu)
}
for (i = 0; i < brps; i++) {
+ char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i);
+ char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i);
ARMCPRegInfo dbgregs[] = {
- { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
+ { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
.access = PL1_RW, .accessfn = access_tda,
.fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
.writefn = dbgbvr_write, .raw_writefn = raw_write
},
- { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
+ { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
.access = PL1_RW, .accessfn = access_tda,
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
@@ -6569,17 +6571,21 @@ static void define_debug_regs(ARMCPU *cpu)
},
};
define_arm_cp_regs(cpu, dbgregs);
+ g_free(dbgbvr_el1_name);
+ g_free(dbgbcr_el1_name);
}
for (i = 0; i < wrps; i++) {
+ char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i);
+ char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i);
ARMCPRegInfo dbgregs[] = {
- { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
+ { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
.access = PL1_RW, .accessfn = access_tda,
.fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
.writefn = dbgwvr_write, .raw_writefn = raw_write
},
- { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
+ { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
.access = PL1_RW, .accessfn = access_tda,
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
@@ -6587,6 +6593,8 @@ static void define_debug_regs(ARMCPU *cpu)
},
};
define_arm_cp_regs(cpu, dbgregs);
+ g_free(dbgwvr_el1_name);
+ g_free(dbgwcr_el1_name);
}
}
--
2.25.1
- [PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max, (continued)
- [PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max, Peter Maydell, 2022/05/19
- [PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters, Peter Maydell, 2022/05/19
- [PULL 09/22] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant, Peter Maydell, 2022/05/19
- [PULL 10/22] hw/intc/arm_gicv3: Support configurable number of physical priority bits, Peter Maydell, 2022/05/19
- [PULL 06/22] target/arm: Drop unsupported_encoding() macro, Peter Maydell, 2022/05/19
- [PULL 02/22] target/arm: Factor out FWB=0 specific part of combine_cacheattrs(), Peter Maydell, 2022/05/19
- [PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs(), Peter Maydell, 2022/05/19
- [PULL 11/22] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU, Peter Maydell, 2022/05/19
- [PULL 14/22] hw/adc/zynq-xadc: Use qemu_irq typedef, Peter Maydell, 2022/05/19
- [PULL 15/22] target/arm/helper.c: Delete stray obsolete comment, Peter Maydell, 2022/05/19
- [PULL 13/22] Fix aarch64 debug register names.,
Peter Maydell <=
- [PULL 18/22] hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node, Peter Maydell, 2022/05/19
- [PULL 19/22] ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY, Peter Maydell, 2022/05/19
- [PULL 20/22] target/arm: Fix PAuth keys access checks for disabled SEL2, Peter Maydell, 2022/05/19
- [PULL 17/22] hw/arm/virt: Fix incorrect non-secure flash dtb node name, Peter Maydell, 2022/05/19
- [PULL 21/22] target/arm: Enable FEAT_HCX for -cpu max, Peter Maydell, 2022/05/19
- [PULL 16/22] target/arm: Make number of counters in PMCR follow the CPU, Peter Maydell, 2022/05/19
- [PULL 22/22] target/arm: Use FIELD definitions for CPACR, CPTR_ELx, Peter Maydell, 2022/05/19
- [PULL 08/22] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1, Peter Maydell, 2022/05/19
- Re: [PULL 00/22] target-arm queue, Richard Henderson, 2022/05/19