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Re: [PATCH 2/2] target/riscv: Run extension checks for all CPUs
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 2/2] target/riscv: Run extension checks for all CPUs |
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Date: |
Tue, 17 May 2022 15:07:58 +1000 |
On Tue, May 17, 2022 at 3:02 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
>
> 在 2022/5/17 下午12:11, Alistair Francis 写道:
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > Instead of just running the extension checks for the base CPUs, instead
> > run them for all CPUs.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/cpu.c | 161 ++++++++++++++++++++++-----------------------
> > 1 file changed, 80 insertions(+), 81 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 49b844535a..ee48a18ae4 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -593,102 +593,101 @@ static void riscv_cpu_realize(DeviceState *dev,
> > Error **errp)
> > }
> > assert(env->misa_mxl_max == env->misa_mxl);
> >
> > - /* If only MISA_EXT is unset for misa, then set it from properties */
> > - if (env->misa_ext == 0) {
> > - uint32_t ext = 0;
> > + /* Do some ISA extension error checking */
> > + if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> > + error_setg(errp,
> > + "I and E extensions are incompatible");
> > + return;
> > + }
> >
> > - /* Do some ISA extension error checking */
> > - if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> > - error_setg(errp,
> > - "I and E extensions are incompatible");
> > - return;
> > - }
> > + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
> > + error_setg(errp,
> > + "Either I or E extension must be set");
> > + return;
> > + }
> >
> > - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
> > - error_setg(errp,
> > - "Either I or E extension must be set");
> > - return;
> > - }
> > + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> > + cpu->cfg.ext_a && cpu->cfg.ext_f &&
> > + cpu->cfg.ext_d &&
> > + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
> > + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
> > + cpu->cfg.ext_i = true;
> > + cpu->cfg.ext_m = true;
> > + cpu->cfg.ext_a = true;
> > + cpu->cfg.ext_f = true;
> > + cpu->cfg.ext_d = true;
> > + cpu->cfg.ext_icsr = true;
> > + cpu->cfg.ext_ifencei = true;
> > + }
>
> Maybe you can merge the changes from my first patch to here and put this
> before the check on 'I' and 'E'.
This patch causes some failures as the extensions aren't set on all
machines now, so I'm actually going to drop it
Alistair
>
> Regards,
>
> Weiwei Li
>
> >
> > - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> > - cpu->cfg.ext_a && cpu->cfg.ext_f &&
> > - cpu->cfg.ext_d &&
> > - cpu->cfg.ext_icsr &&
> > cpu->cfg.ext_ifencei)) {
> > - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
> > - cpu->cfg.ext_i = true;
> > - cpu->cfg.ext_m = true;
> > - cpu->cfg.ext_a = true;
> > - cpu->cfg.ext_f = true;
> > - cpu->cfg.ext_d = true;
> > - cpu->cfg.ext_icsr = true;
> > - cpu->cfg.ext_ifencei = true;
> > - }
> > + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> > + error_setg(errp, "F extension requires Zicsr");
> > + return;
> > + }
> >
> > - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> > - error_setg(errp, "F extension requires Zicsr");
> > - return;
> > - }
> > + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
> > + error_setg(errp, "Zfh/Zfhmin extensions require F extension");
> > + return;
> > + }
> >
> > - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
> > - error_setg(errp, "Zfh/Zfhmin extensions require F extension");
> > - return;
> > - }
> > + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
> > + error_setg(errp, "D extension requires F extension");
> > + return;
> > + }
> >
> > - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
> > - error_setg(errp, "D extension requires F extension");
> > - return;
> > - }
> > + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
> > + error_setg(errp, "V extension requires D extension");
> > + return;
> > + }
> >
> > - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
> > - error_setg(errp, "V extension requires D extension");
> > - return;
> > - }
> > + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
> > + error_setg(errp, "Zve32f/Zve64f extensions require F extension");
> > + return;
> > + }
> > +
> > + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
> > + cpu->cfg.ext_zhinxmin) {
> > + cpu->cfg.ext_zfinx = true;
> > + }
> >
> > - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) &&
> > !cpu->cfg.ext_f) {
> > - error_setg(errp, "Zve32f/Zve64f extensions require F
> > extension");
> > + if (cpu->cfg.ext_zfinx) {
> > + if (!cpu->cfg.ext_icsr) {
> > + error_setg(errp, "Zfinx extension requires Zicsr");
> > return;
> > }
> > -
> > - /* Set the ISA extensions, checks should have happened above */
> > - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
> > - cpu->cfg.ext_zhinxmin) {
> > - cpu->cfg.ext_zfinx = true;
> > + if (cpu->cfg.ext_f) {
> > + error_setg(errp,
> > + "Zfinx cannot be supported together with F extension");
> > + return;
> > }
> > + }
> >
> > - if (cpu->cfg.ext_zfinx) {
> > - if (!cpu->cfg.ext_icsr) {
> > - error_setg(errp, "Zfinx extension requires Zicsr");
> > - return;
> > - }
> > - if (cpu->cfg.ext_f) {
> > - error_setg(errp,
> > - "Zfinx cannot be supported together with F extension");
> > - return;
> > - }
> > - }
> > + if (cpu->cfg.ext_zk) {
> > + cpu->cfg.ext_zkn = true;
> > + cpu->cfg.ext_zkr = true;
> > + cpu->cfg.ext_zkt = true;
> > + }
> >
> > - if (cpu->cfg.ext_zk) {
> > - cpu->cfg.ext_zkn = true;
> > - cpu->cfg.ext_zkr = true;
> > - cpu->cfg.ext_zkt = true;
> > - }
> > + if (cpu->cfg.ext_zkn) {
> > + cpu->cfg.ext_zbkb = true;
> > + cpu->cfg.ext_zbkc = true;
> > + cpu->cfg.ext_zbkx = true;
> > + cpu->cfg.ext_zkne = true;
> > + cpu->cfg.ext_zknd = true;
> > + cpu->cfg.ext_zknh = true;
> > + }
> >
> > - if (cpu->cfg.ext_zkn) {
> > - cpu->cfg.ext_zbkb = true;
> > - cpu->cfg.ext_zbkc = true;
> > - cpu->cfg.ext_zbkx = true;
> > - cpu->cfg.ext_zkne = true;
> > - cpu->cfg.ext_zknd = true;
> > - cpu->cfg.ext_zknh = true;
> > - }
> > + if (cpu->cfg.ext_zks) {
> > + cpu->cfg.ext_zbkb = true;
> > + cpu->cfg.ext_zbkc = true;
> > + cpu->cfg.ext_zbkx = true;
> > + cpu->cfg.ext_zksed = true;
> > + cpu->cfg.ext_zksh = true;
> > + }
> >
> > - if (cpu->cfg.ext_zks) {
> > - cpu->cfg.ext_zbkb = true;
> > - cpu->cfg.ext_zbkc = true;
> > - cpu->cfg.ext_zbkx = true;
> > - cpu->cfg.ext_zksed = true;
> > - cpu->cfg.ext_zksh = true;
> > - }
> > + /* If only MISA_EXT is unset for misa, then set it from properties */
> > + if (env->misa_ext == 0) {
> > + uint32_t ext = 0;
> >
> > if (cpu->cfg.ext_i) {
> > ext |= RVI;
>
>