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[PULL v2 33/86] CXL/cxl_component: Add cxl_get_hb_cstate()
From: |
Michael S. Tsirkin |
Subject: |
[PULL v2 33/86] CXL/cxl_component: Add cxl_get_hb_cstate() |
Date: |
Mon, 16 May 2022 16:52:25 -0400 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-32-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/cxl/cxl_component.h | 2 ++
hw/pci-bridge/pci_expander_bridge.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 4f69688c47..70b5018156 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -218,4 +218,6 @@ static inline hwaddr cxl_decode_ig(int ig)
return 1 << (ig + 8);
}
+CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb);
+
#endif
diff --git a/hw/pci-bridge/pci_expander_bridge.c
b/hw/pci-bridge/pci_expander_bridge.c
index 22feda1ff0..69244decdb 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -72,6 +72,13 @@ static GList *pxb_dev_list;
#define TYPE_PXB_HOST "pxb-host"
+CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb)
+{
+ CXLHost *host = PXB_CXL_HOST(hb);
+
+ return &host->cxl_cstate;
+}
+
static int pxb_bus_num(PCIBus *bus)
{
PXBDev *pxb = convert_to_pxb(bus->parent_dev);
--
MST
- [PULL v2 22/86] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, (continued)
- [PULL v2 22/86] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Michael S. Tsirkin, 2022/05/16
- [PULL v2 23/86] hw/cxl/device: Implement get/set Label Storage Area (LSA), Michael S. Tsirkin, 2022/05/16
- [PULL v2 24/86] qtests/cxl: Add initial root port and CXL type3 tests, Michael S. Tsirkin, 2022/05/16
- [PULL v2 25/86] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Michael S. Tsirkin, 2022/05/16
- [PULL v2 26/86] acpi/cxl: Add _OSC implementation (9.14.2), Michael S. Tsirkin, 2022/05/16
- [PULL v2 27/86] acpi/cxl: Create the CEDT (9.14.1), Michael S. Tsirkin, 2022/05/16
- [PULL v2 28/86] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Michael S. Tsirkin, 2022/05/16
- [PULL v2 29/86] hw/cxl/host: Add support for CXL Fixed Memory Windows., Michael S. Tsirkin, 2022/05/16
- [PULL v2 30/86] acpi/cxl: Introduce CFMWS structures in CEDT, Michael S. Tsirkin, 2022/05/16
- [PULL v2 32/86] pci/pcie_port: Add pci_find_port_by_pn(), Michael S. Tsirkin, 2022/05/16
- [PULL v2 33/86] CXL/cxl_component: Add cxl_get_hb_cstate(),
Michael S. Tsirkin <=
- [PULL v2 31/86] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Michael S. Tsirkin, 2022/05/16
- [PULL v2 34/86] mem/cxl_type3: Add read and write functions for associated hostmem., Michael S. Tsirkin, 2022/05/16
- [PULL v2 36/86] hw/cxl/component Add a dumb HDM decoder handler, Michael S. Tsirkin, 2022/05/16
- [PULL v2 35/86] cxl/cxl-host: Add memops for CFMWS region., Michael S. Tsirkin, 2022/05/16
- [PULL v2 37/86] i386/pc: Enable CXL fixed memory windows, Michael S. Tsirkin, 2022/05/16
- [PULL v2 38/86] tests/acpi: q35: Allow addition of a CXL test., Michael S. Tsirkin, 2022/05/16
- [PULL v2 39/86] qtests/bios-tables-test: Add a test for CXL emulation., Michael S. Tsirkin, 2022/05/16
- [PULL v2 41/86] qtest/cxl: Add more complex test cases with CFMWs, Michael S. Tsirkin, 2022/05/16
- [PULL v2 40/86] tests/acpi: Add tables for CXL emulation., Michael S. Tsirkin, 2022/05/16
- [PULL v2 42/86] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Michael S. Tsirkin, 2022/05/16