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[PULL 11/91] hw/cxl/device: Timestamp implementation (8.2.9.3)
From: |
Michael S. Tsirkin |
Subject: |
[PULL 11/91] hw/cxl/device: Timestamp implementation (8.2.9.3) |
Date: |
Mon, 16 May 2022 06:36:12 -0400 |
From: Ben Widawsky <ben.widawsky@intel.com>
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/cxl/cxl_device.h | 6 ++++++
hw/cxl/cxl-mailbox-utils.c | 42 +++++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 954205653e..797a22ddb4 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -111,6 +111,12 @@ typedef struct cxl_device_state {
size_t cel_size;
};
+ struct {
+ bool set;
+ uint64_t last_set;
+ uint64_t host_set;
+ } timestamp;
+
/* memory region for persistent memory, HDM */
uint64_t pmem_size;
} CXLDeviceState;
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index fb1f53f48e..4584aa31f7 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -44,6 +44,9 @@ enum {
#define CLEAR_RECORDS 0x1
#define GET_INTERRUPT_POLICY 0x2
#define SET_INTERRUPT_POLICY 0x3
+ TIMESTAMP = 0x03,
+ #define GET 0x0
+ #define SET 0x1
};
/* 8.2.8.4.5.1 Command Return Codes */
@@ -106,9 +109,46 @@ DEFINE_MAILBOX_HANDLER_NOP(events_clear_records);
DEFINE_MAILBOX_HANDLER_ZEROED(events_get_interrupt_policy, 4);
DEFINE_MAILBOX_HANDLER_NOP(events_set_interrupt_policy);
+/* 8.2.9.3.1 */
+static ret_code cmd_timestamp_get(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
+{
+ uint64_t time, delta;
+ uint64_t final_time = 0;
+
+ if (cxl_dstate->timestamp.set) {
+ /* First find the delta from the last time the host set the time. */
+ time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ delta = time - cxl_dstate->timestamp.last_set;
+ final_time = cxl_dstate->timestamp.host_set + delta;
+ }
+
+ /* Then adjust the actual time */
+ stq_le_p(cmd->payload, final_time);
+ *len = 8;
+
+ return CXL_MBOX_SUCCESS;
+}
+
+/* 8.2.9.3.2 */
+static ret_code cmd_timestamp_set(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
+{
+ cxl_dstate->timestamp.set = true;
+ cxl_dstate->timestamp.last_set = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+ cxl_dstate->timestamp.host_set = le64_to_cpu(*(uint64_t *)cmd->payload);
+
+ *len = 0;
+ return CXL_MBOX_SUCCESS;
+}
+
static QemuUUID cel_uuid;
#define IMMEDIATE_CONFIG_CHANGE (1 << 1)
+#define IMMEDIATE_POLICY_CHANGE (1 << 3)
#define IMMEDIATE_LOG_CHANGE (1 << 4)
static struct cxl_cmd cxl_cmd_set[256][256] = {
@@ -120,6 +160,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
cmd_events_get_interrupt_policy, 0, 0 },
[EVENTS][SET_INTERRUPT_POLICY] = { "EVENTS_SET_INTERRUPT_POLICY",
cmd_events_set_interrupt_policy, 4, IMMEDIATE_CONFIG_CHANGE },
+ [TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
+ [TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8,
IMMEDIATE_POLICY_CHANGE },
};
void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
--
MST
- [PULL 00/91] virtio,pc,pci: fixes,cleanups,features, Michael S. Tsirkin, 2022/05/16
- [PULL 01/91] virtio: fix feature negotiation for ACCESS_PLATFORM, Michael S. Tsirkin, 2022/05/16
- [PULL 02/91] intel-iommu: correct the value used for error_setg_errno(), Michael S. Tsirkin, 2022/05/16
- [PULL 03/91] hw/pci/cxl: Add a CXL component type (interface), Michael S. Tsirkin, 2022/05/16
- [PULL 05/91] MAINTAINERS: Add entry for Compute Express Link Emulation, Michael S. Tsirkin, 2022/05/16
- [PULL 04/91] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5), Michael S. Tsirkin, 2022/05/16
- [PULL 07/91] hw/cxl/device: Implement the CAP array (8.2.8.1-2), Michael S. Tsirkin, 2022/05/16
- [PULL 08/91] hw/cxl/device: Implement basic mailbox (8.2.8.4), Michael S. Tsirkin, 2022/05/16
- [PULL 06/91] hw/cxl/device: Introduce a CXL device (8.2.8), Michael S. Tsirkin, 2022/05/16
- [PULL 09/91] hw/cxl/device: Add memory device utilities, Michael S. Tsirkin, 2022/05/16
- [PULL 11/91] hw/cxl/device: Timestamp implementation (8.2.9.3),
Michael S. Tsirkin <=
- [PULL 10/91] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1), Michael S. Tsirkin, 2022/05/16
- [PULL 12/91] hw/cxl/device: Add log commands (8.2.9.4) + CEL, Michael S. Tsirkin, 2022/05/16
- [PULL 13/91] hw/pxb: Use a type for realizing expanders, Michael S. Tsirkin, 2022/05/16
- [PULL 14/91] hw/pci/cxl: Create a CXL bus type, Michael S. Tsirkin, 2022/05/16
- [PULL 15/91] cxl: Machine level control on whether CXL support is enabled, Michael S. Tsirkin, 2022/05/16
- [PULL 17/91] qtest/cxl: Introduce initial test for pxb-cxl only., Michael S. Tsirkin, 2022/05/16
- [PULL 16/91] hw/pxb: Allow creation of a CXL PXB (host bridge), Michael S. Tsirkin, 2022/05/16
- [PULL 18/91] hw/cxl/rp: Add a root port, Michael S. Tsirkin, 2022/05/16
- [PULL 19/91] hw/cxl/device: Add a memory device (8.2.8.5), Michael S. Tsirkin, 2022/05/16
- [PULL 20/91] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Michael S. Tsirkin, 2022/05/16