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[PATCH qemu v3 05/10] target/riscv: rvv: Add mask agnostic for vector in
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From: |
~eopxd |
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Subject: |
[PATCH qemu v3 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions |
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Date: |
Thu, 12 May 2022 08:55:19 -0000 |
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index e41e85f4f0..ae498f6db0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1723,6 +1723,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2d3fcaefc9..429cf2cddb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1403,12 +1403,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
@@ -1461,11 +1466,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
--
2.34.2
- [PATCH qemu v3 00/10] Add mask agnostic behavior for rvv instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 03/10] target/riscv: rvv: Add mask agnostic for vx instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions,
~eopxd <=
- [PATCH qemu v3 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 01/10] target/riscv: rvv: Add mask agnostic for vv instructions, ~eopxd, 2022/05/12
- [PATCH qemu v3 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, ~eopxd, 2022/05/12
- Re: [PATCH qemu v3 00/10] Add mask agnostic behavior for rvv instructions, Weiwei Li, 2022/05/12