[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH qemu v17 09/16] target/riscv: rvv: Add tail agnostic for vector i
|
From: |
~eopxd |
|
Subject: |
[PATCH qemu v17 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions |
|
Date: |
Thu, 12 May 2022 08:26:31 -0000 |
From: eopXD <eop.chen@sifive.com>
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39865df095..8f39420dd2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1370,6 +1370,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1381,6 +1383,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1419,6 +1428,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1430,6 +1441,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.34.2
- [PATCH qemu v17 00/16] Add tail agnostic behavior for rvv instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 03/16] target/riscv: rvv: Rename ambiguous esz, ~eopxd, 2022/05/12
- [PATCH qemu v17 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 05/16] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 04/16] target/riscv: rvv: Early exit when vstart >= vl, ~eopxd, 2022/05/12
- [PATCH qemu v17 02/16] target/riscv: rvv: Prune redundant access_type parameter passed, ~eopxd, 2022/05/12
- [PATCH qemu v17 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions,
~eopxd <=
- [PATCH qemu v17 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/05/12
- [PATCH qemu v17 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior, ~eopxd, 2022/05/12
- [PATCH qemu v17 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/05/12
- [PATCH qemu v17 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/05/12