Re: [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vecto

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Re: [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vecto

From:	Weiwei Li
Subject:	Re: [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
Date:	Wed, 11 May 2022 10:28:59 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0


在 2022/3/17 下午5:08, ~eopxd 写道:

From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
  target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++++
  target/riscv/vector_helper.c            | 26 +++++++++++++++++++++++++
  2 files changed, 38 insertions(+)



Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>

Regards,
Weiwei Li


diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5cbf323c18..8fb8045957 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2428,6 +2428,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
          data =                                                     \
              FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs1),                    \
                             vreg_ofs(s, a->rs2), cpu_env,           \
@@ -2513,6 +2514,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
        \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);              \
          data = FIELD_DP32(data, VDATA, VTA_ALL_1S,                \
                            s->cfg_vta_all_1s);                     \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);              \
          return opfvf_trans(a->rd, a->rs1, a->rs2, data,           \
                             fns[s->sew - 1], s);                   \
      }                                                             \
@@ -2552,6 +2554,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
       \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);             \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
                             vreg_ofs(s, a->rs1),                  \
                             vreg_ofs(s, a->rs2), cpu_env,         \
@@ -2592,6 +2595,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
       \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);             \
          return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
                             fns[s->sew - 1], s);                  \
      }                                                            \
@@ -2629,6 +2633,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
          tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs1),                    \
                             vreg_ofs(s, a->rs2), cpu_env,           \
@@ -2669,6 +2674,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
       \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);             \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);             \
          return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
                             fns[s->sew - 1], s);                  \
      }                                                            \
@@ -2753,6 +2759,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
          data = FIELD_DP32(data, VDATA, VM, a->vm);
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
          data = FIELD_DP32(data, VDATA, VTA, s->vta);
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
                             vreg_ofs(s, a->rs2), cpu_env,
                             s->cfg_ptr->vlen / 8,
@@ -2867,6 +2874,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f 
*a)
              TCGv_i32 desc;
              uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
              data = FIELD_DP32(data, VDATA, VTA, s->vta);
+            data = FIELD_DP32(data, VDATA, VMA, s->vma);
              static gen_helper_vmv_vx * const fns[3] = {
                  gen_helper_vmv_v_x_h,
                  gen_helper_vmv_v_x_w,
@@ -2968,6 +2976,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
@@ -3021,6 +3030,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
@@ -3089,6 +3099,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
@@ -3144,6 +3155,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
          data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
                             vreg_ofs(s, a->rs2), cpu_env,           \
                             s->cfg_ptr->vlen / 8,                   \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 4e48c92617..5b9d766e0e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3053,10 +3053,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,        
  \
      uint32_t total_elems =                                \
          vext_get_total_elems(env, desc, ESZ);             \
      uint32_t vta = vext_vta(desc);                        \
+    uint32_t vma = vext_vma(desc);                        \
      uint32_t i;                                           \
                                                            \
      for (i = env->vstart; i < vl; i++) {                  \
          if (!vm && !vext_elem_mask(v0, i)) {              \
+            /* set masked-off elements to 1s */           \
+            vext_set_elems_1s(vd, vma, i * ESZ,           \
+                              (i + 1) * ESZ);             \
              continue;                                     \
          }                                                 \
          do_##NAME(vd, vs1, vs2, i, env);                  \
@@ -3092,10 +3096,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,      
  \
      uint32_t total_elems =                                \
          vext_get_total_elems(env, desc, ESZ);              \
      uint32_t vta = vext_vta(desc);                        \
+    uint32_t vma = vext_vma(desc);                        \
      uint32_t i;                                           \
                                                            \
      for (i = env->vstart; i < vl; i++) {                  \
          if (!vm && !vext_elem_mask(v0, i)) {              \
+            /* set masked-off elements to 1s */           \
+            vext_set_elems_1s(vd, vma, i * ESZ,           \
+                              (i + 1) * ESZ);             \
              continue;                                     \
          }                                                 \
          do_##NAME(vd, s1, vs2, i, env);                   \
@@ -3667,6 +3675,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
      uint32_t total_elems =                             \
          vext_get_total_elems(env, desc, ESZ);          \
      uint32_t vta = vext_vta(desc);                     \
+    uint32_t vma = vext_vma(desc);                     \
      uint32_t i;                                        \
                                                         \
      if (vl == 0) {                                     \
@@ -3674,6 +3683,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
      }                                                  \
      for (i = env->vstart; i < vl; i++) {               \
          if (!vm && !vext_elem_mask(v0, i)) {           \
+            /* set masked-off elements to 1s */        \
+            vext_set_elems_1s(vd, vma, i * ESZ,        \
+                              (i + 1) * ESZ);          \
              continue;                                  \
          }                                              \
          do_##NAME(vd, vs2, i, env);                    \
@@ -4184,12 +4196,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void 
*vs2,   \
      uint32_t vl = env->vl;                                    \
      uint32_t total_elems = env_archcpu(env)->cfg.vlen;        \
      uint32_t vta_all_1s = vext_vta_all_1s(desc);              \
+    uint32_t vma = vext_vma(desc);                            \
      uint32_t i;                                               \
                                                                \
      for (i = env->vstart; i < vl; i++) {                      \
          ETYPE s1 = *((ETYPE *)vs1 + H(i));                    \
          ETYPE s2 = *((ETYPE *)vs2 + H(i));                    \
          if (!vm && !vext_elem_mask(v0, i)) {                  \
+            /* set masked-off elements to 1s */               \
+            if (vma) {                                        \
+                vext_set_elem_mask(vd, i, 1);                 \
+            }                                                 \
              continue;                                         \
          }                                                     \
          vext_set_elem_mask(vd, i,                             \
@@ -4217,11 +4234,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void 
*vs2,       \
      uint32_t vl = env->vl;                                          \
      uint32_t total_elems = env_archcpu(env)->cfg.vlen;              \
      uint32_t vta_all_1s = vext_vta_all_1s(desc);                    \
+    uint32_t vma = vext_vma(desc);                                  \
      uint32_t i;                                                     \
                                                                      \
      for (i = env->vstart; i < vl; i++) {                            \
          ETYPE s2 = *((ETYPE *)vs2 + H(i));                          \
          if (!vm && !vext_elem_mask(v0, i)) {                        \
+            /* set masked-off elements to 1s */                     \
+            if (vma) {                                              \
+                vext_set_elem_mask(vd, i, 1);                       \
+            }                                                       \
              continue;                                               \
          }                                                           \
          vext_set_elem_mask(vd, i,                                   \
@@ -4344,10 +4366,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
      uint32_t total_elems =                             \
          vext_get_total_elems(env, desc, ESZ);          \
      uint32_t vta = vext_vta(desc);                     \
+    uint32_t vma = vext_vma(desc);                     \
      uint32_t i;                                        \
                                                         \
      for (i = env->vstart; i < vl; i++) {               \
          if (!vm && !vext_elem_mask(v0, i)) {           \
+            /* set masked-off elements to 1s */        \
+            vext_set_elems_1s(vd, vma, i * ESZ,        \
+                              (i + 1) * ESZ);          \
              continue;                                  \
          }                                              \
          do_##NAME(vd, vs2, i);                         \

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[PATCH qemu v2 00/10] Add mask agnostic behavior for rvv instructions, ~eopxd, 2022/05/10
- [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/05/10
  - Re: [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, Weiwei Li, 2022/05/10
- [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, ~eopxd, 2022/05/10
  - Re: [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, Weiwei Li <=
- [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, ~eopxd, 2022/05/10
  - Re: [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, Weiwei Li, 2022/05/10
- [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, ~eopxd, 2022/05/10
  - Re: [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, Weiwei Li, 2022/05/10
- [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/05/10
  - Re: [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, Weiwei Li, 2022/05/10
- [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/05/10
  - Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, Weiwei Li, 2022/05/10
  - Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, Weiwei Li, 2022/05/10
- [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions, ~eopxd, 2022/05/10

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