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[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
From: |
Peter Maydell |
Subject: |
[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max |
Date: |
Mon, 9 May 2022 12:58:35 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 81104080003..b200012d89b 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -25,6 +25,7 @@ the following architecture extensions:
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
- FEAT_HPDS (Hierarchical permission disables)
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+- FEAT_IESB (Implicit error synchronization event)
- FEAT_JSCVT (JavaScript conversion instructions)
- FEAT_LOR (Limited ordering regions)
- FEAT_LPA (Large Physical Address space)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 35881c74b20..10410619f90 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64mmfr2;
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
--
2.25.1
- [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c, (continued)
- [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Peter Maydell, 2022/05/09
- [PULL 09/32] target/arm: Split out aa32_max_features, Peter Maydell, 2022/05/09
- [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers, Peter Maydell, 2022/05/09
- [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes, Peter Maydell, 2022/05/09
- [PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Peter Maydell, 2022/05/09
- [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Peter Maydell, 2022/05/09
- [PULL 15/32] target/arm: Enable SCR and HCR bits for RAS, Peter Maydell, 2022/05/09
- [PULL 17/32] target/arm: Implement ESB instruction, Peter Maydell, 2022/05/09
- [PULL 16/32] target/arm: Implement virtual SError exceptions, Peter Maydell, 2022/05/09
- [PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max,
Peter Maydell <=
- [PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max, Peter Maydell, 2022/05/09
- [PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 24/32] target/arm: Define cortex-a76, Peter Maydell, 2022/05/09
- [PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max, Peter Maydell, 2022/05/09
- [PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 27/32] qapi/machine.json: Add cluster-id, Peter Maydell, 2022/05/09
- [PULL 25/32] target/arm: Define neoverse-n1, Peter Maydell, 2022/05/09
- [PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu(), Peter Maydell, 2022/05/09