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[PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2
From: |
Richard Henderson |
Subject: |
[PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2 |
Date: |
Sat, 30 Apr 2022 22:50:05 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d1b558385c..7303103016 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3704,6 +3704,11 @@ static inline bool isar_feature_aa32_ssbs(const
ARMISARegisters *id)
return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
}
+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+}
+
/*
* 64-bit feature tests via id registers.
*/
@@ -4010,6 +4015,11 @@ static inline bool isar_feature_aa64_ssbs(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
}
+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
+}
+
static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
@@ -4093,6 +4103,11 @@ static inline bool isar_feature_any_tts2uxn(const
ARMISARegisters *id)
return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
}
+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+}
+
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/
--
2.34.1
- [PATCH v4 31/45] target/arm: Enable FEAT_Debugv8p2 for -cpu max, (continued)
- [PATCH v4 31/45] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2, Richard Henderson, 2022/05/01
- [PATCH v4 38/45] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 07/45] target/arm: Change cpreg access permissions to enum, Richard Henderson, 2022/05/01
- [PATCH v4 28/45] target/arm: Split out aa32_max_features, Richard Henderson, 2022/05/01
- [PATCH v4 33/45] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/05/01
- [PATCH v4 35/45] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/05/01
- [PATCH v4 37/45] target/arm: Implement ESB instruction, Richard Henderson, 2022/05/01
- [PATCH v4 19/45] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
- [PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2,
Richard Henderson <=
- [PATCH v4 29/45] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/05/01
- [PATCH v4 36/45] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/05/01
- [PATCH v4 40/45] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 41/45] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 44/45] target/arm: Define cortex-a76, Richard Henderson, 2022/05/01
- [PATCH v4 45/45] target/arm: Define neoverse-n1, Richard Henderson, 2022/05/01
- [PATCH v4 42/45] target/arm: Enable FEAT_CSV3 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 43/45] target/arm: Enable FEAT_DGH for -cpu max, Richard Henderson, 2022/05/01