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[PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2
From: |
Richard Henderson |
Subject: |
[PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2 |
Date: |
Sat, 30 Apr 2022 22:50:06 -0700 |
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Rely on EL3-no-EL2 squashing during registration.
---
target/arm/helper.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 228472506d..a5741e0ad7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7246,11 +7246,14 @@ static const ARMCPRegInfo jazelle_regs[] = {
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
};
+static const ARMCPRegInfo contextidr_el2 = {
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
static const ARMCPRegInfo vhe_reginfo[] = {
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
- .access = PL2_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -8212,6 +8215,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
}
+ if (cpu_isar_feature(aa64_vh, cpu) ||
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
+ }
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
define_arm_cp_regs(cpu, vhe_reginfo);
}
--
2.34.1
- Re: [PATCH v4 18/45] target/arm: Reformat comments in add_cpreg_to_hashtable, (continued)
- [PATCH v4 39/45] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 34/45] target/arm: Add minimal RAS registers, Richard Henderson, 2022/05/01
- [PATCH v4 10/45] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases, Richard Henderson, 2022/05/01
- [PATCH v4 27/45] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 22/45] target/arm: Merge zcr reginfo, Richard Henderson, 2022/05/01
- [PATCH v4 31/45] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2,
Richard Henderson <=
- [PATCH v4 38/45] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/05/01
- [PATCH v4 07/45] target/arm: Change cpreg access permissions to enum, Richard Henderson, 2022/05/01
- [PATCH v4 28/45] target/arm: Split out aa32_max_features, Richard Henderson, 2022/05/01
- [PATCH v4 33/45] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/05/01
- [PATCH v4 35/45] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/05/01
- [PATCH v4 37/45] target/arm: Implement ESB instruction, Richard Henderson, 2022/05/01
- [PATCH v4 19/45] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable, Richard Henderson, 2022/05/01
- [PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2, Richard Henderson, 2022/05/01
- [PATCH v4 29/45] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/05/01