Re: [PATCH v39 05/22] target/avr: Add instruction translation - Arithmetic and Logic Instructions

[Aleksandar Markovic]

On Wednesday, December 18, 2019, Michael Rolnik <address@hidden> wrote:
> This includes:
> - ADD, ADC, ADIW
> - SBIW, SUB, SUBI, SBC, SBCI
> - AND, ANDI
> - OR, ORI, EOR
> - COM, NEG
> - INC, DEC
> - MUL, MULS, MULSU
> - FMUL, FMULS, FMULSU
> - DES

...

> +
> +/*
> + *  Performs the logical AND between the contents of register Rd and register
> + *  Rr and places the result in the destination register Rd.
> + */
> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
> +    tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */

Hi, Michael.

Please add before this line a blank line and a comment:

/* update status register */

This is needed to visually separate core functionality and updating status register in trans_AND() function.

And please repeat that for all instructions that update status register.

Regards,

Aleksandar