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[PULL 42/88] spapr/xive: Configure number of servers in KVM
From: |
David Gibson |
Subject: |
[PULL 42/88] spapr/xive: Configure number of servers in KVM |
Date: |
Tue, 17 Dec 2019 15:42:36 +1100 |
From: Greg Kurz <address@hidden>
The XIVE KVM devices now has an attribute to configure the number of
interrupt servers. This allows to greatly optimize the usage of the VP
space in the XIVE HW, and thus to start a lot more VMs.
Only set this attribute if available in order to support older POWER9
KVM.
The XIVE KVM device now reports the exhaustion of VPs upon the
connection of the first VCPU. Check that in order to have a chance
to provide a hint to the user.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/spapr_xive_kvm.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index 46c7609bd8..32b2809210 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -152,7 +152,8 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx,
Error **errp)
void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
{
- SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;
+ MachineState *ms = MACHINE(qdev_get_machine());
+ SpaprXive *xive = SPAPR_MACHINE(ms)->xive;
unsigned long vcpu_id;
int ret;
@@ -171,8 +172,16 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
ret = kvm_vcpu_enable_cap(tctx->cs, KVM_CAP_PPC_IRQ_XIVE, 0, xive->fd,
vcpu_id, 0);
if (ret < 0) {
- error_setg(errp, "XIVE: unable to connect CPU%ld to KVM device: %s",
+ Error *local_err = NULL;
+
+ error_setg(&local_err,
+ "XIVE: unable to connect CPU%ld to KVM device: %s",
vcpu_id, strerror(errno));
+ if (errno == ENOSPC) {
+ error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n",
+ ms->smp.max_cpus);
+ }
+ error_propagate(errp, local_err);
return;
}
@@ -758,6 +767,16 @@ int kvmppc_xive_connect(SpaprInterruptController *intc,
uint32_t nr_servers,
return -1;
}
+ /* Tell KVM about the # of VCPUs we may have */
+ if (kvm_device_check_attr(xive->fd, KVM_DEV_XIVE_GRP_CTRL,
+ KVM_DEV_XIVE_NR_SERVERS)) {
+ if (kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_CTRL,
+ KVM_DEV_XIVE_NR_SERVERS, &nr_servers, true,
+ &local_err)) {
+ goto fail;
+ }
+ }
+
/*
* 1. Source ESB pages - KVM mapping
*/
--
2.23.0
- [PULL 41/88] spapr/xics: Configure number of servers in KVM, (continued)
- [PULL 41/88] spapr/xics: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 33/88] ppc/pnv: Fix TIMA indirect access, David Gibson, 2019/12/16
- [PULL 29/88] ppc/pnv: Instantiate cores separately, David Gibson, 2019/12/16
- [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper, David Gibson, 2019/12/16
- [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces, David Gibson, 2019/12/16
- [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model, David Gibson, 2019/12/16
- [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, David Gibson, 2019/12/16
- [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller, David Gibson, 2019/12/16
- [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, David Gibson, 2019/12/16
- [PULL 39/88] linux-headers: Update, David Gibson, 2019/12/16
- [PULL 42/88] spapr/xive: Configure number of servers in KVM,
David Gibson <=
- [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler, David Gibson, 2019/12/16
- [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper, David Gibson, 2019/12/16
- [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper, David Gibson, 2019/12/16
- [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover, David Gibson, 2019/12/16
- [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models, David Gibson, 2019/12/16
- [PULL 57/88] xics: Don't deassert outputs, David Gibson, 2019/12/16
- [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, David Gibson, 2019/12/16
- [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper, David Gibson, 2019/12/16