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[PULL 22/88] ppc/xive: Introduce OS CAM line helpers
From: |
David Gibson |
Subject: |
[PULL 22/88] ppc/xive: Introduce OS CAM line helpers |
Date: |
Tue, 17 Dec 2019 15:42:16 +1100 |
From: Cédric Le Goater <address@hidden>
The OS CAM line has a special encoding exploited by the HW. Provide
helper routines to hide the details to the TIMA command handlers. This
also clarifies the endianness of different variables : 'qw1w2' is
big-endian and 'cam' is native.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/xive.c | 41 ++++++++++++++++++++++++++++++++++++++---
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 177663d2b4..42e9a11ef7 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -337,14 +337,49 @@ static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr
offset,
xive_tctx_notify(tctx, TM_QW1_OS);
}
+static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
+ uint32_t *nvt_idx, bool *vo)
+{
+ if (nvt_blk) {
+ *nvt_blk = xive_nvt_blk(cam);
+ }
+ if (nvt_idx) {
+ *nvt_idx = xive_nvt_idx(cam);
+ }
+ if (vo) {
+ *vo = !!(cam & TM_QW1W2_VO);
+ }
+}
+
+static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk,
+ uint32_t *nvt_idx, bool *vo)
+{
+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+ uint32_t cam = be32_to_cpu(qw1w2);
+
+ xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo);
+ return qw1w2;
+}
+
+static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
+{
+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+}
+
static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
unsigned size)
{
- uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
uint32_t qw1w2;
+ uint32_t qw1w2_new;
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
- qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
- memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+ qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);
+
+ /* Invalidate CAM line */
+ qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
+ xive_tctx_set_os_cam(tctx, qw1w2_new);
return qw1w2;
}
--
2.23.0
- [PULL 28/88] ppc/xive: Implement the XivePresenter interface, (continued)
- [PULL 28/88] ppc/xive: Implement the XivePresenter interface, David Gibson, 2019/12/16
- [PULL 16/88] ppc/pnv: Add a LPC "ranges" property, David Gibson, 2019/12/16
- [PULL 18/88] ppc/xive: Introduce helpers for the NVT id, David Gibson, 2019/12/16
- [PULL 20/88] xive/kvm: Trigger interrupts from userspace, David Gibson, 2019/12/16
- [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer, David Gibson, 2019/12/16
- [PULL 17/88] ppc/xive: Record the IPB in the associated NVT, David Gibson, 2019/12/16
- [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX, David Gibson, 2019/12/16
- [PULL 21/88] ppc/pnv: Quiesce some XIVE errors, David Gibson, 2019/12/16
- [PULL 24/88] ipmi: Add support to customize OEM functions, David Gibson, 2019/12/16
- [PULL 36/88] ppc/spapr: Implement the XiveFabric interface, David Gibson, 2019/12/16
- [PULL 22/88] ppc/xive: Introduce OS CAM line helpers,
David Gibson <=
- [PULL 25/88] ppc/pnv: Add HIOMAP commands, David Gibson, 2019/12/16
- [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper, David Gibson, 2019/12/16
- [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT, David Gibson, 2019/12/16
- [PULL 34/88] ppc/xive: Introduce a XiveFabric interface, David Gibson, 2019/12/16
- [PULL 35/88] ppc/pnv: Implement the XiveFabric interface, David Gibson, 2019/12/16
- [PULL 41/88] spapr/xics: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 33/88] ppc/pnv: Fix TIMA indirect access, David Gibson, 2019/12/16
- [PULL 29/88] ppc/pnv: Instantiate cores separately, David Gibson, 2019/12/16
- [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper, David Gibson, 2019/12/16
- [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces, David Gibson, 2019/12/16