[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty |
|
Date: |
Mon, 9 Dec 2019 10:11:53 -0800 |
Mark both sstatus and vsstatus as dirty (3).
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1a379bd2ae..1d879b34db 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -44,6 +44,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
+ bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t misa;
@@ -396,6 +397,12 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, vsstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, vsstatus));
+ }
tcg_temp_free(tmp);
}
#else
@@ -740,6 +747,11 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
+#if !defined(CONFIG_USER_ONLY)
+ ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+#else
+ ctx->virt_enabled = false;
+#endif
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
--
2.24.0
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, (continued)
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/12/09
- [PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/12/09
- [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/12/09
- [PATCH v1 23/36] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/12/09
- [PATCH v1 24/36] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/12/09
- [PATCH v1 25/36] target/riscv: Add hfence instructions, Alistair Francis, 2019/12/09
- [PATCH v1 26/36] target/riscv: Remove the hret instruction, Alistair Francis, 2019/12/09
- [PATCH v1 27/36] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/12/09
- [PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty,
Alistair Francis <=
- [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/12/09
- [PATCH v1 30/36] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/12/09
- [PATCH v1 31/36] target/riscv: Implement second stage MMU, Alistair Francis, 2019/12/09
- [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails, Alistair Francis, 2019/12/09
- [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions, Alistair Francis, 2019/12/09
- [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/12/09
- [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/12/09
- [PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/12/09
- Re: [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5, Aleksandar Markovic, 2019/12/09