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[PATCH v1 10/36] target/riscv: Print priv and virt in disas log
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 10/36] target/riscv: Print priv and virt in disas log |
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Date: |
Mon, 9 Dec 2019 10:11:06 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ab6a891dc3..1a379bd2ae 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -808,7 +808,15 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
+ RISCVCPU *rvcpu = RISCV_CPU(cpu);
+ CPURISCVState *env = &rvcpu->env;
+#endif
+
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+#ifndef CONFIG_USER_ONLY
+ qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv,
env->virt);
+#endif
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
}
--
2.24.0
- [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5, Alistair Francis, 2019/12/09
- [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong, Alistair Francis, 2019/12/09
- [PATCH v1 02/36] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/12/09
- [PATCH v1 03/36] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/12/09
- [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/12/09
- [PATCH v1 05/36] target/riscv: Add support for the new execption numbers, Alistair Francis, 2019/12/09
- [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2019/12/09
- [PATCH v1 07/36] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/12/09
- [PATCH v1 08/36] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/12/09
- [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/12/09
- [PATCH v1 10/36] target/riscv: Print priv and virt in disas log,
Alistair Francis <=
- [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/12/09
- [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/12/09
- [PATCH v1 13/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 15/36] target/riscv: Convert mstatus to pointers, Alistair Francis, 2019/12/09
- [PATCH v1 16/36] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/12/09
- [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2019/12/09
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/12/09