[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 05/11] target/arm: Add isar_feature tests for PAN + ATS1E1
From: |
Richard Henderson |
Subject: |
[PATCH 05/11] target/arm: Add isar_feature tests for PAN + ATS1E1 |
Date: |
Tue, 3 Dec 2019 14:53:27 -0800 |
Include definitions for all of the bits in ID_MMFR3.
We already have a definition for ID_AA64MMFR1.PAN.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 49dc436e5e..170dd5b124 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1694,6 +1694,15 @@ FIELD(ID_ISAR6, FHM, 8, 4)
FIELD(ID_ISAR6, SB, 12, 4)
FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_MMFR3, CMAINTVA, 0, 4)
+FIELD(ID_MMFR3, CMAINTSW, 4, 4)
+FIELD(ID_MMFR3, BPMAINT, 8, 4)
+FIELD(ID_MMFR3, MAINTBCST, 12, 4)
+FIELD(ID_MMFR3, PAN, 16, 4)
+FIELD(ID_MMFR3, COHWALK, 20, 4)
+FIELD(ID_MMFR3, CMEMSZ, 24, 4)
+FIELD(ID_MMFR3, SUPERSEC, 28, 4)
+
FIELD(ID_MMFR4, SPECSEI, 0, 4)
FIELD(ID_MMFR4, AC2, 4, 4)
FIELD(ID_MMFR4, XNX, 8, 4)
@@ -3401,6 +3410,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const
ARMISARegisters *id)
return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
}
+static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
+}
+
+static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
+}
+
/*
* 64-bit feature tests via id registers.
*/
@@ -3550,6 +3569,16 @@ static inline bool isar_feature_aa64_lor(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
}
+static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
+}
+
+static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
+}
+
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
--
2.17.1
- Re: [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1, (continued)
- [PATCH 01/11] cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN, Richard Henderson, 2019/12/03
- [PATCH 04/11] target/arm: Reduce CPSR_RESERVED, Richard Henderson, 2019/12/03
- [PATCH 06/11] target/arm: Update MSR access for PAN, Richard Henderson, 2019/12/03
- [PATCH 07/11] target/arm: Update arm_mmu_idx_el for PAN, Richard Henderson, 2019/12/03
- [PATCH 05/11] target/arm: Add isar_feature tests for PAN + ATS1E1,
Richard Henderson <=
- [PATCH 03/11] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Richard Henderson, 2019/12/03
- [PATCH 09/11] target/arm: Set PAN bit as required on exception entry, Richard Henderson, 2019/12/03
- [PATCH 08/11] target/arm: Enforce PAN semantics in get_S1prot, Richard Henderson, 2019/12/03
- [PATCH 11/11] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max, Richard Henderson, 2019/12/03
- [PATCH 10/11] target/arm: Implement ATS1E1 system registers, Richard Henderson, 2019/12/03