[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max
|
From: |
Richard Henderson |
|
Subject: |
[PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max |
|
Date: |
Mon, 2 Dec 2019 18:29:33 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a39d6fcea3..009411813f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -670,6 +670,7 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64mmfr1;
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
cpu->isar.id_aa64mmfr1 = t;
/* Replicate the same data to the 32-bit id registers. */
--
2.17.1
- Re: [PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions, (continued)
- [PATCH v4 19/40] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/12/02
- [PATCH v4 22/40] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2019/12/02
- [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2019/12/02
- [PATCH v4 24/40] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2019/12/02
- [PATCH v4 30/40] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2019/12/02
- [PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max,
Richard Henderson <=
- [PATCH v4 27/40] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2019/12/02
[PATCH v4 18/40] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2019/12/02
[PATCH v4 32/40] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2019/12/02