[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] fbe5ac: target/arm: take HSTR traps of cp15 a
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] fbe5ac: target/arm: take HSTR traps of cp15 accesses to EL... |
|
Date: |
Tue, 02 Apr 2024 04:58:20 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876
https://github.com/qemu/qemu/commit/fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and
EL0 accesses to cp15 registers. We incorrectly implemented this so
they trap to EL1 when we detect the need for a HSTR trap at code
generation time. (The check in access_check_cp_reg() which we do at
runtime to catch traps from EL0 is correctly routing them to EL2.)
Use the correct target EL when generating the code to take the trap.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2226
Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over
UNDEF-at-EL1")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240325133116.2075362-1-peter.maydell@linaro.org
Commit: aaaae12055064ed10c12d8660246f1b4aa06e5ed
https://github.com/qemu/qemu/commit/aaaae12055064ed10c12d8660246f1b4aa06e5ed
Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M docs/system/arm/sbsa.rst
Log Message:
-----------
docs: sbsa: update specs, add dt note
Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
specifications. Then BBR defines firmware interface.
Added note about DeviceTree data passed from QEMU to firmware. It is
very minimal and provides only data we use in firmware.
Added NUMA information to list of things reported by DeviceTree.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20240328163851.1386176-1-marcin.juszkiewicz@linaro.org
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 44e25fbc1900c99c91a44e532c5bd680bc403459
https://github.com/qemu/qemu/commit/44e25fbc1900c99c91a44e532c5bd680bc403459
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
If the group of the highest priority pending interrupt is disabled
via ICC_IGRPEN*, the ICC_HPPIR* registers should return
INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture
specification pseudocode functions ICC_HPPIR1_EL1[] and
HighestPriorityPendingInterrupt().)
Make HPPIR reads honour the group disable, the way we already do
when determining whether to preempt in icc_hppi_can_preempt().
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240328153333.2522667-1-peter.maydell@linaro.org
Commit: 27c335a464ef3fdaffe759e8122e3e7742e19485
https://github.com/qemu/qemu/commit/27c335a464ef3fdaffe759e8122e3e7742e19485
Author: Cédric Le Goater <clg@redhat.com>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M tests/qtest/stm32l4x5_gpio-test.c
Log Message:
-----------
tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
The test mangles the GPIO address and the pin number in the
qtest_add_data_func data parameter. Doing so, it assumes that the host
pointer size is always 64-bit, which breaks on 32-bit :
../tests/qtest/stm32l4x5_gpio-test.c: In function ‘test_gpio_output_mode’:
../tests/qtest/stm32l4x5_gpio-test.c:272:25: error: cast from pointer to
integer of different size [-Werror=pointer-to-int-cast]
272 | unsigned int pin = ((uint64_t)data) & 0xF;
| ^
../tests/qtest/stm32l4x5_gpio-test.c:273:22: error: cast from pointer to
integer of different size [-Werror=pointer-to-int-cast]
273 | uint32_t gpio = ((uint64_t)data) >> 32;
| ^
To fix, improve the mangling of the GPIO address and pin number fields
by using GPIO_SIZE so that the resulting value fits in a 32-bit pointer.
While at it, include some helpers to hide the details.
Cc: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Cc: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20240329092747.298259-1-clg@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 393770d7a02135e7468018f52da610712f151ec0
https://github.com/qemu/qemu/commit/393770d7a02135e7468018f52da610712f151ec0
Author: Cédric Le Goater <clg@redhat.com>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M hw/arm/raspi4b.c
Log Message:
-----------
raspi4b: Reduce RAM to 1Gb on 32-bit hosts
Change the board revision number and RAM size to 1Gb on 32-bit hosts.
On these systems, RAM has a 2047 MB limit and this breaks the tests.
Fixes: 7785e8ea2204 ("hw/arm: Introduce Raspberry PI 4 machine")
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20240329150155.357043-1-clg@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7fcf7575f3d201fc84ae168017ffdfd6c86257a6
https://github.com/qemu/qemu/commit/7fcf7575f3d201fc84ae168017ffdfd6c86257a6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-02 (Tue, 02 Apr 2024)
Changed paths:
M docs/system/arm/sbsa.rst
M hw/arm/raspi4b.c
M hw/intc/arm_gicv3_cpuif.c
M target/arm/tcg/translate.c
M tests/qtest/stm32l4x5_gpio-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240402' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* take HSTR traps of cp15 accesses to EL2, not EL1
* docs: sbsa: update specs, add dt note
* hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
* tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
* raspi4b: Reduce RAM to 1Gb on 32-bit hosts
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYL3J8ZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lL9D/9ayKF76MKs+oK8+uHTOLPb
# Mk71K1apgFnkzC7v9xuI76M6SzZpcKslUbieucDhkDLdVuZvlV3eUcwQGbNWu9fx
# PCkx7RmD54o+nlGxacZx4wGDfgu9j3maCVik048WxNoHb03NPahfHIb/GFRyHgt/
# TTjeqfAX7GDbHzMiGuaEJi5dLuAP0/imLt7pooJv4JRDX3CMY+tzlclU4ySMBr+S
# 0fs5oi6kZMayM8iolpSrPDQy/N3jZJpd5pNPPIcsnL5DEJHKodHbD11+Zetb1tQ7
# Tyw+x+hUb8Yx2WADVBaihYnbvakUVLt7ZzdgDENV534O/1Vmabzt14CBGTwq4faQ
# 8Hbc4e/ulhsOUlaxCDKTCuCKDW7sub7UelSz7mX6dAwcjvEi/L99dkP1wSpl0W04
# 3uTQyjDrfCOVNJ/FMYLRp5VkjwUVacbs3u3Tpe2bgRMI+hxnKZjtIMIY09q3l7em
# JrPOsiiJlVzngcQko1K0cor3p5W43HIhLUlh0RqJL/CsVhXFfHShAJowK31vGnNp
# ITklT5CWKMmogHTJycQieemhwwKaALgCUBC9TrcD1dTJe/GksYXVg6Fit7IJttBI
# zsPMM21Namtr1tKsV71xgtpDrkiWZkeFRpo/GrEf50bX1Mx7Dc8D/ons2RS0G2vo
# S13Dyt6GBtzS9M8rKX2fsQ==
# =rYVb
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 02 Apr 2024 11:23:27 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240402' of
https://git.linaro.org/people/pmaydell/qemu-arm:
raspi4b: Reduce RAM to 1Gb on 32-bit hosts
tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
docs: sbsa: update specs, add dt note
target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/6af9d12c88b9...7fcf7575f3d2
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications