[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 9352f8: coroutine: reserve 5, 000 mappings
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 9352f8: coroutine: reserve 5, 000 mappings |
|
Date: |
Fri, 22 Mar 2024 05:58:33 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9352f80cd926fe2dde7c89b93ee33bb0356ff40e
https://github.com/qemu/qemu/commit/9352f80cd926fe2dde7c89b93ee33bb0356ff40e
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2024-03-21 (Thu, 21 Mar 2024)
Changed paths:
M util/qemu-coroutine.c
Log Message:
-----------
coroutine: reserve 5,000 mappings
Daniel P. Berrangé <berrange@redhat.com> pointed out that the coroutine
pool size heuristic is very conservative. Instead of halving
max_map_count, he suggested reserving 5,000 mappings for non-coroutine
users based on observations of guests he has access to.
Fixes: 86a637e48104 ("coroutine: cap per-thread local pool size")
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20240320181232.1464819-1-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 68c9e54beae82c08c0dd433a7baed36dabb425f8
https://github.com/qemu/qemu/commit/68c9e54beae82c08c0dd433a7baed36dabb425f8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: do not enable all named features by default
Commit 3b8022269c added the capability of named features/profile
extensions to be added in riscv,isa. To do that we had to assign priv
versions for each one of them in isa_edata_arr[]. But this resulted in a
side-effect: vendor CPUs that aren't running priv_version_latest started
to experience warnings for these profile extensions [1]:
| $ qemu-system-riscv32 -M sifive_e
| qemu-system-riscv32: warning: disabling zic64b extension for hart
0x00000000 because privilege spec version does not match
| qemu-system-riscv32: warning: disabling ziccamoa extension for
hart 0x00000000 because privilege spec version does not match
This is benign as far as the CPU behavior is concerned since disabling
both extensions is a no-op (aside from riscv,isa). But the warnings are
unpleasant to deal with, especially because we're sending user warnings
for extensions that users can't enable/disable.
Instead of enabling all named features all the time, separate them by
priv version. During finalize() time, after we decided which
priv_version the CPU is running, enable/disable all the named extensions
based on the priv spec chosen. This will be enough for a bug fix, but as
a future work we should look into how we can name these extensions in a
way that we don't need an explicit ext_name => priv_ver as we're doing
here.
The named extensions being added in isa_edata_arr[] that will be
enabled/disabled based solely on priv version can be removed from
riscv_cpu_named_features[]. 'zic64b' is an extension that can be
disabled based on block sizes so it'll retain its own flag and entry.
[1] https://lists.gnu.org/archive/html/qemu-devel/2024-03/msg02592.html
Reported-by: Clément Chigot <chigot@adacore.com>
Fixes: 3b8022269c ("target/riscv: add riscv,isa to named features")
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Clément Chigot <chigot@adacore.com>
Message-ID: <20240312203214.350980-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d3646e31ce6d1e02e46e6eabdbc2e637c0cbece7
https://github.com/qemu/qemu/commit/d3646e31ce6d1e02e46e6eabdbc2e637c0cbece7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240314175704.478276-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0848f7c18ef50de9f955e7eeb4363d92766a41bf
https://github.com/qemu/qemu/commit/0848f7c18ef50de9f955e7eeb4363d92766a41bf
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
trans_rvv.c.inc: set vstart = 0 in int scalar move insns
trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f aren't
setting vstart = 0 after execution. This is usually done by a helper in
vector_helper.c but these functions don't use helpers.
We'll set vstart after any potential 'over' brconds, and that will also
mandate a mark_vs_dirty() too.
Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240314175704.478276-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 768e7b329c0be22035da077fe76221dd0a47103b
https://github.com/qemu/qemu/commit/768e7b329c0be22035da077fe76221dd0a47103b
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
vmvr_v isn't handling the case where the host might be big endian and
the bytes to be copied aren't sequential.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240314175704.478276-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7e53e3ddf6dff200098e112c5370ab16d2d5dbd1
https://github.com/qemu/qemu/commit/7e53e3ddf6dff200098e112c5370ab16d2d5dbd1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: always clear vstart in whole vec move insns
These insns have 2 paths: we'll either have vstart already cleared if
vstart_eq_zero or we'll do a brcond to check if vstart >= maxsz to call
the 'vmvr_v' helper. The helper will clear vstart if it executes until
the end, or if vstart >= vl.
For starters, the check itself is wrong: we're checking vstart >= maxsz,
when in fact we should use vstart in bytes, or 'startb' like 'vmvr_v' is
calling, to do the comparison. But even after fixing the comparison we'll
still need to clear vstart in the end, which isn't happening too.
We want to make the helpers responsible to manage vstart, including
these corner cases, precisely to avoid these situations:
- remove the wrong vstart >= maxsz cond from the translation;
- add a 'startb >= maxsz' cond in 'vmvr_v', and clear vstart if that
happens.
This way we're now sure that vstart is being cleared in the end of the
execution, regardless of the path taken.
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240314175704.478276-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 929e521a47b7110339526771720bc2096f69dddf
https://github.com/qemu/qemu/commit/929e521a47b7110339526771720bc2096f69dddf
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: always clear vstart for ldst_whole insns
Commit 8ff8ac6329 added a conditional to guard the vext_ldst_whole()
helper if vstart >= evl. But by skipping the helper we're also not
setting vstart = 0 at the end of the insns, which is incorrect.
We'll move the conditional to vext_ldst_whole(), following in line with
the removal of all brconds vstart >= vl that the next patch will do. The
idea is to make the helpers responsible for their own vstart management.
Fix ldst_whole isns by:
- remove the brcond that skips the helper if vstart is >= evl;
- vext_ldst_whole() now does an early exit with the same check, where
evl = (vlenb * nf) >> log2_esz, but the early exit will also clear
vstart.
The 'width' param is now unneeded in ldst_whole_trans() and is also
removed. It was used for the evl calculation for the brcond and has no
other use now. The 'width' is reflected in vext_ldst_whole() via
log2_esz, which is encoded by GEN_VEXT_LD_WHOLE() as
"ctzl(sizeof(ETYPE))".
Suggested-by: Max Chou <max.chou@sifive.com>
Fixes: 8ff8ac6329 ("target/riscv: rvv: Add missing early exit condition for
whole register load/store")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240314175704.478276-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: df4252b2ecaf93b601109373a17427d1867046e8
https://github.com/qemu/qemu/commit/df4252b2ecaf93b601109373a17427d1867046e8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
M target/riscv/vector_internals.c
M target/riscv/vector_internals.h
Log Message:
-----------
target/riscv/vector_helpers: do early exit when vstart >= vl
We're going to make changes that will required each helper to be
responsible for the 'vstart' management, i.e. we will relieve the
'vstart < vl' assumption that helpers have today.
Helpers are usually able to deal with vstart >= vl, i.e. doing nothing
aside from setting vstart = 0 at the end, but the tail update functions
will update the tail regardless of vstart being valid or not. Unifying
the tail update process in a single function that would handle the
vstart >= vl case isn't trivial (see [1] for more info).
This patch takes a blunt approach: do an early exit in every single
vector helper if vstart >= vl, unless the helper is guarded with
vstart_eq_zero in the translation. For those cases the helper is ready
to deal with cases where vl might be zero, i.e. throwing exceptions
based on it like vcpop_m() and first_m().
Helpers that weren't changed:
- vcpop_m(), vfirst_m(), vmsetm(), GEN_VEXT_VIOTA_M(): these are guarded
directly with vstart_eq_zero;
- GEN_VEXT_VCOMPRESS_VM(): guarded with vcompress_vm_check() that checks
vstart_eq_zero;
- GEN_VEXT_RED(): guarded with either reduction_check() or
reduction_widen_check(), both check vstart_eq_zero;
- GEN_VEXT_FRED(): guarded with either freduction_check() or
freduction_widen_check(), both check vstart_eq_zero.
Another exception is vext_ldst_whole(), who operates on effective vector
length regardless of the current settings in vtype and vl.
[1]
https://lore.kernel.org/qemu-riscv/1590234b-0291-432a-a0fa-c5a6876097bc@linux.alibaba.com/
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240314175704.478276-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b46631f1229add97189907ff8d8672353af66eb2
https://github.com/qemu/qemu/commit/b46631f1229add97189907ff8d8672353af66eb2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvvk.c.inc
Log Message:
-----------
target/riscv: remove 'over' brconds from vector trans
All helpers that rely on vstart >= vl are now doing early exits using
the VSTART_CHECK_EARLY_EXIT() macro. This macro will not only exit the
helper but also clear vstart.
We're still left with brconds that are skipping the helper, which is the
only place where we're clearing vstart. The pattern goes like this:
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
(... calls helper that clears vstart ...)
gen_set_label(over);
return true;
This means that every time we jump to 'over' we're not clearing vstart,
which is an oversight that we're doing across the board.
Instead of setting vstart = 0 manually after each 'over' jump, remove
those brconds that are skipping helpers. The exception will be
trans_vmv_s_x() and trans_vfmv_s_f(): they don't use a helper and are
already clearing vstart manually in the 'over' label.
While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240314175704.478276-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d57dfe4b37ae542cec84a0cf751ecef313614cb6
https://github.com/qemu/qemu/commit/d57dfe4b37ae542cec84a0cf751ecef313614cb6
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240314175704.478276-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bac802ada83100c0c47f64ff219aba0e5357dcbd
https://github.com/qemu/qemu/commit/bac802ada83100c0c47f64ff219aba0e5357dcbd
Author: Ivan Klokov <ivan.klokov@syntacore.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: enable 'vstart_eq_zero' in the end of insns
The vstart_eq_zero flag is updated at the beginning of the translation
phase from the env->vstart variable. During the execution phase all
functions will set env->vstart = 0 after a successful execution, but the
vstart_eq_zero flag remains the same as at the start of the block. This
will wrongly cause SIGILLs in translations that requires env->vstart = 0
and might be reading vstart_eq_zero = false.
This patch adds a new finalize_rvv_inst() helper that is called at the
end of each vector instruction that will both update vstart_eq_zero and
do a mark_vs_dirty().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240314175704.478276-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0a11629c915f61df798919db51a18ffe4649cb65
https://github.com/qemu/qemu/commit/0a11629c915f61df798919db51a18ffe4649cb65
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: optimize loops in ldst helpers
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240314175704.478276-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 078189b327ae5c5727b51ec714d9663b1d0ca3df
https://github.com/qemu/qemu/commit/078189b327ae5c5727b51ec714d9663b1d0ca3df
Author: Frank Chang <frank.chang@sifive.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc: Update APLIC IDC after claiming iforce register
Currently, QEMU only sets the iforce register to 0 and returns early
when claiming the iforce register. However, this may leave mip.meip
remains at 1 if a spurious external interrupt triggered by iforce
register is the only pending interrupt to be claimed, and the interrupt
cannot be lowered as expected.
This commit fixes this issue by calling riscv_aplic_idc_update() to
update the IDC status after the iforce register is claimed.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240321104951.12104-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c9b07fe14d3525cd3f2fc01f46eeb3d4ed7c3603
https://github.com/qemu/qemu/commit/c9b07fe14d3525cd3f2fc01f46eeb3d4ed7c3603
Author: Max Chou <max.chou@sifive.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
According to the Zvfbfmin definition in the RISC-V BF16 extensions spec,
the Zvfbfmin extension only requires either the V extension or the
Zve32f extension.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240321170929.1162507-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e06adebb08325c39e4c9b652139426c10f021abb
https://github.com/qemu/qemu/commit/e06adebb08325c39e4c9b652139426c10f021abb
Author: Irina Ryapolova <irina.ryapolova@syntacore.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Fix mode in riscv_tlb_fill
Need to convert mmu_idx to privilege mode for PMP function.
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Fixes: b297129ae1 ("target/riscv: propagate PMP permission to TLB page")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240320172828.23965-1-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 385e575cd5ab2436c123e4b7f8c9b383a64c0dbe
https://github.com/qemu/qemu/commit/385e575cd5ab2436c123e4b7f8c9b383a64c0dbe
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M hw/riscv/virt.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/kvm/kvm_riscv.h
Log Message:
-----------
target/riscv/kvm: fix timebase-frequency when using KVM acceleration
The timebase-frequency of guest OS should be the same with host
machine. The timebase-frequency value in DTS should be got from
hypervisor when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Message-ID: <20240314061510.9800-1-yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1590154ee4376819a8c6ee61e849ebf4a4e7cd02
https://github.com/qemu/qemu/commit/1590154ee4376819a8c6ee61e849ebf4a4e7cd02
Author: Song Gao <gaosong@loongson.cn>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Fix qemu-system-loongarch64 assert failed with the option
'-d int'
qemu-system-loongarch64 assert failed with the option '-d int',
the helper_idle() raise an exception EXCP_HLT, but the exception name is
undefined.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240321123606.1704900-1-gaosong@loongson.cn>
Commit: 6a91e62694624035064c58bad5b3e75924892355
https://github.com/qemu/qemu/commit/6a91e62694624035064c58bad5b3e75924892355
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M util/qemu-coroutine.c
Log Message:
-----------
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging
Pull request
I was too quick in sending the coroutine pool sizing change for -rc0 and still
needed to address feedback from Daniel Berrangé.
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmX8bOUACgkQnKSrs4Gr
# c8hcHAf/cWacqq8B6fiUVszTHBZuvOn+curY0JGjwA6D1yeWmUVkn4xk06GYA8Zc
# wrm5jTy9nznt/Es9V8DyOCgYAPyKgDsavP1uuPjLTtJnA1lXgdrjfUi7Swd4B+5r
# rBb+WJZXa9sGM8uy2wcPxTFmIgYT7u2/b8JaOnUDBIIdvhmyOBJZTOnfRzh9xCz/
# 0vmPseq7qgWJohzpx5AVcxT3BP1cRCmOw6sKyHTdughLj+DOqg0maKamLzwBnnqC
# gdJBbplXnCH+Xz4jQ9JkzV6EWOq3MxcFFszvt8Zm3OjauSKOjTyrzUNRCZcoImYh
# Ft0A5SIla3aRN+smoXC/LBKs2HnYUg==
# =CNpd
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 21 Mar 2024 17:22:45 GMT
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full]
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
coroutine: reserve 5,000 mappings
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c43af0a21b09b5a7d031606df0b169dcffe7082
https://github.com/qemu/qemu/commit/2c43af0a21b09b5a7d031606df0b169dcffe7082
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/riscv/virt.c
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/kvm/kvm-cpu.c
M target/riscv/kvm/kvm_riscv.h
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
M target/riscv/vector_internals.c
M target/riscv/vector_internals.h
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20240322' of
https://github.com/alistair23/qemu into staging
RISC-V PR for 9.0
* Do not enable all named features by default
* A range of Vector fixes
* Update APLIC IDC after claiming iforce register
* Remove the dependency of Zvfbfmin to Zfbfmin
* Fix mode in riscv_tlb_fill
* Fix timebase-frequency when using KVM acceleration
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmX9RscACgkQr3yVEwxT
# gBNaRg/+KUSF6AuY25pS7GawbufBbwWWaWN9G/inPVoCnLbeYrkB3uZw3nBd3iV8
# KiD9Azabl6TLBFC/f7eP9alNDIoSrq5EliayrlFEZIncYvig2Y3CkWUeK6oJqDp2
# Dz1Vah4IB96bU2/M9icyHkh3tnSnbhq0JrbgoAYwWutZy4ERYugTHulOGPxBj64I
# JIfb8wYqaak3Uak+g0mz/YBNHegLEDxIzIRhO4oWPE0MWKSO3t79G9qVAYi7pkFB
# ZQQasZy0h9ZpwKvVajiO8yjwh7COI0IPU+4vZNkNXue0SXQvAvcKA4DdaTwmMTio
# 9UM9HRB371F5LtJLdvAT2TR8FfW26Y7xBe458jheFOnPHKwxEFtUFCQ39UJB3bDN
# k7CYvU3GIqUJHD7PtYZfzTdYkdnIDpr9yKTPP2/nCN53FzXuJs/XTyySphJ6mZ2m
# dsr1bnJn/ncZP7W2vdWGfgQEKt2CHfE5qWM++RwhmQc+IKn2ImMA0hBsg6Gl2imB
# 9WANt3UX784VDmcwcFVgDgr6nftDs7gjVCtHAaRV7Oq2f9hcr17pRxg66mSXs0BX
# fMhcqHBe01LpZQRbaGQ0ImTQksEFyH2KTvt0kjF4SfpVzMfVOi/Zmy9goYNq4iYd
# tfucBbXVhpzbJ/9HeOzKAJQ2Wt0NyLiyDIOkWXj61WquS/0Mr9g=
# =8vP1
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 22 Mar 2024 08:52:23 GMT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240322' of https://github.com/alistair23/qemu:
target/riscv/kvm: fix timebase-frequency when using KVM acceleration
target/riscv: Fix mode in riscv_tlb_fill
target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
hw/intc: Update APLIC IDC after claiming iforce register
target/riscv/vector_helper.c: optimize loops in ldst helpers
target/riscv: enable 'vstart_eq_zero' in the end of insns
trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
target/riscv: remove 'over' brconds from vector trans
target/riscv/vector_helpers: do early exit when vstart >= vl
target/riscv: always clear vstart for ldst_whole insns
target/riscv: always clear vstart in whole vec move insns
target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
trans_rvv.c.inc: set vstart = 0 in int scalar move insns
target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
target/riscv: do not enable all named features by default
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 853546f8128476eefb701d4a55b2781bb3a46faa
https://github.com/qemu/qemu/commit/853546f8128476eefb701d4a55b2781bb3a46faa
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-22 (Fri, 22 Mar 2024)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into
staging
pull-loongarch-20240322
# -----BEGIN PGP SIGNATURE-----
#
# iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZf1WZgAKCRBAov/yOSY+
# 35zZBADDPLM3130Q/2zsGhol1C538i4+hYRbrX+OsLnlaldyE3NqCPcgaKwVE3xS
# T9aOln91rDyQedz4DVYYSx+Oa1JpRjGko957REmopL50SJOYi6n7YhHJksaUirjJ
# tMDZdPClOegieOpCu8LgJAVhaxTpZvfLedJVPt7O6Fl/uP3pLg==
# =XLqh
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 22 Mar 2024 09:59:02 GMT
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu:
target/loongarch: Fix qemu-system-loongarch64 assert failed with the option
'-d int'
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/fea445e8fe9a...853546f81284
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications