[Qemu-commits] [qemu/qemu] 3011c1: target/riscv: Update $ra with current

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[Qemu-commits] [qemu/qemu] 3011c1: target/riscv: Update $ra with current

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 3011c1: target/riscv: Update $ra with current $pc in trans...
Date:	Fri, 08 Mar 2024 03:47:45 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 3011c1dd9c807cf41997d13c9244ea4e92237575
      
https://github.com/qemu/qemu/commit/3011c1dd9c807cf41997d13c9244ea4e92237575
  Author: Jason Chien <jason.chien@sifive.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/insn_trans/trans_rvzce.c.inc

  Log Message:
  -----------
  target/riscv: Update $ra with current $pc in trans_cm_jalt()

The original implementation sets $pc to the address read from the jump
vector table first and links $ra with the address of the next instruction
after the updated $pc. After jumping to the updated $pc and executing the
next ret instruction, the program jumps to $ra, which is in the same
function currently executing, which results in an infinite loop.
This commit stores the jump address in a temporary, updates $ra with the
current $pc, and copies the temporary to $pc.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240207081820.28559-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7dd0b070fa09311a0330d0309c8cd9afeb081e79
      
https://github.com/qemu/qemu/commit/7dd0b070fa09311a0330d0309c8cd9afeb081e79
  Author: Sia Jee Heng <jeeheng.sia@starfivetech.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/acpi/aml-build.c
    M hw/arm/virt-acpi-build.c
    M include/hw/acpi/acpi-defs.h
    M include/hw/acpi/aml-build.h

  Log Message:
  -----------
  hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location

RISC-V should also generate the SPCR in a manner similar to ARM.
Therefore, instead of replicating the code, relocate this function
to the common AML build.

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240129021440.17640-2-jeeheng.sia@starfivetech.com>
[ Changes by AF:
 - Add missing Language SPCR entry
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3e6f1e61b4bc0facd13967580feed47d96a2c28c
      
https://github.com/qemu/qemu/commit/3e6f1e61b4bc0facd13967580feed47d96a2c28c
  Author: Sia Jee Heng <jeeheng.sia@starfivetech.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Generate SPCR table

Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 119ea3576b5b62c35a186e0aa8b5eef9d0d21b35
      
https://github.com/qemu/qemu/commit/119ea3576b5b62c35a186e0aa8b5eef9d0d21b35
  Author: Alexandre Ghiti <alexghiti@rivosinc.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw: riscv: Allow large kernels to boot by moving the initrd further away in 
RAM

Currently, the initrd is placed at 128MB, which overlaps with the kernel
when it is large (for example syzbot kernels are). From the kernel side,
there is no reason we could not push the initrd further away in memory
to accommodate large kernels, so move the initrd at 512MB when possible.

The ideal solution would have been to place the initrd based on the
kernel size but we actually can't since the bss size is not known when
the image is loaded by load_image_targphys_as() and the initrd would
then overlap with this section.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240206154042.514698-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0191131dbad4e9d64da6fd819184f836ac70c2a2
      
https://github.com/qemu/qemu/commit/0191131dbad4e9d64da6fd819184f836ac70c2a2
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M linux-user/syscall.c

  Log Message:
  -----------
  linux-user/riscv: Add Zicboz extensions to hwprobe

Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
This patch introduces this for QEMU's user space emulator.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240207115926.887816-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a3432cf227908f8169bfc45caa900ef29e757440
      
https://github.com/qemu/qemu/commit/a3432cf227908f8169bfc45caa900ef29e757440
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M linux-user/syscall.c

  Log Message:
  -----------
  linux-user/riscv: Sync hwprobe keys with Linux

Upstream Linux recently added many additional keys to the hwprobe API.
This patch adds support for all of them with the exception of Ztso,
which is currently not supported in QEMU.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240207115926.887816-3-christoph.muellner@vrull.eu>
[ Changes by AF:
 - Fixup whitespace
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4f6473ad6853e6a1a2fa4ed35d6331cc16949ad5
      
https://github.com/qemu/qemu/commit/4f6473ad6853e6a1a2fa4ed35d6331cc16949ad5
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()

Recent changes in options handling removed the 'mmu' default the bare
CPUs had, meaning that we must enable 'mmu' by hand when using the
rva22s64 profile CPU.

Given that this profile is setting a satp mode, it already implies that
we need a 'mmu'. Enable the 'mmu' in this case.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3b8022269c667c2c35d35e600741478c4774358c
      
https://github.com/qemu/qemu/commit/3b8022269c667c2c35d35e600741478c4774358c
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_cfg.h
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: add riscv,isa to named features

Further discussions after the introduction of rva22 support in QEMU
revealed that what we've been calling 'named features' are actually
regular extensions, with their respective riscv,isa DTs. This is
clarified in [1]. [2] is a bug tracker asking for the profile spec to be
less cryptic about it.

As far as QEMU goes we understand extensions as something that the user
can enable/disable in the command line. This isn't the case for named
features, so we'll have to reach a middle ground.

We'll keep our existing nomenclature 'named features' to refer to any
extension that the user can't control in the command line. We'll also do
the following:

- 'svade' and 'zic64b' flags are renamed to 'ext_svade' and
  'ext_zic64b'. 'ext_svade' and 'ext_zic64b' now have riscv,isa strings and
  priv_spec versions;

- skip name feature check in cpu_bump_multi_ext_priv_ver(). Now that
  named features have a riscv,isa and an entry in isa_edata_arr[] we
  don't need to gate the call to cpu_cfg_ext_get_min_version() anymore.

[1] https://github.com/riscv/riscv-profiles/issues/121
[2] https://github.com/riscv/riscv-profiles/issues/142

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a0952c15556d740a8dae88c7038ad5efe68745bc
      
https://github.com/qemu/qemu/commit/a0952c15556d740a8dae88c7038ad5efe68745bc
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_cfg.h
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: add remaining named features

The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
until now, we were implying that they were available.

We can't do this anymore since named features also has a riscv,isa
entry. Let's add them to riscv_cpu_named_features[].

Instead of adding one bool for each named feature that we'll always
implement, i.e. can't be turned off, add a 'ext_always_enabled' bool in
cpu->cfg. This bool will be set to 'true' in TCG accel init, and all
named features will point to it. This also means that KVM won't see
these features as always enable, which is our intention.

If any accelerator adds support to disable one of these features, we'll
have to promote them to regular extensions and allow users to disable it
via command line.

After this patch, here's the riscv,isa from a buildroot using the
'rva22s64' CPU:

 # cat /proc/device-tree/cpus/cpu@0/riscv,isa
rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240215223955.969568-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 148189ff1313e995a0a84957c496ff92965151a2
      
https://github.com/qemu/qemu/commit/148189ff1313e995a0a84957c496ff92965151a2
  Author: Andrew Jones <ajones@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Reset henvcfg to zero

The hypervisor should decide what it wants to enable. Zero all
configuration enable bits on reset.

Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
svadu extension") missed one reference to 'hade'. Change it now.

Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address 
translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 70d22fd92c3bacd15e6ba423999a1cf4a5e2e819
      
https://github.com/qemu/qemu/commit/70d22fd92c3bacd15e6ba423999a1cf4a5e2e819
  Author: Andrew Jones <ajones@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_helper.c
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: Gate hardware A/D PTE bit updating

Gate hardware A/D PTE bit updating on {m,h}envcfg.ADUE and only
enable menvcfg.ADUE on reset if svade has not been selected. Now
that we also consider svade, we have four possible configurations:

 1) !svade && !svadu
    use hardware updating and there's no way to disable it
    (the default, which maintains past behavior. Maintaining
     the default, even with !svadu is a change that fixes [1])

 2) !svade && svadu
    use hardware updating, but also provide {m,h}envcfg.ADUE,
    allowing software to switch to exception mode
    (being able to switch is a change which fixes [1])

 3) svade && !svadu
    use exception mode and there's no way to switch to hardware
    updating
    (this behavior change fixes [2])

 4) svade && svadu
    use exception mode, but also provide {m,h}envcfg.ADUE,
    allowing software to switch to hardware updating
    (this behavior change fixes [2])

Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address 
translation") [1]
Fixes: 48531f5adb2a ("target/riscv: implement svade") [2]
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: adb49752dd18e556427c634ed1d3570378e87819
      
https://github.com/qemu/qemu/commit/adb49752dd18e556427c634ed1d3570378e87819
  Author: Andrew Jones <ajones@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: Promote svade to a normal extension

Named features are extensions which don't make sense for users to
control and are therefore not exposed on the command line. However,
svade is an extension which makes sense for users to control, so treat
it like a "normal" extension. The default is false, even for the max
cpu type, since QEMU has always implemented hardware A/D PTE bit
updating, so users must opt into svade (or get it from a CPU type
which enables it by default).

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 57020a464c1c8ff1d40a94a4eca6c6955ca0a6e1
      
https://github.com/qemu/qemu/commit/57020a464c1c8ff1d40a94a4eca6c6955ca0a6e1
  Author: Irina Ryapolova <irina.ryapolova@syntacore.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: FIX xATP_MODE validation

The SATP register is an SXLEN-bit read/write WARL register. It means that CSR 
fields are only defined
for a subset of bit encodings, but allow any value to be written while 
guaranteeing to return a legal
value whenever read (See riscv-privileged-20211203, SATP CSR).

For example on rv64 we are trying to write to SATP CSR val = 0x1000000000000000 
(SATP_MODE = 1 - Reserved for standard use)
and after that we are trying to read SATP_CSR. We read from the SATP CSR value 
= 0x1000000000000000, which is not a correct
operation (return illegal value).

Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240109145923.37893-1-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1349f969520856bb1310dbe264e54ad29b7ff352
      
https://github.com/qemu/qemu/commit/1349f969520856bb1310dbe264e54ad29b7ff352
  Author: Irina Ryapolova <irina.ryapolova@syntacore.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: UPDATE xATP write CSR

Added xATP_MODE validation for vsatp/hgatp CSRs.
The xATP register is an SXLEN-bit read/write WARL register, so
the legal value must be returned (See riscv-privileged-20211203, 
SATP/VSATP/HGATP CSRs).

Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240109145923.37893-2-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ef8cabab3c3ab91fd2ff098537eee6a433b36b4c
      
https://github.com/qemu/qemu/commit/ef8cabab3c3ab91fd2ff098537eee6a433b36b4c
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/pmu.h

  Log Message:
  -----------
  target/riscv: Add missing include guard in pmu.h

Add missing include guard in pmu.h to avoid the problem of double
inclusion.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240220110907.10479-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a29f5b957644dd0f14a43c8719b18c134875195c
      
https://github.com/qemu/qemu/commit/a29f5b957644dd0f14a43c8719b18c134875195c
  Author: Haibo Xu <haibo1.xu@intel.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables

Enable ACPI NUMA support by adding the following 2 ACPI tables:
SRAT: provides the association for memory/Harts and Proximity Domains
SLIT: provides the relative distance between Proximity Domains

The SRAT RINTC Affinity Structure definition[1] was based on the recently
approved ACPI CodeFirst ECR[2].

[1] https://github.com/riscv-non-isa/riscv-acpi/issues/25
[2] https://mantis.uefi.org/mantis/view.php?id=2433

Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240129094200.3581037-1-haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3fe8896536d39824272c61c5708ef547faa2e87a
      
https://github.com/qemu/qemu/commit/3fe8896536d39824272c61c5708ef547faa2e87a
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier

Hotplugged FDT nodes will attempt to write this node that, at this
moment, is being created only in create_fdt_pcie() during
finalize_fdt().

Create it earlier.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240217192607.32565-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7778cddddaeea98920589bb7ba91effd78f0cf04
      
https://github.com/qemu/qemu/commit/7778cddddaeea98920589bb7ba91effd78f0cf04
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt.c: add virtio-iommu-pci hotplug support

We want to add a RISC-V 'virt' libqos machine to increase our test
coverage. Some of the tests will try to plug a virtio-iommu-pci
device into the board and do some tests with it.

Enable virtio-iommu-pci in the 'virt' machine.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240217192607.32565-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f2d44e9c1e530ee5005e650c91c28107f615c6ae
      
https://github.com/qemu/qemu/commit/f2d44e9c1e530ee5005e650c91c28107f615c6ae
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt.c: make aclint compatible with 'qtest' accel

The 'virt' machine makes assumptions on the Advanced Core-Local
Interruptor, or aclint, based on 'tcg_enabled()' conditionals.  This
will impact MSI related tests support when adding a RISC-V 'virt' libqos
machine. The accelerator used in that case, 'qtest', isn't being
accounted for and we'll error out if we try to enable aclint.

Create a new virt_aclint_allowed() helper to gate the aclint code
considering both TCG and 'qtest' accelerators. The error message is
left untouched, mentioning TCG only, because we don't expect the
regular user to be aware of 'qtest'.

We want to add 'qtest' support for aclint only, leaving the TCG specific
bits out of it. This is done by changing the current format we use
today:

if (tcg_enabled()) {
   if (s->have_aclint) { - aclint logic - }
   else { - non-aclint, TCG logic - }
}

into:

if (virt_aclint_allowed() && s->have_aclint) {
 - aclint logic -
} else if (tcg_enabled()) {
 - non-aclint, TCG logic -
}

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240217192607.32565-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4c1608caa4d567de5e73265ac79fdfd517a4189a
      
https://github.com/qemu/qemu/commit/4c1608caa4d567de5e73265ac79fdfd517a4189a
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M tests/qtest/libqos/meson.build
    A tests/qtest/libqos/riscv-virt-machine.c

  Log Message:
  -----------
  tests/libqos: add riscv/virt machine nodes

Add a RISC-V 'virt' machine to the graph. This implementation is a
modified copy of the existing arm machine in arm-virt-machine.c

It contains a virtio-mmio and a generic-pcihost controller. The
generic-pcihost controller hardcodes assumptions from the ARM 'virt'
machine, like ecam and pio_base addresses, so we'll add an extra step to
set its parameters after creating it.

Our command line is incremented with 'aclint' parameters to allow the
machine to run MSI tests.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240217192607.32565-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 09c4e887595a5df9d80006a3632d43249b986c54
      
https://github.com/qemu/qemu/commit/09c4e887595a5df9d80006a3632d43249b986c54
  Author: Palmer Dabbelt <palmer@rivosinc.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_cfg.h
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Add support for Ztso

The Ztso extension is already ratified, this adds it as a CPU property
and adds various fences throughout the port in order to allow TSO
targets to function on weaker hosts.  We need no fences for AMOs as
they're already SC, the places we need barriers are described.
These fences are placed in the RISC-V backend rather than TCG as is
planned for x86-on-arm64 because RISC-V allows heterogeneous (and
likely soon dynamic) hart memory models.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240207122256.902627-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4f1a53b362c52707c100c493a5a67108f62d65b1
      
https://github.com/qemu/qemu/commit/4f1a53b362c52707c100c493a5a67108f62d65b1
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M linux-user/syscall.c

  Log Message:
  -----------
  linux-user/riscv: Add Ztso extension to hwprobe

This patch exposes Ztso via hwprobe in QEMU's user space emulator.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240207122256.902627-3-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e73d59675ded3690893550777056412be95ea16f
      
https://github.com/qemu/qemu/commit/e73d59675ded3690893550777056412be95ea16f
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M tests/tcg/riscv64/Makefile.target

  Log Message:
  -----------
  tests: riscv64: Use 'zfa' instead of 'Zfa'

Running test-fcvtmod triggers the following deprecation warning:
  warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead
Let's fix that.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240229180656.1208881-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6a02465f917d549c7ea8e0ca799724fb818e1120
      
https://github.com/qemu/qemu/commit/6a02465f917d549c7ea8e0ca799724fb818e1120
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M include/standard-headers/drm/drm_fourcc.h
    M include/standard-headers/linux/ethtool.h
    M include/standard-headers/linux/virtio_config.h
    M include/standard-headers/linux/virtio_pci.h
    M include/standard-headers/linux/virtio_pmem.h
    M linux-headers/asm-generic/unistd.h
    M linux-headers/asm-mips/mman.h
    M linux-headers/asm-mips/unistd_n32.h
    M linux-headers/asm-mips/unistd_n64.h
    M linux-headers/asm-mips/unistd_o32.h
    M linux-headers/asm-powerpc/unistd_32.h
    M linux-headers/asm-powerpc/unistd_64.h
    M linux-headers/asm-riscv/kvm.h
    M linux-headers/asm-s390/unistd_32.h
    M linux-headers/asm-s390/unistd_64.h
    M linux-headers/asm-x86/kvm.h
    M linux-headers/asm-x86/unistd_32.h
    M linux-headers/asm-x86/unistd_64.h
    M linux-headers/asm-x86/unistd_x32.h
    M linux-headers/linux/iommufd.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/userfaultfd.h
    M linux-headers/linux/vfio.h

  Log Message:
  -----------
  linux-headers: Update to Linux v6.8-rc6

The idea with this update is to get the latest KVM caps for RISC-V.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240304134732.386590-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3108e2f1c69d602a8916c68c861505c0953098ca
      
https://github.com/qemu/qemu/commit/3108e2f1c69d602a8916c68c861505c0953098ca
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: update KVM exts to Linux 6.8

The last KVM extensions added were back in 6.6. Sync them to Linux 6.8.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240304134732.386590-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 249e0905d0536a2431d093510bb3580eca9caac1
      
https://github.com/qemu/qemu/commit/249e0905d0536a2431d093510bb3580eca9caac1
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: move ratified/frozen exts to non-experimental

smaia and ssaia were ratified in August 25th 2023 [1].

zvfh and zvfhmin were ratified in August 2nd 2023 [2].

zfbfmin and zvfbf(min|wma) are frozen and moved to public review since
Dec 16th 2023 [3].

zaamo and zalrsc are both marked as "Frozen" since January 24th 2024
[4].

[1] https://jira.riscv.org/browse/RVS-438
[2] https://jira.riscv.org/browse/RVS-871
[3] https://jira.riscv.org/browse/RVS-704
[4] https://jira.riscv.org/browse/RVS-1995

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240301144053.265964-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e231ec8f677d94ee38316bce8e8bad3e324b0434
      
https://github.com/qemu/qemu/commit/e231ec8f677d94ee38316bce8e8bad3e324b0434
  Author: Vadim Shakirov <vadim.shakirov@syntacore.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit

mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit
by privileged spec

Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240202113919.18236-1-vadim.shakirov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 944b6dfd3d67236882f2bc09d1d30ed923268e16
      
https://github.com/qemu/qemu/commit/944b6dfd3d67236882f2bc09d1d30ed923268e16
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  trans_rvv.c.inc: mark_vs_dirty() before loads and stores

While discussing a problem with how we're (not) setting vstart_eq_zero
Richard had the following to say w.r.t the conditional mark_vs_dirty()
calls on load/store functions [1]:

"I think it's required to have stores set dirty unconditionally, before
the operation.

Consider a store that traps on the 2nd element, leaving vstart = 2, and
exiting to the main loop via exception. The exception enters the kernel
page fault handler. The kernel may need to fault in the page for the
process, and in the meantime task switch.

If vs dirty is not already set, the kernel won't know to save vector
state on task switch."

Do a mark_vs_dirty() before both loads and stores.

[1] 
https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aac0c@linaro.org/

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240306171932.549549-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a506c4289dd05b3134a1b6eb0b506eaee81e224d
      
https://github.com/qemu/qemu/commit/a506c4289dd05b3134a1b6eb0b506eaee81e224d
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  trans_rvv.c.inc: remove 'is_store' bool from load/store fns

After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in some load/store functions that were changed. Remove it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240306171932.549549-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 938dd05ea1f3a9e3c713b1d73dc2992d62efb830
      
https://github.com/qemu/qemu/commit/938dd05ea1f3a9e3c713b1d73dc2992d62efb830
  Author: demin.han <demin.han@starfivetech.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Fix shift count overflow

The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
and results in wrong vill.

Signed-off-by: demin.han <demin.han@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bf31cf06eb5e709a1a7b082dc7956baadc4b70fa
      
https://github.com/qemu/qemu/commit/bf31cf06eb5e709a1a7b082dc7956baadc4b70fa
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/intc/riscv_aplic.c

  Log Message:
  -----------
  hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode

The writes to setipnum_le register in APLIC MSI-mode have special
consideration for level-triggered interrupts as-per section "4.9.2
Special consideration for level-sensitive interrupt sources" of the
RISC-V AIA specification.

Particularly, the below text from the RISC-V specification defines
the behaviour of writes to setipnum_le for level-triggered interrupts:

"A second option is for the interrupt service routine to write the
APLIC’s source identity number for the interrupt to the domain’s
setipnum register just before exiting. This will cause the interrupt’s
pending bit to be set to one again if the source is still asserting
an interrupt, but not if the source is not asserting an interrupt."

Fix setipnum_le write emulation for APLIC MSI-mode by implementing
the above behaviour in riscv_aplic_set_pending() function.

Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240306095722.463296-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0678e9f29c2301d0a1afc8d01a78cdfa7ad2ddbd
      
https://github.com/qemu/qemu/commit/0678e9f29c2301d0a1afc8d01a78cdfa7ad2ddbd
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/intc/riscv_aplic.c

  Log Message:
  -----------
  hw/intc/riscv_aplic: Fix in_clrip[x] read emulation

The reads to in_clrip[x] registers return rectified input values of the
interrupt sources.

A rectified input value of an interrupt source is defined by the section
"4.5.2 Source configurations (sourcecfg[1]–sourcecfg[1023])" of the RISC-V
AIA specification as:
"rectified input value = (incoming wire value) XOR (source is inverted)"

Update the riscv_aplic_read_input_word() implementation to match the above.

Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240306095722.463296-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6979b7b3f242c44a4908a5fe83f424aa852648a3
      
https://github.com/qemu/qemu/commit/6979b7b3f242c44a4908a5fe83f424aa852648a3
  Author: Hiroaki Yamamoto <hrak1529@gmail.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Fix privilege mode of G-stage translation for debugging

G-stage translation should be considered to be user-level access in
riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().

This fixes a bug that prevents gdb from reading memory while the VM is
running in VS-mode.

Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240228081028.35081-1-hrak1529@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 301876597112218c1e465ecc2b2fef6b27d5c27b
      
https://github.com/qemu/qemu/commit/301876597112218c1e465ecc2b2fef6b27d5c27b
  Author: Ilya Chugin <danger_mail@list.ru>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  target/riscv: fix ACPI MCFG table

MCFG segments should point to PCI configuration range, not BAR MMIO.

Signed-off-by: Ilya Chugin <danger_mail@list.ru>
Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and devices")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Message-ID: <180d236d-c8e4-411a-b4d2-632eb82092fa@list.ru>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cbccded4a2b5d685a426a437e25f67d3a375b292
      
https://github.com/qemu/qemu/commit/cbccded4a2b5d685a426a437e25f67d3a375b292
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M hw/acpi/aml-build.c
    M hw/arm/virt-acpi-build.c
    M hw/intc/riscv_aplic.c
    M hw/riscv/boot.c
    M hw/riscv/virt-acpi-build.c
    M hw/riscv/virt.c
    M include/hw/acpi/acpi-defs.h
    M include/hw/acpi/aml-build.h
    M include/standard-headers/drm/drm_fourcc.h
    M include/standard-headers/linux/ethtool.h
    M include/standard-headers/linux/virtio_config.h
    M include/standard-headers/linux/virtio_pci.h
    M include/standard-headers/linux/virtio_pmem.h
    M linux-headers/asm-generic/unistd.h
    M linux-headers/asm-mips/mman.h
    M linux-headers/asm-mips/unistd_n32.h
    M linux-headers/asm-mips/unistd_n64.h
    M linux-headers/asm-mips/unistd_o32.h
    M linux-headers/asm-powerpc/unistd_32.h
    M linux-headers/asm-powerpc/unistd_64.h
    M linux-headers/asm-riscv/kvm.h
    M linux-headers/asm-s390/unistd_32.h
    M linux-headers/asm-s390/unistd_64.h
    M linux-headers/asm-x86/kvm.h
    M linux-headers/asm-x86/unistd_32.h
    M linux-headers/asm-x86/unistd_64.h
    M linux-headers/asm-x86/unistd_x32.h
    M linux-headers/linux/iommufd.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/userfaultfd.h
    M linux-headers/linux/vfio.h
    M linux-user/syscall.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_cfg.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/insn_trans/trans_rvzce.c.inc
    M target/riscv/kvm/kvm-cpu.c
    M target/riscv/machine.c
    M target/riscv/pmu.h
    M target/riscv/tcg/tcg-cpu.c
    M target/riscv/translate.c
    M target/riscv/vector_helper.c
    M tests/qtest/libqos/meson.build
    A tests/qtest/libqos/riscv-virt-machine.c
    M tests/tcg/riscv64/Makefile.target

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20240308-1' of 
https://github.com/alistair23/qemu into staging

RISC-V PR for 9.0

* Update $ra with current $pc in trans_cm_jalt
* Enable SPCR for SCPI virt machine
* Allow large kernels to boot by moving the initrd further away in RAM
* Sync hwprobe keys with kernel
* Named features riscv,isa, 'svade' rework
* FIX xATP_MODE validation
* Add missing include guard in pmu.h
* Add SRAT and SLIT ACPI tables
* libqos fixes and add a riscv machine
* Add Ztso extension
* Use 'zfa' instead of 'Zfa'
* Update KVM exts to Linux 6.8
* move ratified/frozen exts to non-experimental
* Ensure mcountinhibit, mcounteren, scounteren, hcounteren are 32-bit
* mark_vs_dirty() before loads and stores
* Remove 'is_store' bool from load/store fns
* Fix shift count overflow
* Fix setipnum_le write emulation for APLIC MSI-mode
* Fix in_clrip[x] read emulation
* Fix privilege mode of G-stage translation for debugging
* Fix ACPI MCFG table for virt machine

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmXq8joACgkQr3yVEwxT
# gBMCRxAAvG1RsCxWhMjLYDEYuUhQkP2nd86PHJMrNxAeb5WUIrgrYyT6OLXpfuKN
# 8Hz5sR1bJnZSxKfGSFIHoPVxvW788fg7c5fIgg9txEssEQYhd7rCCPALxdiu/zlb
# 0fbfx9Ir0nb9qS6vQuT4dEddmljKYKPry8dH0anWI7SVIfdor2TTlP4xOAR88Yq7
# gdGIKvr7PrUhI5JdoWBe8R6w7vguT35EO6aiC+7PA+8AT1SXrxFrg86bYtDUffD+
# LktGcI7GhlIeosolodU8iNK7CdZTywRuyIQ+/KF4mmC7qaC8yJNVVTwX9/vXbH36
# dWIFkOv3VRnLBKt3/PW1DRZoUbSLpWjwH7WZsvQWPW5Ql717pGWId4eXSemxCFLN
# u7gGZ29/1jxMuYue+FImHTbBf6fSV25VOfo5ZfR/AfzxLBbugsP56CPwfK3K2OBq
# fQ+k3hl8iCx62rZrcAa69TuMBQJB5Q94NIFP1m5u/bPIZZhT311RVY1xx/dRCXnI
# 9/7DiPUyMeV4np2j4crvs4/QVTqYvpt4U9ElYrMWUxsTUyBEGEaSzpRsR5FCRmSH
# 2IrJsVWw5QsTlHukCMvxWIiWnYS5KIe764LsY31FNOlbl8eNJkyapc+BE8HWjgPa
# xYROCWOL7T/E1BPJ7wbEBlzPhuJOndZX91Zbfq0n+SAYq4YnNu4=
# =sCqM
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Mar 2024 11:10:50 GMT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20240308-1' of https://github.com/alistair23/qemu: 
(34 commits)
  target/riscv: fix ACPI MCFG table
  target/riscv: Fix privilege mode of G-stage translation for debugging
  hw/intc/riscv_aplic: Fix in_clrip[x] read emulation
  hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode
  target/riscv: Fix shift count overflow
  trans_rvv.c.inc: remove 'is_store' bool from load/store fns
  trans_rvv.c.inc: mark_vs_dirty() before loads and stores
  target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
  target/riscv: move ratified/frozen exts to non-experimental
  target/riscv/kvm: update KVM exts to Linux 6.8
  linux-headers: Update to Linux v6.8-rc6
  tests: riscv64: Use 'zfa' instead of 'Zfa'
  linux-user/riscv: Add Ztso extension to hwprobe
  RISC-V: Add support for Ztso
  tests/libqos: add riscv/virt machine nodes
  hw/riscv/virt.c: make aclint compatible with 'qtest' accel
  hw/riscv/virt.c: add virtio-iommu-pci hotplug support
  hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier
  hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables
  target/riscv: Add missing include guard in pmu.h
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/8480dd8685b3...cbccded4a2b5

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