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[Qemu-commits] [qemu/qemu] 84e945: vl, pc: turn -no-fd-bootchk into a ma
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 84e945: vl, pc: turn -no-fd-bootchk into a machine property |
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Date: |
Wed, 28 Feb 2024 06:24:02 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 84e945aad2d0cd950996a73705b4467e30ddbfa2
https://github.com/qemu/qemu/commit/84e945aad2d0cd950996a73705b4467e30ddbfa2
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/pc.h
M qemu-options.hx
M system/globals.c
M system/vl.c
Log Message:
-----------
vl, pc: turn -no-fd-bootchk into a machine property
Add a fd-bootchk property to PC machine types, so that -no-fd-bootchk
returns an error if the machine does not support booting from floppies
and checking for boot signatures therein.
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 68fb78d7d5723066ec2cacee7d25d67a4143b42f
https://github.com/qemu/qemu/commit/68fb78d7d5723066ec2cacee7d25d67a4143b42f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: mask high bits of CR3 in 32-bit mode
CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
paging or PAE paging). Do this in mmu_translate() to remove
the last where get_physical_address() meaningfully drops the high
bits of the address.
Cc: qemu-stable@nongnu.org
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates",
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d09c79010ffd880dc69e7a21e3cfdef90b928fb8
https://github.com/qemu/qemu/commit/d09c79010ffd880dc69e7a21e3cfdef90b928fb8
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: check validity of VMCB addresses
MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor. Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).
The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though the manual is not clear on that.
Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates",
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5f97afe2543f09160a8d123ab6e2e8c6d98fa9ce
https://github.com/qemu/qemu/commit/5f97afe2543f09160a8d123ab6e2e8c6d98fa9ce
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/i386/cpu.h
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: introduce function to query MMU indices
Remove knowledge of specific MMU indexes (other than MMU_NESTED_IDX and
MMU_PHYS_IDX) from mmu_translate(). This will make it possible to split
32-bit and 64-bit MMU indexes.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 90f641531c782c873a05895f411c05fbbbef3c49
https://github.com/qemu/qemu/commit/90f641531c782c873a05895f411c05fbbbef3c49
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: use separate MMU indexes for 32-bit accesses
Accesses from a 32-bit environment (32-bit code segment for instruction
accesses, EFER.LMA==0 for processor accesses) have to mask away the
upper 32 bits of the address. While a bit wasteful, the easiest way
to do so is to use separate MMU indexes. These days, QEMU anyway is
compiled with a fixed value for NB_MMU_MODES. Split MMU_USER_IDX,
MMU_KSMAP_IDX and MMU_KNOSMAP_IDX in two.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b1661801c184119a10ad6cbc3b80330fc22e7b2c
https://github.com/qemu/qemu/commit/b1661801c184119a10ad6cbc3b80330fc22e7b2c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Fix physical address truncation
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory above 4G will experience undefined behaviour.
The truncation code was originally introduced in commit 33dfdb5 ("x86:
only allow real mode to access 32bit without LMA"), where it applied
only to translations performed while paging is disabled (and so cannot
affect guests using PAE).
Commit 9828198 ("target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX")
rearranged the code such that the truncation also applied to the use
of MMU_PHYS_IDX and MMU_NESTED_IDX. Commit 4a1e9d4 ("target/i386: Use
atomic operations for pte updates") brought this truncation into scope
for page table entry accesses, and is the first commit for which a
Windows 10 32-bit guest will reliably fail to boot if memory above 4G
is present.
The truncation code however is not completely redundant. Even though the
maximum address size for any executed instruction is 32 bits, helpers for
operations such as BOUND, FSAVE or XSAVE may ask get_physical_address()
to translate an address outside of the 32-bit range, if invoked with an
argument that is close to the 4G boundary. Likewise for processor
accesses, for example TSS or IDT accesses, when EFER.LMA==0.
So, move the address truncation in get_physical_address() so that it
applies to 32-bit MMU indexes, but not to MMU_PHYS_IDX and MMU_NESTED_IDX.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2040
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates",
2022-10-18)
Cc: qemu-stable@nongnu.org
Co-developed-by: Michael Brown <mcb30@ipxe.org>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a28fe7dc1939333c81b895cdced81c69eb7c5ad0
https://github.com/qemu/qemu/commit/a28fe7dc1939333c81b895cdced81c69eb7c5ad0
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: remove unnecessary/wrong application of the A20 mask
If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already
applied in get_physical_address(), which is called via probe_access_full()
and x86_cpu_tlb_fill().
If ptw_translate() on the other hand does a MMU_NESTED_IDX access,
the A20 mask must not be applied to the address that is looked up in
the nested page tables; it must be applied only to the addresses that
hold the NPT entries (which is achieved via MMU_PHYS_IDX, per the
previous paragraph).
Therefore, we can remove A20 masking from the computation of the page
table entry's address, and let get_physical_address() or mmu_translate()
apply it when they know they are returning a host-physical address.
Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates",
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b5a9de3259f4c791bde2faff086dd5737625e41e
https://github.com/qemu/qemu/commit/b5a9de3259f4c791bde2faff086dd5737625e41e
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: leave the A20 bit set in the final NPT walk
The A20 mask is only applied to the final memory access. Nested
page tables are always walked with the raw guest-physical address.
Unlike the previous patch, in this one the masking must be kept, but
it was done too early.
Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates",
2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: dcaff46101c1f3abd97bbc5ba2f6c904def4e3b3
https://github.com/qemu/qemu/commit/dcaff46101c1f3abd97bbc5ba2f6c904def4e3b3
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M hw/ide/core.c
M hw/ide/ide-dev.c
M hw/ide/ide-internal.h
Log Message:
-----------
ide: collapse parameters to ide_init_drive
All calls to ide_init_drive comes from ide_dev_initfn. Just pass down the
IDEDevice (IDEState is kinda obsolete and should be merged into IDEDevice).
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d13f40357b307e49a7983bd52d4ec35003b7ddc0
https://github.com/qemu/qemu/commit/d13f40357b307e49a7983bd52d4ec35003b7ddc0
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M hw/ide/core.c
M hw/ide/ide-dev.c
M include/hw/ide/ide-dev.h
M include/sysemu/sysemu.h
M qemu-options.hx
M system/globals.c
M system/vl.c
Log Message:
-----------
ide, vl: turn -win2k-hack into a property on IDE devices
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 542b10bd148ae9f0aa839c66534272970c46c7f0
https://github.com/qemu/qemu/commit/542b10bd148ae9f0aa839c66534272970c46c7f0
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M tests/tcg/aarch64/semicall.h
M tests/tcg/arm/semicall.h
M tests/tcg/i386/system/boot.S
M tests/tcg/multiarch/arm-compat-semi/semiconsole.c
M tests/tcg/multiarch/arm-compat-semi/semihosting.c
M tests/tcg/multiarch/float_convd.c
M tests/tcg/multiarch/float_convs.c
M tests/tcg/multiarch/float_helpers.h
M tests/tcg/multiarch/float_madds.c
M tests/tcg/multiarch/libs/float_helpers.c
M tests/tcg/riscv64/semicall.h
M tests/tcg/x86_64/system/boot.S
Log Message:
-----------
tests/tcg: update licenses to GPLv2 as intended
My default header template is GPLv3 but for QEMU code we really should
stick to GPLv2-or-later (allowing others to up-license it if they
wish). While this is test code we should still be consistent on the
source distribution.
I wrote all of this code so its not a problem. However there remains
one GPLv3 file left which is the crt0-tc2x.S for TriCore.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-2-alex.bennee@linaro.org>
Commit: cdb5bfc9f3454e969c51669a2283347b9755d517
https://github.com/qemu/qemu/commit/cdb5bfc9f3454e969c51669a2283347b9755d517
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M tests/tcg/Makefile.target
Log Message:
-----------
tests/tcg: bump TCG test timeout to 120s
This is less than ideal but easier than making sure we get all the
iterations of the memory test. Update the comment accordingly.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-3-alex.bennee@linaro.org>
Commit: 151b7dba391fab64cc008a1fdba6ddcf6f8c39c8
https://github.com/qemu/qemu/commit/151b7dba391fab64cc008a1fdba6ddcf6f8c39c8
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M tests/vm/Makefile.include
M tests/vm/basevm.py
Log Message:
-----------
tests/vm: avoid re-building the VM images all the time
The main problem is that "check-venv" is a .PHONY target will always
evaluate and trigger a full re-build of the VM images. While its
tempting to drop it from the dependencies that does introduce a
breakage on freshly configured builds.
Fortunately we do have the otherwise redundant --force flag for the
script which up until now was always on. If we make the usage of
--force conditional on dependencies other than check-venv triggering
the update we can avoid the costly rebuild and still run cleanly on a
fresh checkout.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2118
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-4-alex.bennee@linaro.org>
Commit: 8467ac75b3b7207a49a1c6c7b87f0f7d2d0cea18
https://github.com/qemu/qemu/commit/8467ac75b3b7207a49a1c6c7b87f0f7d2d0cea18
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M tests/vm/openbsd
Log Message:
-----------
tests/vm: update openbsd image to 7.4
The old links are dead so even if we have the ISO cached we can't
finish the install. Update to the current stable and tweak the install
strings.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2192
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-5-alex.bennee@linaro.org>
Commit: 690bd97b5b18b9198300e09a55ff980ab57ba665
https://github.com/qemu/qemu/commit/690bd97b5b18b9198300e09a55ff980ab57ba665
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Use GDBFeature for dynamic XML
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231213-gdb-v17-1-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-6-alex.bennee@linaro.org>
Commit: 1b53948ff8f70fef3d2a07651a3342f77c043322
https://github.com/qemu/qemu/commit/1b53948ff8f70fef3d2a07651a3342f77c043322
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
Log Message:
-----------
target/ppc: Use GDBFeature for dynamic XML
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231213-gdb-v17-2-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-7-alex.bennee@linaro.org>
Commit: 33a24910aedaa184515b04921cc8a5dcccd99235
https://github.com/qemu/qemu/commit/33a24910aedaa184515b04921cc8a5dcccd99235
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: Use GDBFeature for dynamic XML
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20231213-gdb-v17-3-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-8-alex.bennee@linaro.org>
Commit: ac1e86710000ba3cf2e80836fb3f66ba12b169b8
https://github.com/qemu/qemu/commit/ac1e86710000ba3cf2e80836fb3f66ba12b169b8
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
M target/arm/gdbstub.c
M target/hexagon/cpu.c
M target/loongarch/gdbstub.c
M target/m68k/helper.c
M target/microblaze/cpu.c
M target/ppc/gdbstub.c
M target/riscv/gdbstub.c
M target/s390x/gdbstub.c
Log Message:
-----------
gdbstub: Use GDBFeature for gdb_register_coprocessor
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-4-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-9-alex.bennee@linaro.org>
Commit: c494f8f5299995fb7a0b0f5d621083f23ff3e5e8
https://github.com/qemu/qemu/commit/c494f8f5299995fb7a0b0f5d621083f23ff3e5e8
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M gdbstub/gdbstub.c
Log Message:
-----------
gdbstub: Use GDBFeature for GDBRegisterState
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231213-gdb-v17-5-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-10-alex.bennee@linaro.org>
Commit: 66260159a72ecd6c384197ba3d6e6f660ca5b482
https://github.com/qemu/qemu/commit/66260159a72ecd6c384197ba3d6e6f660ca5b482
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
M target/hexagon/gdbstub.c
M target/hexagon/internal.h
M target/loongarch/gdbstub.c
M target/m68k/helper.c
M target/microblaze/cpu.h
M target/microblaze/gdbstub.c
M target/ppc/gdbstub.c
M target/riscv/gdbstub.c
M target/s390x/gdbstub.c
Log Message:
-----------
gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-6-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-11-alex.bennee@linaro.org>
Commit: ee59fa1dd57bac8ba8c81e02f2710ba08d1aa49d
https://github.com/qemu/qemu/commit/ee59fa1dd57bac8ba8c81e02f2710ba08d1aa49d
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M gdbstub/gdbstub.c
M hw/core/cpu-common.c
M include/exec/gdbstub.h
Log Message:
-----------
gdbstub: Simplify XML lookup
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-7-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-12-alex.bennee@linaro.org>
Commit: ecd6f6a8820c8fa91e4d96c1bb640913bd856343
https://github.com/qemu/qemu/commit/ecd6f6a8820c8fa91e4d96c1bb640913bd856343
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/hw/core/cpu.h
M target/arm/cpu.c
M target/arm/cpu64.c
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/microblaze/gdbstub.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
Log Message:
-----------
gdbstub: Infer number of core registers from XML
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20231213-gdb-v17-8-777047380591@daynix.com>
[AJB: remove core reg check from microblaze read reg]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-13-alex.bennee@linaro.org>
Commit: f1a5287fc30acb788c2210e5f2a18c3d4006a8dc
https://github.com/qemu/qemu/commit/f1a5287fc30acb788c2210e5f2a18c3d4006a8dc
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M include/hw/core/cpu.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
M target/riscv/cpu.c
Log Message:
-----------
hw/core/cpu: Remove gdb_get_dynamic_xml member
This function is no longer used.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-9-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-14-alex.bennee@linaro.org>
Commit: eb37086fb0282a9a4f01ecbb618761d4853efc8c
https://github.com/qemu/qemu/commit/eb37086fb0282a9a4f01ecbb618761d4853efc8c
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
M scripts/feature_to_c.py
M target/riscv/gdbstub.c
Log Message:
-----------
gdbstub: Add members to identify registers to GDBFeature
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20231213-gdb-v17-10-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-15-alex.bennee@linaro.org>
Commit: 926e146eff8d7b89754e8b681f80e962d220f077
https://github.com/qemu/qemu/commit/926e146eff8d7b89754e8b681f80e962d220f077
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M contrib/plugins/cache.c
M include/qemu/qemu-plugin.h
M plugins/api.c
M plugins/plugin.h
M plugins/qemu-plugins.symbols
Log Message:
-----------
plugins: remove previous n_vcpus functions from API
This information is already accessible using qemu_info_t during plugin
install.
We will introduce another function (qemu_plugin_num_vcpus) which
represent how many cpus were enabled, by tracking new cpu indexes.
It's a breaking change, so we bump API version.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213094009.150349-2-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-16-alex.bennee@linaro.org>
Commit: 4a448b148ca076d80a41addd4fc1e49497cb23c8
https://github.com/qemu/qemu/commit/4a448b148ca076d80a41addd4fc1e49497cb23c8
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M include/qemu/qemu-plugin.h
M plugins/api.c
M plugins/core.c
M plugins/plugin.h
M plugins/qemu-plugins.symbols
Log Message:
-----------
plugins: add qemu_plugin_num_vcpus function
We now keep track of how many vcpus were started. This way, a plugin can
easily query number of any vcpus at any point of execution, which
unifies user and system mode workflows.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213094009.150349-3-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-17-alex.bennee@linaro.org>
Commit: c490e681ecce6d035fb67f02c2b674ab62a667f6
https://github.com/qemu/qemu/commit/c490e681ecce6d035fb67f02c2b674ab62a667f6
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M plugins/core.c
Log Message:
-----------
plugins: fix order of init/idle/resume callback
We found that vcpu_init_hook was called *after* idle callback.
vcpu_init is called from cpu_realize_fn, while idle/resume cb are called
from qemu_wait_io_event (in vcpu thread).
This change ensures we only call idle and resume cb only once a plugin
was init for a given vcpu.
Next change in the series will run vcpu_init asynchronously, which will
make it run *after* resume callback as well. So we fix this now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20240213094009.150349-4-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-18-alex.bennee@linaro.org>
Commit: f2e8d2d89954ed3d9603c904aaad1264cf250551
https://github.com/qemu/qemu/commit/f2e8d2d89954ed3d9603c904aaad1264cf250551
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M linux-user/nios2/cpu_loop.c
Log Message:
-----------
linux-user: ensure nios2 processes queued work
While async processes are rare for linux-user we do use them from time
to time. The most obvious one is tb_flush when we run out of
translation space. We will also need this when we move plugin
vcpu_init to an async task.
Fix nios2 to follow its older, wiser and more stable siblings.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-19-alex.bennee@linaro.org>
Commit: 81cf548f533b4f9e1dc58414f081c2530e08fa48
https://github.com/qemu/qemu/commit/81cf548f533b4f9e1dc58414f081c2530e08fa48
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M hw/core/cpu-common.c
Log Message:
-----------
cpu: call plugin init hook asynchronously
This ensures we run during a cpu_exec, which allows to call start/end
exclusive from this init hook (needed for new scoreboard API introduced
later).
async work is run before any tb is translated/executed, so we can
guarantee plugin init will be called before any other hook.
The previous change made sure that any idle/resume cb call will not be
done before initializing plugin for a given vcpu.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20240213094009.150349-5-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-20-alex.bennee@linaro.org>
Commit: 33a277fec03a61e470bc279b03b1a3759505f3e0
https://github.com/qemu/qemu/commit/33a277fec03a61e470bc279b03b1a3759505f3e0
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M accel/tcg/plugin-gen.c
M accel/tcg/plugin-helpers.h
M include/qemu/plugin.h
M plugins/api.c
Log Message:
-----------
plugins: Use different helpers when reading registers
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20231213-gdb-v17-12-777047380591@daynix.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-21-alex.bennee@linaro.org>
Commit: c3d0b46645d4b95b1fa24f4911738cb59d26173e
https://github.com/qemu/qemu/commit/c3d0b46645d4b95b1fa24f4911738cb59d26173e
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
Log Message:
-----------
gdbstub: expose api to find registers
Expose an internal API to QEMU to return all the registers for a vCPU.
The list containing the details required to called gdb_read_register().
Based-on: <20231025093128.33116-15-akihiko.odaki@daynix.com>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-22-alex.bennee@linaro.org>
Commit: c006147122dede4440c027142ce3025f64e199c0
https://github.com/qemu/qemu/commit/c006147122dede4440c027142ce3025f64e199c0
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M accel/tcg/plugin-gen.c
M hw/core/cpu-common.c
M include/hw/core/cpu.h
M include/qemu/plugin.h
M include/qemu/typedefs.h
M plugins/core.c
Log Message:
-----------
plugins: create CPUPluginState and migrate plugin_mask
As we expand the per-vCPU data for plugins we don't want to pollute
CPUState. For now this just moves the plugin_mask (renamed to
event_mask) as the memory callbacks are accessed directly by TCG
generated code.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-23-alex.bennee@linaro.org>
Commit: 8df5e27cf71c727a3e1bc9172819ec69eca32ff4
https://github.com/qemu/qemu/commit/8df5e27cf71c727a3e1bc9172819ec69eca32ff4
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M include/qemu/qemu-plugin.h
M plugins/api.c
M plugins/qemu-plugins.symbols
Log Message:
-----------
plugins: add an API to read registers
We can only request a list of registers once the vCPU has been
initialised so the user needs to use either call the get function on
vCPU initialisation or during the translation phase.
We don't expose the reg number to the plugin instead hiding it behind
an opaque handle. For now this is just the gdb_regnum encapsulated in
an anonymous GPOINTER but in future as we add more state for plugins
to track we can expand it.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-24-alex.bennee@linaro.org>
Commit: 6036b9cfde74f45af7ef449d7c034fb8a9cf2901
https://github.com/qemu/qemu/commit/6036b9cfde74f45af7ef449d7c034fb8a9cf2901
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M tests/plugin/insn.c
Log Message:
-----------
tests/tcg: expand insn test case to exercise register API
This ensure we at least read every register the plugin API reports at
least once during the check-tcg checks.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-25-alex.bennee@linaro.org>
Commit: 9e096a76c78ac215e8d06cc9739ab9c181d85a2b
https://github.com/qemu/qemu/commit/9e096a76c78ac215e8d06cc9739ab9c181d85a2b
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M contrib/plugins/execlog.c
Log Message:
-----------
contrib/plugins: fix imatch
We can't directly save the ephemeral imatch from argv as that memory
will get recycled.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-26-alex.bennee@linaro.org>
Commit: af6e4e0a22c18a7cc97650caec56ed99c9899dd7
https://github.com/qemu/qemu/commit/af6e4e0a22c18a7cc97650caec56ed99c9899dd7
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M contrib/plugins/execlog.c
M docs/devel/tcg-plugins.rst
Log Message:
-----------
contrib/plugins: extend execlog to track register changes
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions which mention
registers we are interested in tracking.
Example usage:
./qemu-aarch64 -D plugin.log -d plugin \
-cpu max,sve256=on \
-plugin contrib/plugins/libexeclog.so,reg=sp,reg=z\* \
./tests/tcg/aarch64-linux-user/sha512-sve
will display in the execlog any changes to the stack pointer (sp) and
the SVE Z registers.
As testing registers every instruction will be quite a heavy operation
there is an additional flag which attempts to optimise the register
tracking by only instrumenting instructions which are likely to change
its value. This relies on the QEMU disassembler showing up the register
names in disassembly so is an explicit opt-in.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Based-On: <20231025093128.33116-19-akihiko.odaki@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-27-alex.bennee@linaro.org>
Commit: b0b3c0f56258b697dd3faca389e98d0022bc7727
https://github.com/qemu/qemu/commit/b0b3c0f56258b697dd3faca389e98d0022bc7727
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M docs/devel/tcg-plugins.rst
Log Message:
-----------
docs/devel: lift example and plugin API sections up
This makes them a bit more visible in the TCG emulation menu rather
than hiding them away bellow the ToC limit.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-28-alex.bennee@linaro.org>
Commit: f87b220f2a9d6a552c4cd2004475e76f38a08279
https://github.com/qemu/qemu/commit/f87b220f2a9d6a552c4cd2004475e76f38a08279
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M docs/devel/tcg-plugins.rst
Log Message:
-----------
docs/devel: document some plugin assumptions
While we attempt to hide implementation details from the plugin we
shouldn't be totally obtuse. Let the user know what they can and can't
expect with the various instrumentation options.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-29-alex.bennee@linaro.org>
Commit: 02ca5ec15089c8717d435d8a842360f15afa7d20
https://github.com/qemu/qemu/commit/02ca5ec15089c8717d435d8a842360f15afa7d20
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M docs/devel/multi-thread-tcg.rst
Log Message:
-----------
docs/devel: plugins can trigger a tb flush
When scoreboards need to be reallocated.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213094009.150349-8-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-30-alex.bennee@linaro.org>
Commit: d316f1b14615854de1bf4c0a9789e9c8951cc437
https://github.com/qemu/qemu/commit/d316f1b14615854de1bf4c0a9789e9c8951cc437
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M accel/tcg/plugin-gen.c
M accel/tcg/plugin-helpers.h
M contrib/plugins/cache.c
M contrib/plugins/execlog.c
M docs/devel/multi-thread-tcg.rst
M docs/devel/tcg-plugins.rst
M gdbstub/gdbstub.c
M hw/core/cpu-common.c
M include/exec/gdbstub.h
M include/hw/core/cpu.h
M include/qemu/plugin.h
M include/qemu/qemu-plugin.h
M include/qemu/typedefs.h
M linux-user/nios2/cpu_loop.c
M plugins/api.c
M plugins/core.c
M plugins/plugin.h
M plugins/qemu-plugins.symbols
M scripts/feature_to_c.py
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hexagon/gdbstub.c
M target/hexagon/internal.h
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/loongarch/gdbstub.c
M target/m68k/cpu.c
M target/m68k/helper.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/gdbstub.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/gdbstub.c
M tests/plugin/insn.c
M tests/tcg/Makefile.target
M tests/tcg/aarch64/semicall.h
M tests/tcg/arm/semicall.h
M tests/tcg/i386/system/boot.S
M tests/tcg/multiarch/arm-compat-semi/semiconsole.c
M tests/tcg/multiarch/arm-compat-semi/semihosting.c
M tests/tcg/multiarch/float_convd.c
M tests/tcg/multiarch/float_convs.c
M tests/tcg/multiarch/float_helpers.h
M tests/tcg/multiarch/float_madds.c
M tests/tcg/multiarch/libs/float_helpers.c
M tests/tcg/riscv64/semicall.h
M tests/tcg/x86_64/system/boot.S
M tests/vm/Makefile.include
M tests/vm/basevm.py
M tests/vm/openbsd
Log Message:
-----------
Merge tag 'pull-maintainer-updates-280224-1' of
https://gitlab.com/stsquad/qemu into staging
Testing, gdbstub and plugin updates:
- fix some test/tcg license headers to GPLv2+
- bump up check-tcg timeout to 120s
- avoid re-building VM images too often
- update OpenBSD to 7.4
- use GDBFeature to build gdbstub XML
- unify plugin vcpu count under qemu_plugin_num_vcpus
- avoid spurious idle/resume callbacks on new vCPUs
- ensure nios2-linux-user processes async work
- call vcpu_init plugin callback through async work
- define plugin helpers when registers being read
- add plugin API for reading register values
- add support for register tracking to execlog
- update plugin docs with assumptions
- mention plugins can trigger tb_flush in mttcg design doc
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# gpg: Signature made Wed 28 Feb 2024 09:55:09 GMT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key)
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* tag 'pull-maintainer-updates-280224-1' of https://gitlab.com/stsquad/qemu:
(29 commits)
docs/devel: plugins can trigger a tb flush
docs/devel: document some plugin assumptions
docs/devel: lift example and plugin API sections up
contrib/plugins: extend execlog to track register changes
contrib/plugins: fix imatch
tests/tcg: expand insn test case to exercise register API
plugins: add an API to read registers
plugins: create CPUPluginState and migrate plugin_mask
gdbstub: expose api to find registers
plugins: Use different helpers when reading registers
cpu: call plugin init hook asynchronously
linux-user: ensure nios2 processes queued work
plugins: fix order of init/idle/resume callback
plugins: add qemu_plugin_num_vcpus function
plugins: remove previous n_vcpus functions from API
gdbstub: Add members to identify registers to GDBFeature
hw/core/cpu: Remove gdb_get_dynamic_xml member
gdbstub: Infer number of core registers from XML
gdbstub: Simplify XML lookup
gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bfe8020c814a30479a4241aaa78b63960655962b
https://github.com/qemu/qemu/commit/bfe8020c814a30479a4241aaa78b63960655962b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M hw/i386/pc.c
M hw/ide/core.c
M hw/ide/ide-dev.c
M hw/ide/ide-internal.h
M include/hw/i386/pc.h
M include/hw/ide/ide-dev.h
M include/sysemu/sysemu.h
M qemu-options.hx
M system/globals.c
M system/vl.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: Fix physical address truncation on 32-bit PAE
* Remove globals for options -no-fd-bootchk and -win2k-hack
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# gpg: Signature made Tue 27 Feb 2024 23:23:48 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
ide, vl: turn -win2k-hack into a property on IDE devices
ide: collapse parameters to ide_init_drive
target/i386: leave the A20 bit set in the final NPT walk
target/i386: remove unnecessary/wrong application of the A20 mask
target/i386: Fix physical address truncation
target/i386: use separate MMU indexes for 32-bit accesses
target/i386: introduce function to query MMU indices
target/i386: check validity of VMCB addresses
target/i386: mask high bits of CR3 in 32-bit mode
vl, pc: turn -no-fd-bootchk into a machine property
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/158a054c4d1a...bfe8020c814a
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- [Qemu-commits] [qemu/qemu] 84e945: vl, pc: turn -no-fd-bootchk into a machine property,
Peter Maydell <=