[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 944128: aspeed: introduce a new UART0 device
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 944128: aspeed: introduce a new UART0 device name |
|
Date: |
Tue, 27 Feb 2024 09:19:39 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 944128ee8e26d70a29c66e0e630ceb371750f23c
https://github.com/qemu/qemu/commit/944128ee8e26d70a29c66e0e630ceb371750f23c
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: introduce a new UART0 device name
The Aspeed datasheet refers to the UART controllers
as UART1 - UART13 for the ast10x0, ast2600, ast2500
and ast2400 SoCs and the Aspeed ast2700 introduces an UART0
and the UART controllers as UART0 - UART12.
To keep the naming in the QEMU models
in sync with the datasheet, let's introduce a new UART0 device name
and do the required adjustements.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - Kept original assert() in aspeed_soc_uart_set_chr()
- Fixed 'i' range in connect_serial_hds_to_uarts() loop ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: db052d0eafe86c336d512dba99a1ec7c5c553f63
https://github.com/qemu/qemu/commit/db052d0eafe86c336d512dba99a1ec7c5c553f63
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: fix hardcode boot address 0
In the previous design of ASPEED SOCs QEMU model, it set the boot
address at "0" which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL and initialize DRAM and copy u-boot image
from SPI/Flash to DRAM at address 0x400000000 at SPL boot stage.
Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.
Currently, qemu not support emulate two CPU architectures
at the same machine. Therefore, qemu will only support
to emulate CPU(cortex-a35) side for ast2700 and the boot
address is "0x4 00000000".
Fixed hardcode boot address "0" for future models using
a different mapping address.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5306ff73fea63d62bc3908c9cad9a88523cb1637
https://github.com/qemu/qemu/commit/5306ff73fea63d62bc3908c9cad9a88523cb1637
Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: Simplify init since PCIe is always enabled
There is no point in checking do we have PCIe if first thing after check
is adding PCIe card without checking.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240215153311.186772-1-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: aa29cdd6e3d430ad6bae4281512c2b7df9e12e98
https://github.com/qemu/qemu/commit/aa29cdd6e3d430ad6bae4281512c2b7df9e12e98
Author: Ard Biesheuvel <ardb@kernel.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Advertise Cortex-A53 erratum #843419 fix via REVIDR
The Cortex-A53 r0p4 revision that QEMU emulates is affected by a CatA
erratum #843419 (i.e., the most severe), which requires workarounds in
the toolchain as well as the OS.
Since the emulation is obviously not affected in the same way, we can
indicate this via REVIDR bit #8, which on r0p4 has the meaning that no
workarounds for erratum #843419 are needed.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240215160202.2803452-1-ardb+git@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9d19a8ffcc253383f73850f6a61f04d7940f8cb6
https://github.com/qemu/qemu/commit/9d19a8ffcc253383f73850f6a61f04d7940f8cb6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine
This code -- which was moved many times around -- was added in
commit 377e214539 ("ahci: Add allwinner AHCI") and belong to the
AllWinner machines. See also commit dca625768a ("arm: allwinner-a10:
Add SATA").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240215160713.80409-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9d80aa04832a5ec342f31a6bfea50b9245110139
https://github.com/qemu/qemu/commit/9d80aa04832a5ec342f31a6bfea50b9245110139
Author: Abhiram Tilak <atp.exp@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/rtc/m48t59.c
Log Message:
-----------
misc: m48t59: replace qemu_system_reset_request() call with
watchdog_perform_action()
A few watchdog devices use qemu_system_reset_request(). This is not ideal since
behaviour of watchdog-expiry can't be changed by QMP using `watchdog_action`.
As stated in BiteSizedTasks wiki page, instead of using
qemu_system_reset_request()
to reset when a watchdog timer expires, let watchdog_perform_action() decide
what to do.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2124
Signed-off-by: Abhiram Tilak <atp.exp@gmail.com>
Message-id: 20240216192612.30838-4-atp.exp@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: efabbc07e96b502acb4927743964dde132d75ded
https://github.com/qemu/qemu/commit/efabbc07e96b502acb4927743964dde132d75ded
Author: Abhiram Tilak <atp.exp@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/timer/pxa2xx_timer.c
Log Message:
-----------
misc: pxa2xx_timer: replace qemu_system_reset_request() call with
watchdog_perform_action()
A few watchdog devices use qemu_system_reset_request(). This is not ideal since
behaviour of watchdog-expiry can't be changed by QMP using `watchdog_action`.
As stated in BiteSizedTasks wiki page, instead of using
qemu_system_reset_request()
to reset when a watchdog timer expires, let watchdog_perform_action() decide
what to do.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2124
Signed-off-by: Abhiram Tilak <atp.exp@gmail.com>
Message-id: 20240216192612.30838-5-atp.exp@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3b3e4c2803a58ddc14f37d05c7d0e2a3f749bc67
https://github.com/qemu/qemu/commit/3b3e4c2803a58ddc14f37d05c7d0e2a3f749bc67
Author: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/ssi/xlnx-versal-ospi.c
Log Message:
-----------
xlnx-versal-ospi: disable reentrancy detection for iomem_dac
The OSPI DMA reads flash data through the OSPI linear address space (the
iomem_dac region), because of this the reentrancy guard introduced in
commit a2e1753b ("memory: prevent dma-reentracy issues") is disabled for
the memory region.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Message-id: 20240219105637.65052-1-sai.pavan.boddu@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5928ed26b3a72640f8567bd892863e491a1c8c3f
https://github.com/qemu/qemu/commit/5928ed26b3a72640f8567bd892863e491a1c8c3f
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/stm32l4x5_soc.c
M include/hw/arm/stm32l4x5_soc.h
Log Message:
-----------
hw/arm: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs
Fixes: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI")
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240220184145.106107-2-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 397424f87f6b80b351d38438110cf5caf86cc05b
https://github.com/qemu/qemu/commit/397424f87f6b80b351d38438110cf5caf86cc05b
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M tests/qtest/stm32l4x5_exti-test.c
Log Message:
-----------
tests/qtest: Check that EXTI fan-in irqs are correctly connected
This commit adds a QTest that verifies each input line of a specific
EXTI OR gate can influence the output line.
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240220184145.106107-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4d28d57c9f2eb1cdf70b29cea6e50282e010075b
https://github.com/qemu/qemu/commit/4d28d57c9f2eb1cdf70b29cea6e50282e010075b
Author: Jessica Clarke <jrtc27@jrtc27.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/rtc/pl031.c
Log Message:
-----------
pl031: Update last RTCLR value on write in case it's read back
The PL031 allows you to read RTCLR, which is meant to give you the last
value written. PL031State has an lr field which is used when reading
from RTCLR, and is present in the VM migration state, but we never
actually update it, so it always reads as its initial 0 value.
Cc: qemu-stable@nongnu.org
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20240222000341.1562443-1-jrtc27@jrtc27.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4d85bfc86bf9a32123b787e1fa15022b0e630644
https://github.com/qemu/qemu/commit/4d85bfc86bf9a32123b787e1fa15022b0e630644
Author: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
block: m25p80: Add support of mt35xu02gbba
Add Micro 2Gb OSPI flash part with sfdp data.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20240220091721.82954-2-sai.pavan.boddu@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 06005459dcd75aca23c942519046154197ab4542
https://github.com/qemu/qemu/commit/06005459dcd75aca23c942519046154197ab4542
Author: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/xlnx-versal-virt.c
Log Message:
-----------
arm: xlnx-versal-virt: Add machine property ospi-flash
This property allows users to change flash model on command line as
below.
ex: "-M xlnx-versal-virt,ospi-flash=mt35xu02gbba"
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Message-id: 20240220091721.82954-3-sai.pavan.boddu@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7421ddc4dca27b77dbc62e5cc2aaaae116802639
https://github.com/qemu/qemu/commit/7421ddc4dca27b77dbc62e5cc2aaaae116802639
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
arm/ptw: Handle atomic updates of page tables entries in MMIO during PTW.
I'm far from confident this handling here is correct. Hence
RFC. In particular not sure on what locks I should hold for this
to be even moderately safe.
The function already appears to be inconsistent in what it returns
as the CONFIG_ATOMIC64 block returns the endian converted 'eventual'
value of the cmpxchg whereas the TCG_OVERSIZED_GUEST case returns
the previous value.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-id: 20240219161229.11776-1-Jonathan.Cameron@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e41f32fe8254cd1b2e00bcc5af1e4d528c5a79db
https://github.com/qemu/qemu/commit/e41f32fe8254cd1b2e00bcc5af1e4d528c5a79db
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M system/bootdevice.c
Log Message:
-----------
system/bootdevice: Don't unregister reset handler in restore_boot_order()
Currently the qemu_register_reset() API permits the reset handler functions
registered with it to remove themselves from within the callback function.
This is fine with our current implementation, but is a bit odd, because
generally reset is supposed to be idempotent, and doesn't fit well in a
three-phase-reset world where a resettable object will get multiple
callbacks as the system is reset.
We now have only one user of qemu_register_reset() which makes use of
the ability to unregister itself within the callback:
restore_boot_order(). We want to change our implementation of
qemu_register_reset() to something where it would be awkward to
maintain the "can self-unregister" feature. Rather than making that
reimplementation complicated, change restore_boot_order() so that it
doesn't unregister itself but instead returns doing nothing for any
calls after it has done the "restore the boot order" work.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240220160622.114437-4-peter.maydell@linaro.org
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Commit: e54c24339f3e6533af0b0c4364c5c9c9f74e9273
https://github.com/qemu/qemu/commit/e54c24339f3e6533af0b0c4364c5c9c9f74e9273
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M docs/devel/qom.rst
M include/qom/object.h
Log Message:
-----------
include/qom/object.h: New OBJECT_DEFINE_SIMPLE_TYPE{, _WITH_INTERFACES} macros
We have an OBJECT_DEFINE_TYPE_EXTENDED macro, plus several variations
on it, which emits the boilerplate for the TypeInfo and ensures it is
registered with the type system. However, all the existing macros
insist that the type being defined has its own FooClass struct, so
they aren't useful for the common case of a simple leaf class which
doesn't have any new methods or any other need for its own class
struct (that is, for the kind of type that OBJECT_DECLARE_SIMPLE_TYPE
declares).
Pull the actual implementation of OBJECT_DEFINE_TYPE_EXTENDED out
into a new DO_OBJECT_DEFINE_TYPE_EXTENDED which parameterizes the
value we use for the class_size field. This lets us add a new
OBJECT_DEFINE_SIMPLE_TYPE which does the same job as the various
existing OBJECT_DEFINE_*_TYPE_* family macros for this kind of simple
type, and the variant OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES for
when the type will implement some interfaces.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240220160622.114437-5-peter.maydell@linaro.org
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Commit: 9f1c70a254341fd7ee23c96e806436ecb83684d8
https://github.com/qemu/qemu/commit/9f1c70a254341fd7ee23c96e806436ecb83684d8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M include/sysemu/reset.h
Log Message:
-----------
hw/core: Add documentation and license comments to reset.h
Add the usual boilerplate license/copyright comment to reset.h (using
the text from reset.c), and document the existing functions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20240220160622.114437-6-peter.maydell@linaro.org
Commit: 4c046ce37af0c4dcca2b440809ebd07f9953dcfb
https://github.com/qemu/qemu/commit/4c046ce37af0c4dcca2b440809ebd07f9953dcfb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M MAINTAINERS
M hw/core/meson.build
A hw/core/resetcontainer.c
A include/hw/core/resetcontainer.h
Log Message:
-----------
hw/core: Add ResetContainer which holds objects implementing Resettable
Implement a ResetContainer. This is a subclass of Object, and it
implements the Resettable interface. The container holds a list of
arbitrary other objects which implement Resettable, and when the
container is reset, all the objects it contains are also reset.
This will allow us to have a 3-phase-reset equivalent of the old
qemu_register_reset() API: we will have a single "simulation reset"
top level ResetContainer, and objects in it are the equivalent of the
old QEMUResetHandler functions.
The qemu_register_reset() API manages its list of callbacks using a
QTAILQ, but here we use a GPtrArray for our list of Resettable
children: we expect the "remove" operation (which will need to do an
iteration through the list) to be fairly uncommon, and we get simpler
code with fewer memory allocations.
Since there is currently no listed owner in MAINTAINERS for the
existing reset-related source files, create a new section for
them, and add these new files there also.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20240220160622.114437-7-peter.maydell@linaro.org
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Commit: 86fae16ed298518ea851d6accc48643e6bdf8ed1
https://github.com/qemu/qemu/commit/86fae16ed298518ea851d6accc48643e6bdf8ed1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/core/reset.c
M include/sysemu/reset.h
Log Message:
-----------
hw/core/reset: Add qemu_{register, unregister}_resettable()
Implement new functions qemu_register_resettable() and
qemu_unregister_resettable(). These are intended to be
three-phase-reset aware equivalents of the old qemu_register_reset()
and qemu_unregister_reset(). Instead of passing in a function
pointer and opaque, you register any QOM object that implements the
Resettable interface.
The implementation is simple: we have a single global instance of a
ResettableContainer, which we reset in qemu_devices_reset(), and
the Resettable objects passed to qemu_register_resettable() are
added to it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20240220160622.114437-8-peter.maydell@linaro.org
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Commit: 71b3ea373bc3b8e3e656d1e8c390896e21c31c0b
https://github.com/qemu/qemu/commit/71b3ea373bc3b8e3e656d1e8c390896e21c31c0b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/core/reset.c
M include/sysemu/reset.h
Log Message:
-----------
hw/core/reset: Implement qemu_register_reset via qemu_register_resettable
Reimplement qemu_register_reset() via qemu_register_resettable().
We define a new LegacyReset object which implements Resettable and
defines its reset hold phase method to call a QEMUResetHandler
function. When qemu_register_reset() is called, we create a new
LegacyReset object and add it to the simulation_reset
ResettableContainer. When qemu_unregister_reset() is called, we find
the LegacyReset object in the container and remove it.
This implementation of qemu_unregister_reset() means we'll end up
scanning the ResetContainer's list of child objects twice, once
to find the LegacyReset object, and once in g_ptr_array_remove().
In theory we could avoid this by having the ResettableContainer
interface include a resettable_container_remove_with_equal_func()
that took a callback method so that we could use
g_ptr_array_find_with_equal_func() and g_ptr_array_remove_index().
But we don't expect qemu_unregister_reset() to be called frequently
or in hot paths, and we expect the simulation_reset container to
usually not have many children.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20240220160622.114437-9-peter.maydell@linaro.org
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Commit: 0441e35f95fd8658967138062f8c10fe594e9559
https://github.com/qemu/qemu/commit/0441e35f95fd8658967138062f8c10fe594e9559
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/core/machine.c
Log Message:
-----------
hw/core/machine: Use qemu_register_resettable for sysbus reset
Move the reset of the sysbus (and thus all devices and buses anywhere
on the qbus tree) from qemu_register_reset() to qemu_register_resettable().
This is a behaviour change: because qemu_register_resettable() is
aware of three-phase reset, this now means that:
* 'enter' phase reset methods of devices and buses are called
before any legacy reset callbacks registered with qemu_register_reset()
* 'exit' phase reset methods of devices and buses are called
after any legacy qemu_register_reset() callbacks
Put another way, a qemu_register_reset() callback is now correctly
ordered in the 'hold' phase along with any other 'hold' phase methods.
The motivation for doing this is that we will now be able to resolve
some reset-ordering issues using the three-phase mechanism, because
the 'exit' phase is always after the 'hold' phase, even when the
'hold' phase function was registered with qemu_register_reset().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20240220160622.114437-10-peter.maydell@linaro.org
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Commit: a365572b9c5c7baf8fcd9ea7200843e6fbcd53ca
https://github.com/qemu/qemu/commit/a365572b9c5c7baf8fcd9ea7200843e6fbcd53ca
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M docs/devel/reset.rst
Log Message:
-----------
docs/devel/reset: Update to discuss system reset
Now that system reset uses a three-phase-reset, update the reset
documentation to include a section describing how this works.
Include documentation of the current major beartrap in reset, which
is that only devices on the qbus tree will get automatically reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20240220160622.114437-11-peter.maydell@linaro.org
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Commit: f932093ae165ac9abfbded10510ff5c891d44ec3
https://github.com/qemu/qemu/commit/f932093ae165ac9abfbded10510ff5c891d44ec3
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/bcm2836.c
M hw/arm/raspi.c
M include/hw/arm/bcm2836.h
Log Message:
-----------
hw/arm/bcm2836: Split out common part of BCM283X classes
Pre setup for BCM2838 introduction
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-2-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7d04d630ba7ada8a9530d8c45f4b0840f557bf31
https://github.com/qemu/qemu/commit/7d04d630ba7ada8a9530d8c45f4b0840f557bf31
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M hw/arm/bcm2836.c
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/bcm2836.h
Log Message:
-----------
hw/arm/bcm2853_peripherals: Split out common part of peripherals
Pre-setup for BCM2838 introduction
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-3-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 08df0676363e3ed717476df6da065a0d5ea87382
https://github.com/qemu/qemu/commit/08df0676363e3ed717476df6da065a0d5ea87382
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/raspi.c
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/arm/raspi: Split out raspi machine common part
Pre-setup for raspberry pi 4 introduction
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-4-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dcf1d8cdfbe6ab56456380ddc13f551df070a539
https://github.com/qemu/qemu/commit/dcf1d8cdfbe6ab56456380ddc13f551df070a539
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
A hw/arm/bcm2838.c
A hw/arm/bcm2838_peripherals.c
M hw/arm/meson.build
A include/hw/arm/bcm2838.h
A include/hw/arm/bcm2838_peripherals.h
Log Message:
-----------
hw/arm: Introduce BCM2838 SoC
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-5-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 96b22ee585a50bf136973aa893e139798d9d4df3
https://github.com/qemu/qemu/commit/96b22ee585a50bf136973aa893e139798d9d4df3
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/bcm2838.c
M hw/arm/trace-events
M include/hw/arm/bcm2838.h
M include/hw/arm/bcm2838_peripherals.h
Log Message:
-----------
hw/arm/bcm2838: Add GIC-400 to BCM2838 SoC
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-6-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 23c82c1daf30b3ed8d988f3f1d7fbb0557059ac6
https://github.com/qemu/qemu/commit/23c82c1daf30b3ed8d988f3f1d7fbb0557059ac6
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
A hw/gpio/bcm2838_gpio.c
M hw/gpio/meson.build
A include/hw/gpio/bcm2838_gpio.h
Log Message:
-----------
hw/gpio: Add BCM2838 GPIO stub
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-7-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0c8b40db671e2a1336d8effa85e88442af2e0d40
https://github.com/qemu/qemu/commit/0c8b40db671e2a1336d8effa85e88442af2e0d40
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/gpio/bcm2838_gpio.c
Log Message:
-----------
hw/gpio: Implement BCM2838 GPIO functionality
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-8-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b54a9a56796b1c6e27c740d52a88bb7023abb621
https://github.com/qemu/qemu/commit/b54a9a56796b1c6e27c740d52a88bb7023abb621
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/gpio/bcm2838_gpio.c
M include/hw/gpio/bcm2838_gpio.h
Log Message:
-----------
hw/gpio: Connect SD controller to BCM2838 GPIO
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-9-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1367375612c7b6ef0ab479e6c00ae750e57e7055
https://github.com/qemu/qemu/commit/1367375612c7b6ef0ab479e6c00ae750e57e7055
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/bcm2838_peripherals.c
M include/hw/arm/bcm2838_peripherals.h
Log Message:
-----------
hw/arm: Add GPIO and SD to BCM2838 periph
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-10-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7785e8ea220493ef4faa98647946855ba1d28c43
https://github.com/qemu/qemu/commit/7785e8ea220493ef4faa98647946855ba1d28c43
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M hw/arm/bcm2836.c
M hw/arm/bcm2838.c
M hw/arm/meson.build
M hw/arm/raspi.c
A hw/arm/raspi4b.c
M include/hw/arm/raspi_platform.h
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/arm: Introduce Raspberry PI 4 machine
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-11-sergey.kambalin@auriga.com
[PMM: Change name to 'raspi4b', not 'raspi4b-2g']
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bf1da4b308686fe8e3d86db7084793a7a3d7c54a
https://github.com/qemu/qemu/commit/bf1da4b308686fe8e3d86db7084793a7a3d7c54a
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/raspi.c
M hw/arm/raspi4b.c
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/arm/raspi4b: Temporarily disable unimplemented rpi4b devices
This commit adds RPi4B device tree modifications:
- disable pcie, rng200, thermal sensor and genet devices
(they're going to be re-enabled in the following commits)
- create additional memory region in device tree
if RAM amount exceeds VC base address.
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-12-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bd41b27508d896a5c48c6c92a55a60704cb6ec8b
https://github.com/qemu/qemu/commit/bd41b27508d896a5c48c6c92a55a60704cb6ec8b
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/bcm2838_peripherals.c
M include/hw/arm/bcm2838_peripherals.h
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/arm: Add memory region for BCM2837 RPiVid ASB
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-13-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d8a57715bb2a9931b5886fac90e4a5b6bb710aeb
https://github.com/qemu/qemu/commit/d8a57715bb2a9931b5886fac90e4a5b6bb710aeb
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/bcm2838_peripherals.c
M include/hw/arm/bcm2838_peripherals.h
Log Message:
-----------
hw/arm/bcm2838_peripherals: Add clock_isp stub
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2f79d2ed648124f193f813fb26a264997bcb1c38
https://github.com/qemu/qemu/commit/2f79d2ed648124f193f813fb26a264997bcb1c38
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M tests/avocado/boot_linux_console.py
Log Message:
-----------
tests/avocado/boot_linux_console.py: Add Rpi4b boot tests
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Message-id: 20240226000259.2752893-31-sergey.kambalin@auriga.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Comment out use of USB, which depends on PCI]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cda5a7d640d9aa0260a9c21939a30059096715a0
https://github.com/qemu/qemu/commit/cda5a7d640d9aa0260a9c21939a30059096715a0
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/misc/bcm2835_property.c
M include/hw/arm/raspberrypi-fw-defs.h
Log Message:
-----------
hw/misc/bcm2835_property: Add missed BCM2835 properties
Our model of the bcm2835 mailbox is missing a few properties
that we need for the raspi4 kernel:
* RPI_FWREQ_GET_CLOCKS
* RPI_FWREQ_GET_THROTTLED
* RPI_FWREQ_VCHIQ_INIT
Add minimal implementations of them.
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Message-id: 20240226000259.2752893-40-sergey.kambalin@auriga.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: improved commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9c5c959dd748f2972e46a84b8d5f77794f515014
https://github.com/qemu/qemu/commit/9c5c959dd748f2972e46a84b8d5f77794f515014
Author: Sergey Kambalin <serg.oker@gmail.com>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M docs/system/arm/raspi.rst
Log Message:
-----------
docs/system/arm: Add RPi4B to raspi.rst
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240226000259.2752893-42-sergey.kambalin@auriga.com
[PMM: list PCIE and GENET as 'missing' for now, until we land
the patches which add those devices]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b48ff1bfacd6982e26eb8718b61b1b9c3e3e18fe
https://github.com/qemu/qemu/commit/b48ff1bfacd6982e26eb8718b61b1b9c3e3e18fe
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
Merge tag 'pull-aspeed-20240227' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Add support for UART0, in preparation of AST2700 models
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmXd2nMACgkQUaNDx8/7
# 7KErPBAAjKRmJQF9aMEgf7uqsPnJojAVumFe63NE9Gqnvy4MzgoZWfdSnLl2Ddba
# im5IfR7MYv0tzJtqCVtz7o4JwXhhDwesWALQZBM/ms48aacPSNP+7Gn141yLuCCS
# Vr8NBSIz156lSsnFGnRUArcQTDKjDp/1TLRiGcS8SDm/S4Nn++nur+T054EZgbKR
# CMWDeavgzZRb9HPepvWDwqb9qs11hq5/onCqC886dVNznxEKAVYcd0FVbSn3OfDF
# 2EPvKh+fxHlW37wcctlGPnbJK5rRvFi78yZf5utSt+mlVhyiEXjQJ6p8zBIh2w5A
# NlsmUo/UYv1F41yC/vCFRR8KJ2wO5VW7zL6UCGMV6I9hxhu/Qw+FYqWdBbAZWsOO
# GFOkFbe8zbJFXTr/W7P5upBlA7U1/B9VbRj71eu01dqT+n8OGsk8yfnWVs1SjpoD
# 89ZIhpb7lSolQmjPPxrVyfUe3/8ncTx64+CZuAZjxPh/9HA8wDXwVRPtAbIvvGaZ
# YPQ4Qmd4m6nAANAvTg2ufj19WT64XKwrQ6O3IkmGcn0BzHl08GFjru8IUp6rbduG
# m6WqulL1Ej1PrYaiw5ktpJ4Fkoy6iEFXJOWfl3oTLp2KWE5VAohyRKI00AFnHiAC
# frK+cxT4bqDtJR8QbNyJy5d3ZGZV1R6ZA0XjQ1jtb8ty2qISysw=
# =gFeX
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 27 Feb 2024 12:49:55 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20240227' of https://github.com/legoater/qemu:
aspeed: fix hardcode boot address 0
aspeed: introduce a new UART0 device name
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 158a054c4d1a40179f5e83cd7e1cfe65de457b92
https://github.com/qemu/qemu/commit/158a054c4d1a40179f5e83cd7e1cfe65de457b92
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-27 (Tue, 27 Feb 2024)
Changed paths:
M MAINTAINERS
M docs/devel/qom.rst
M docs/devel/reset.rst
M docs/system/arm/raspi.rst
M hw/arm/bcm2835_peripherals.c
M hw/arm/bcm2836.c
A hw/arm/bcm2838.c
A hw/arm/bcm2838_peripherals.c
M hw/arm/meson.build
M hw/arm/raspi.c
A hw/arm/raspi4b.c
M hw/arm/sbsa-ref.c
M hw/arm/stm32l4x5_soc.c
M hw/arm/trace-events
M hw/arm/xlnx-versal-virt.c
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
M hw/core/machine.c
M hw/core/meson.build
M hw/core/reset.c
A hw/core/resetcontainer.c
A hw/gpio/bcm2838_gpio.c
M hw/gpio/meson.build
M hw/misc/bcm2835_property.c
M hw/rtc/m48t59.c
M hw/rtc/pl031.c
M hw/ssi/xlnx-versal-ospi.c
M hw/timer/pxa2xx_timer.c
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/bcm2836.h
A include/hw/arm/bcm2838.h
A include/hw/arm/bcm2838_peripherals.h
M include/hw/arm/raspberrypi-fw-defs.h
M include/hw/arm/raspi_platform.h
M include/hw/arm/stm32l4x5_soc.h
A include/hw/core/resetcontainer.h
M include/hw/display/bcm2835_fb.h
A include/hw/gpio/bcm2838_gpio.h
M include/qom/object.h
M include/sysemu/reset.h
M system/bootdevice.c
M target/arm/cpu64.c
M target/arm/ptw.c
M tests/avocado/boot_linux_console.py
M tests/qtest/stm32l4x5_exti-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240227-1' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Handle atomic updates of page tables entries in MMIO during PTW
* Advertise Cortex-A53 erratum #843419 fix via REVIDR
* MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine
* misc: m48t59: replace qemu_system_reset_request() call with
watchdog_perform_action()
* misc: pxa2xx_timer: replace qemu_system_reset_request() call with
watchdog_perform_action()
* xlnx-versal-ospi: disable reentrancy detection for iomem_dac
* sbsa-ref: Simplify init since PCIe is always enabled
* stm32l4x5: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs
* pl031: Update last RTCLR value on write in case it's read back
* block: m25p80: Add support of mt35xu02gbba
* xlnx-versal-virt: Add machine property ospi-flash
* reset: refactor system reset to be three-phase aware
* new board model raspi4b
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXeAMEZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3syyD/4lJzzstbDIAsu94Z4Hi0So
# CFLAMJFsPy3fMsU2IqVP+TDTyhUeMPebwfj7sQHUtQcXVh5i1/HlYgdUgXsnjGWQ
# pc6BxycpW6uJWYb7Ma3CdSGS+hxEpQ+U8Qeijwqg0kAqhjNtrSIkTRQ4u8p8T+kN
# dWtQzp7D15BpEVhWl/2dLWWJwV3H6TThmr1FbK5wl/c7hJzy2uaXqmmCvercU0Zo
# 6ab3SnGyhaujdd/FsDvhnVEYqcmcO2p9UtSnGAbdfw0zsf4p8cS2Q6M9q4DHBFYn
# 6Bt51DFP5D+114VpqRSXF2Lv9K8swjTgqhDld9vCoios6pS3LMwcTAcONUxE8JU+
# uD7kXTN/lv3atNEy4MTFkTeNtKgbYJJuPwWrDRNdbVXPwrEHGWN3+ZYISmuYb+p+
# XL2/7HeP7/qEVMW2d18+7OCriZwKiBRZRKUrtG7mQSBZEMetbhpA+mLcxAZT0FAl
# 18O/mcvEJrrE7x6Bqyv96b8PE0/er5cVg/b/wrkKS8DL4NWU9bJSjJNRrvt9bvvl
# jSzPGo4ngHlfO0OpurLoFOZCVxKWVXgaKkQ3pOz301nsDyhEndNLeCxrITac8G2Q
# C/WQuMaeOoV1x7N2MzaCQmyRzy8yGkG9av0aI/8feobfV/Yg4wPsfhcEn/XQWXKv
# NUJ4/z78FbJlI2JeDP2QSA==
# =xaMv
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 27 Feb 2024 15:33:21 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240227-1' of
https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
docs/system/arm: Add RPi4B to raspi.rst
hw/misc/bcm2835_property: Add missed BCM2835 properties
tests/avocado/boot_linux_console.py: Add Rpi4b boot tests
hw/arm/bcm2838_peripherals: Add clock_isp stub
hw/arm: Add memory region for BCM2837 RPiVid ASB
hw/arm/raspi4b: Temporarily disable unimplemented rpi4b devices
hw/arm: Introduce Raspberry PI 4 machine
hw/arm: Add GPIO and SD to BCM2838 periph
hw/gpio: Connect SD controller to BCM2838 GPIO
hw/gpio: Implement BCM2838 GPIO functionality
hw/gpio: Add BCM2838 GPIO stub
hw/arm/bcm2838: Add GIC-400 to BCM2838 SoC
hw/arm: Introduce BCM2838 SoC
hw/arm/raspi: Split out raspi machine common part
hw/arm/bcm2853_peripherals: Split out common part of peripherals
hw/arm/bcm2836: Split out common part of BCM283X classes
docs/devel/reset: Update to discuss system reset
hw/core/machine: Use qemu_register_resettable for sysbus reset
hw/core/reset: Implement qemu_register_reset via qemu_register_resettable
hw/core/reset: Add qemu_{register, unregister}_resettable()
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/dccbaf0cc0f1...158a054c4d1a
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications