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[Qemu-commits] [qemu/qemu] 2cc0e4: target/ppc: Fix lxv/stxv MSR facility
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 2cc0e4: target/ppc: Fix lxv/stxv MSR facility check |
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Date: |
Fri, 23 Feb 2024 10:59:40 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 2cc0e449d17310877fb28a942d4627ad22bb68ea
https://github.com/qemu/qemu/commit/2cc0e449d17310877fb28a942d4627ad22bb68ea
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Fix lxv/stxv MSR facility check
The move to decodetree flipped the inequality test for the VEC / VSX
MSR facility check.
This caused application crashes under Linux, where these facility
unavailable interrupts are used for lazy-switching of VEC/VSX register
sets. Getting the incorrect interrupt would result in wrong registers
being loaded, potentially overwriting live values and/or exposing
stale ones.
Cc: qemu-stable@nongnu.org
Reported-by: Joel Stanley <joel@jms.id.au>
Fixes: 70426b5bb738 ("target/ppc: moved stxvx and lxvx from legacy to
decodtree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1769
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Tested-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c8fd9667e5975fe2e70a906e125a758737eab707
https://github.com/qemu/qemu/commit/c8fd9667e5975fe2e70a906e125a758737eab707
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix crash on machine check caused by ifetch
is_prefix_insn_excp() loads the first word of the instruction address
which caused an exception, to determine whether or not it was prefixed
so the prefix bit can be set in [H]SRR1.
This works if the instruction image can be loaded, but if the exception
was caused by an ifetch, this load could fail and cause a recursive
exception and crash. Machine checks caused by ifetch are not excluded
from the prefix check and can crash (see issue 2108 for an example).
Fix this by excluding machine checks caused by ifetch from the prefix
check.
Cc: qemu-stable@nongnu.org
Acked-by: Cédric Le Goater <clg@kaod.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2108
Fixes: 55a7fa34f89 ("target/ppc: Machine check on invalid real address access
on POWER9/10")
Fixes: 5a5d3b23cb2 ("target/ppc: Add SRR1 prefix indication to interrupt
handlers")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: e5f15001448a3cc2cf1b2181ea02cd7b4e03fc56
https://github.com/qemu/qemu/commit/e5f15001448a3cc2cf1b2181ea02cd7b4e03fc56
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M docs/devel/testing.rst
M tests/avocado/boot_linux.py
Log Message:
-----------
tests/avocado: mark boot_linux.py long runtime instead of flaky
The ppc64 and s390x tests were first marked skipIf GITLAB_CI by commit
c0c8687ef0f ("tests/avocado: disable BootLinuxPPC64 test in CI"), and
commit 0f26d94ec9e ("tests/acceptance: skip s390x_ccw_vrtio_tcg on
GitLab") due to being very heavy-weight for gitlab CI.
Commit 9b45cc99318 ("docs/devel: rationalise unstable gitlab tests under
FLAKY_TESTS") changed this to being flaky but it isn't really, it just
had a long runtime.
So take the SPEED=slow variable from qtests and introduce it to avocado,
and make these tests require it.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 458a6aa3b3346c33a9be9441f2f17f2937e88b72
https://github.com/qemu/qemu/commit/458a6aa3b3346c33a9be9441f2f17f2937e88b72
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M tests/avocado/boot_linux_console.py
Log Message:
-----------
tests/avocado: improve flaky ppc/pnv boot_linux_console.py test
The expected MTD partition detection output does not always appear on
the console, despite the test reaching the boot loader and the string
appearing in dmesg. Possibly due to an init script that quietens the
console output. Using an earlier log message improves reliability.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 234aa6d62a2ad5790efcaa2a99c1adf6f5744350
https://github.com/qemu/qemu/commit/234aa6d62a2ad5790efcaa2a99c1adf6f5744350
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M tests/avocado/boot_linux_console.py
Log Message:
-----------
tests/avocado: ppc add powernv10 boot_linux_console test
Add test for POWER10.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 8d07a8aef6feb7d8db4fabdcc3753636c562febe
https://github.com/qemu/qemu/commit/8d07a8aef6feb7d8db4fabdcc3753636c562febe
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M tests/avocado/ppc_powernv.py
M tests/avocado/ppc_pseries.py
Log Message:
-----------
tests/avocado: Add ppc pseries and powernv hash MMU tests
POWER CPUs support hash and radix MMU modes. Linux supports running in
either mode, but defaults to radix. To keep up testing of QEMU's hash
MMU implementation, add some Linux hash boot tests.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 9bf9479328ab3c4a15ef0beb2c93b5e82b8f5209
https://github.com/qemu/qemu/commit/9bf9479328ab3c4a15ef0beb2c93b5e82b8f5209
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M tests/avocado/boot_linux.py
Log Message:
-----------
tests/avocado: Add pseries KVM boot_linux test
ppc has no avocado tests for the KVM backend. Add a KVM boot_linux.py
test for pseries.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c9cb496710758a5d4e05d11a1b0fba1c49c67d34
https://github.com/qemu/qemu/commit/c9cb496710758a5d4e05d11a1b0fba1c49c67d34
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M MAINTAINERS
A tests/avocado/ppc_hv_tests.py
Log Message:
-----------
tests/avocado: ppc add hypervisor tests
The powernv and pseries machines both provide hypervisor facilities
that are supported by KVM. This is a large and complicated set of
features that don't get much system-level testing in ppc tests.
Add a new test case for these which runs QEMU KVM inside the target.
This downloads an Alpine VM image, boots it and downloads and installs
the qemu package, then boots a virtual machine under it, re-using the
original Alpine VM image.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: b41484ccb695fd104776fe9eb964a6360ef2534a
https://github.com/qemu/qemu/commit/b41484ccb695fd104776fe9eb964a6360ef2534a
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M tests/avocado/migration.py
Log Message:
-----------
tests/avocado: Use default CPU for pseries machine
Use the default CPU with the pseries machine unless there is a
specific requirement.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 3d2d2996d771031731b376c65a45600a68b3bb7e
https://github.com/qemu/qemu/commit/3d2d2996d771031731b376c65a45600a68b3bb7e
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M pc-bios/skiboot.lid
M roms/skiboot
Log Message:
-----------
ppc/pnv: Update skiboot to v7.1
This includes a number of improvements and fixes. Importantly there
is a change for QEMU platforms to permit the ChipTOD to be initialised
if it is present in the device tree. This will facilitate ChipTOD
enablement in pnv.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: a5116b959c84f5a631769586bf04b575c88613ba
https://github.com/qemu/qemu/commit/a5116b959c84f5a631769586bf04b575c88613ba
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Rename registers to match ISA
Several registers have names that don't match the ISA (or convention
with other QEMU PPC registers), making them unintuitive to use with
GDB.
Fortunately most of these registers are obscure and/or have not been
correctly implemented in the gdb server (e.g., DEC, TB, CFAR), so risk
of breaking users should be low.
QEMU should follow the ISA for register name convention (where there is
no established GDB name).
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 6cd1da55e8626016a7a74134badee299889a00c0
https://github.com/qemu/qemu/commit/6cd1da55e8626016a7a74134badee299889a00c0
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/spapr_softmmu.c
Log Message:
-----------
hw/ppc/spapr: Add missing license
Commit 9fdf0c2995 ("Start implementing pSeries logical partition
machine") added hw/ppc/spapr_hcall.c, then commit 962104f044
("hw/ppc: moved hcalls that depend on softmmu") extracted the
system code to hw/ppc/spapr_softmmu.c. Take the license and
copyrights from the original spapr_hcall.c at commit 9fdf0c2995.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[npiggin: Update file description.]
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: aea75803a4da88a09526c86f79bbbcdd40d664c2
https://github.com/qemu/qemu/commit/aea75803a4da88a09526c86f79bbbcdd40d664c2
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/spapr_hcall.c
M target/ppc/tcg-stub.c
Log Message:
-----------
hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep
Check tcg_enabled() before calling softmmu_resize_hpt_prepare()
and softmmu_resize_hpt_commit() to allow the compiler to elide
their calls. The stubs are then unnecessary, remove them.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: a3d0cf82df353a96848c021805252d63d677d921
https://github.com/qemu/qemu/commit/a3d0cf82df353a96848c021805252d63d677d921
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_softmmu.c
M include/hw/ppc/spapr.h
Log Message:
-----------
hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr
Since 'softmmu' is quite a loaded term in QEMU, rename the vhyp MMU
facilities to use the vhyp_mmu_ prefix rather than softmmu_.
vhyp_mmu_ is chosen because the code that manipulates the hash table
via guest software hypercalls is QEMU's implementation of the PAPR
hypervisor interface, called vhyp.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[npiggin: Pick a different name, explain it in changelog.]
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 6c568998f3da5dbd27befe781b5e4e742bbaad54
https://github.com/qemu/qemu/commit/6c568998f3da5dbd27befe781b5e4e742bbaad54
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/meson.build
R hw/ppc/spapr_softmmu.c
A hw/ppc/spapr_vhyp_mmu.c
Log Message:
-----------
hw/ppc/spapr: Rename 'softmmu' -> 'vhyp_mmu'
To reduce the use of the term 'softmmu', rename spapr_softmmu.c
to spapr_vhyp_mmu.c.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[np: change name]
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 2df5c1f5b014126595a26c6797089d284a3b211c
https://github.com/qemu/qemu/commit/2df5c1f5b014126595a26c6797089d284a3b211c
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs.
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs property.
It is more appropriate to have its own define which can be further
reused as appropriate for correct interpretation.
Suggested-by: Cedric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Kowshik Jois <kowsjois@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c4f91d7b7be76c47015521ab0109c6e998a369b0
https://github.com/qemu/qemu/commit/c4f91d7b7be76c47015521ab0109c6e998a369b0
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS.
Initialize the machine specific max_cpus limit as per the maximum range
of CPU IPIs available. Keeping between 4096 to 8192 will throw IRQ not
free error due to XIVE/XICS limitation and keeping beyond 8192 will hit
assert in tcg_region_init or spapr_xive_claim_irq.
Logs:
Without patch fix:
[root@host build]# qemu-system-ppc64 -accel tcg -smp 10,maxcpus=4097
qemu-system-ppc64: IRQ 4096 is not free
[root@host build]#
On LPAR:
[root@host build]# qemu-system-ppc64 -accel tcg -smp 10,maxcpus=8193
**
ERROR:../tcg/region.c:774:tcg_region_init: assertion failed:
(region_size >= 2 * page_size)
Bail out! ERROR:../tcg/region.c:774:tcg_region_init: assertion failed:
(region_size >= 2 * page_size)
Aborted (core dumped)
[root@host build]#
On x86:
[root@host build]# qemu-system-ppc64 -accel tcg -smp 10,maxcpus=8193
qemu-system-ppc64: ../hw/intc/spapr_xive.c:596: spapr_xive_claim_irq:
Assertion `lisn < xive->nr_irqs' failed.
Aborted (core dumped)
[root@host build]#
With patch fix:
[root@host build]# qemu-system-ppc64 -accel tcg -smp 10,maxcpus=4097
qemu-system-ppc64: Invalid SMP CPUs 4097. The max CPUs supported by
machine 'pseries-8.2' is 4096
[root@host build]#
Reported-by: Kowshik Jois <kowsjois@linux.ibm.com>
Tested-by: Kowshik Jois <kowsjois@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 51113013f383acc7f98ae988198695ef98bfe7d6
https://github.com/qemu/qemu/commit/51113013f383acc7f98ae988198695ef98bfe7d6
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: change pseries machine default to POWER10 CPU
POWER10 is the latest pseries CPU.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 1392617d35765d5d912625fbb5cab1ffbed8e140
https://github.com/qemu/qemu/commit/1392617d35765d5d912625fbb5cab1ffbed8e140
Author: Cédric Le Goater <clg@kaod.org>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M docs/about/deprecated.rst
M hw/ppc/spapr.c
M roms/skiboot
Log Message:
-----------
spapr: Tag pseries-2.1 - 2.11 machines as deprecated
pseries machines before version 2.11 have undergone many changes to
correct issues, mostly regarding migration compatibility. This is
obfuscating the code uselessly and makes maintenance more difficult.
Remove them and only keep the last version of the 2.x series, 2.12,
still in use by old distros.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 21465ade7ffdc569e5a29bb604dd27a1d36b60b4
https://github.com/qemu/qemu/commit/21465ade7ffdc569e5a29bb604dd27a1d36b60b4
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Change powernv default to powernv10
POWER10 is the latest IBM Power machine. Although it is not offered in
"OPAL mode" (i.e., powernv configuration), so there is a case that it
should remain at powernv9, most of the development work is going into
powernv10 at the moment.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 7b99fb30b39bb14733aa3645b68e0103bbf8e43a
https://github.com/qemu/qemu/commit/7b99fb30b39bb14733aa3645b68e0103bbf8e43a
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/misc/pca9552.c
M tests/qtest/pca9552-test.c
Log Message:
-----------
misc/pca9552: Fix inverted input status
The pca9552 INPUT0 and INPUT1 registers are supposed to
hold the logical values of the LED pins. A logical 0
should be seen in the INPUT0/1 registers for a pin when
its corresponding LSn bits are set to 0, which is also
the state needed for turning on an LED in a typical
usage scenario. Existing code was doing the opposite
and setting INPUT0/1 bit to a 1 when the LSn bit was
set to 0, so this commit fixes that.
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: ff557c272c21692e9fa4d5a18e2d8989485b00e4
https://github.com/qemu/qemu/commit/ff557c272c21692e9fa4d5a18e2d8989485b00e4
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/misc/pca9552.c
M include/hw/misc/pca9552.h
Log Message:
-----------
misc/pca9552: Let external devices set pca9552 inputs
Allow external devices to drive pca9552 input pins by adding
input GPIO's to the model. This allows a device to connect
its output GPIO's to the pca9552 input GPIO's.
In order for an external device to set the state of a pca9552
pin, the pin must first be configured for high impedance (LED
is off). If the pca9552 pin is configured to drive the pin low
(LED is on), then external input will be ignored.
Here is a table describing the logical state of a pca9552 pin
given the state being driven by the pca9552 and an external device:
PCA9552
Configured
State
| Hi-Z | Low |
------+------+-----+
External Hi-Z | Hi | Low |
Device ------+------+-----+
State Low | Low | Low |
------+------+-----+
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: ab8746683c77d0086851bb611b8c52818b6029d2
https://github.com/qemu/qemu/commit/ab8746683c77d0086851bb611b8c52818b6029d2
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: New powernv10-rainier machine type
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 33467ecb86e7938df605d0384a3a0e3e8a57c707
https://github.com/qemu/qemu/commit/33467ecb86e7938df605d0384a3a0e3e8a57c707
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/Kconfig
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control
The Power Hypervisor code expects to see a pca9552 device connected
to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
justified address of 0xC6). This is used by hypervisor code to
control PCIe slot power during hotplug events.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 6f86885a74584f069db95bd6043d9497388808b4
https://github.com/qemu/qemu/commit/6f86885a74584f069db95bd6043d9497388808b4
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Wire up pca9552 GPIO pins for PCIe hotplug power control
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time after it enables power to a PCIe slot by asserting one of
the pca9552 GPIO pins 0-4, it should see a "power good" signal asserted
on one of pca9552 GPIO pins 5-9.
To simulate this behavior, we simply connect the GPIO outputs for
pins 0-4 to the GPIO inputs for pins 5-9.
Each PCIe slot is assigned 3 GPIO pins on the pca9552 device, for
control of up to 5 PCIe slots. The per-slot signal names are:
SLOTx_EN.......PHYP uses this as an output to enable
slot power. We connect this to the
SLOTx_PG pin to simulate a PGOOD signal.
SLOTx_PG.......PHYP uses this as in input to detect
PGOOD for the slot. For our purposes
we just connect this to the SLOTx_EN
output.
SLOTx_Control..PHYP uses this as an output to prevent
a race condition in the real hotplug
circuitry, but we can ignore this output
for simulation.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 7b85f008b68b5c1a59772cad2214366d6cb140f5
https://github.com/qemu/qemu/commit/7b85f008b68b5c1a59772cad2214366d6cb140f5
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv_i2c.c
Log Message:
-----------
ppc/pnv: Use resettable interface to reset child I2C buses
The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have not yet transitioned
to this new interface and use the old reset strategy.
This was preventing the I2C buses and devices wired
to the PNV I2C controller from being reset.
The short term fix for this is to have the PNV I2C
Controller's reset function explicitly call the resettable
interface function, bus_cold_reset(), on all child
I2C buses.
The long term fix should be to transition all PNV parent
devices and buses to use the resettable interface so that
all child buses and devices are automatically reset.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: de0c7d543bcaf4cbde936668817f610bbd18e897
https://github.com/qemu/qemu/commit/de0c7d543bcaf4cbde936668817f610bbd18e897
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M MAINTAINERS
A hw/misc/pca9554.c
A include/hw/misc/pca9554.h
A include/hw/misc/pca9554_regs.h
Log Message:
-----------
misc: Add a pca9554 GPIO device model
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
model does not yet support this.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 6aa4ef32cc06e3846cb1b81d98211ceb96bdfea6
https://github.com/qemu/qemu/commit/6aa4ef32cc06e3846cb1b81d98211ceb96bdfea6
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
M hw/ppc/Kconfig
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Add a pca9554 I2C device to powernv10-rainier
For powernv10-rainier, the Power Hypervisor code expects to see a
pca9554 device connected to the 3rd PNV I2C engine on port 1 at I2C
address 0x25 (or left-justified address of 0x4A). This is used by
the hypervisor code to detect if a "Cable Card" is present.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 4d2cd2d8697164927620fe31f46f4a67e86c4f5f
https://github.com/qemu/qemu/commit/4d2cd2d8697164927620fe31f46f4a67e86c4f5f
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv_i2c.c
A include/hw/i2c/pnv_i2c_regs.h
M tests/qtest/meson.build
A tests/qtest/pnv-host-i2c-test.c
M tests/qtest/pnv-xscom-test.c
A tests/qtest/pnv-xscom.h
Log Message:
-----------
ppc/pnv: Test pnv i2c master and connected devices
Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset
Tests the following for powernv10-ranier only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Connected GPIO pin tests of P10 PCA9552 device. Tests
output of pins 0-4 affect input of pins 5-9 respectively.
- PCA9554 GPIO pins test. Tests input and ouput functionality.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 1adf24708bf7f8506fab6f2d53530af0210e6658
https://github.com/qemu/qemu/commit/1adf24708bf7f8506fab6f2d53530af0210e6658
Author: Chalapathi V <chalapathi.v@linux.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/meson.build
A hw/ppc/pnv_nest_pervasive.c
A include/hw/ppc/pnv_nest_pervasive.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
hw/ppc: Add pnv nest pervasive common chiplet model
A POWER10 chip is divided into logical units called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets have a common basic set of registers and This model will provide
the registers functionality for common registers of nest chiplet (Pervasive
Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
This commit implement the read/write functions of chiplet control registers.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 5706b0064d6a78c32bf46f18910bc4e10dde2687
https://github.com/qemu/qemu/commit/5706b0064d6a78c32bf46f18910bc4e10dde2687
Author: Chalapathi V <chalapathi.v@linux.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/meson.build
A hw/ppc/pnv_n1_chiplet.c
A include/hw/ppc/pnv_n1_chiplet.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
hw/ppc: Add N1 chiplet model
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c295d3b0907ce40d45d9068d875f91363db4c194
https://github.com/qemu/qemu/commit/c295d3b0907ce40d45d9068d875f91363db4c194
Author: Chalapathi V <chalapathi.v@linux.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
hw/ppc: N1 chiplet wiring
This part of the patchset connects the nest1 chiplet model to p10 chip.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 0c0fc268dfd4dbaf59e59377ca8a390f362256ad
https://github.com/qemu/qemu/commit/0c0fc268dfd4dbaf59e59377ca8a390f362256ad
Author: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/gdbstub.c
Log Message:
-----------
target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 19e81ce51e68d9a1e6a317cd3f3e519757d16dfd
https://github.com/qemu/qemu/commit/19e81ce51e68d9a1e6a317cd3f3e519757d16dfd
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/helper_regs.c
M target/ppc/ppc-qmp-cmds.c
Log Message:
-----------
target/ppc: Rename TBL to TB on 64-bit
>From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB
and accessed with mftb instruction. The problem is that TB is the name
of the 64-bit register, and 32-bit implementations can only read the
lower half with one instruction, so 268 has also been called TBL and
it does only read TBL on 32-bit.
Change SPR 268 to be called TB on 64-bit implementations.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 80e28a41479723ad3d5fb092048b7564995f79ef
https://github.com/qemu/qemu/commit/80e28a41479723ad3d5fb092048b7564995f79ef
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Improve timebase register defines naming
The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs at 284 and 285.
The ISA changed around v2.03 to bring TB and TBU reads into the SPR
space at 268 and 269 (access via mftb TBR-space is still supported
but will be phased out). Later, VTB was added which is an entirely
different register.
The SPR number defines in QEMU are understandably inconsistently named.
Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: f6940474fa0db83e1e56a8d0ab955750815e2ccb
https://github.com/qemu/qemu/commit/f6940474fa0db83e1e56a8d0ab955750815e2ccb
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Fix move-to timebase SPR access permissions
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 9a69950feb0983cde8a97f8c7d1623e81b912412
https://github.com/qemu/qemu/commit/9a69950feb0983cde8a97f8c7d1623e81b912412
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/meson.build
A hw/ppc/pnv_chiptod.c
M hw/ppc/trace-events
A include/hw/ppc/pnv_chiptod.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Add POWER9/10 chiptod model
The ChipTOD (for Time-Of-Day) is a chip pervasive facility in IBM POWER
(powernv) processors that keeps a time of day clock.
In particular for this model are facilities that initialise and start
the time of day clock, and that synchronise that clock to cores on the
chip, and to other chips. In this way, all cores on all chips can
synchronise timebase (TB).
This model implements functionality sufficient to run the skiboot
chiptod synchronisation procedure (with the following core timebase
state machine implementation). It does not modify the TB in the cores
where the real hardware would, because the QEMU ppc timebase
implementation is always synchronised acros all cores.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: de3ba0cc38ffb96265f29c2399df0a5c0f301f40
https://github.com/qemu/qemu/commit/de3ba0cc38ffb96265f29c2399df0a5c0f301f40
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines
Wire the ChipTOD model to powernv9 and powernv10 machines.
Suggested-by-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: cde2ba34a951997f01c184acf6e3a29eb6a81e79
https://github.com/qemu/qemu/commit/cde2ba34a951997f01c184acf6e3a29eb6a81e79
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_chiptod.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_chiptod.h
M target/ppc/cpu.h
Log Message:
-----------
ppc/pnv: Implement the ChipTOD to Core transfer
One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.
The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending the TOD value to a SCOM address.
This implementation grabs the core directly and manipulates the
timebase facility state in the core. This is a hack, but it works
enough for now. A better implementation would implement the transfer
to the PnvCore xscom register and drive the timebase state machine
from there.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: d8c14411d0bb5f3d5370e74f8e993eb4eb63c55a
https://github.com/qemu/qemu/commit/d8c14411d0bb5f3d5370e74f8e993eb4eb63c55a
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/cpu.h
M target/ppc/timebase_helper.c
Log Message:
-----------
target/ppc: Implement core timebase state machine and TFMR
This implements the core timebase state machine, which is the core side
of the time-of-day system in POWER processors. This facility is operated
by control fields in the TFMR register, which also contains status
fields.
The core timebase interacts with the chiptod hardware, primarily to
receive TOD updates, to synchronise timebase with other cores. This
model does not actually update TB values with TOD or updates received
from the chiptod, as timebases are always synchronised. It does step
through the states required to perform the update.
There are several asynchronous state transitions. These are modelled
using using mfTFMR to drive state changes, because it is expected that
firmware poll the register to wait for those states. This is good enough
to test basic firmware behaviour without adding real timers. The values
chosen are arbitrary.
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: a21d89b5f4084d8b739d81149e777522f1120e08
https://github.com/qemu/qemu/commit/a21d89b5f4084d8b739d81149e777522f1120e08
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/timebase_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add SMT support to time facilities
The TB, VTB, PURR, HDEC SPRs are per-LPAR registers, and the TFMR is a
per-core register. Add the necessary SMT synchronisation and value
sharing.
The TFMR can only drive the timebase state machine via thread 0 of the
core, which is almost certainly not right, but it is enough for skiboot
and certain other proprietary firmware.
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: e8fe14112bea38377409728b7b0d684bd187ff56
https://github.com/qemu/qemu/commit/e8fe14112bea38377409728b7b0d684bd187ff56
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Fix 440 tlbwe TLB invalidation gaps
The 440 tlbwe (write entry) instruction misses several cases that must
flush the TCG TLB:
- If the new size is smaller than the existing size, the EA no longer
covered should be flushed. This looks like an inverted inequality
test.
- If the TLB PID changes.
- If the TLB attr bit 0 (translation address space) changes.
- If low prot (access control) bits change.
Fix this by removing tricks to avoid TLB flushes, and just invalidate
the TLB if any valid entry is being changed, similarly to 4xx.
Optimisations will be introduced in subsequent changes.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c191ad779372cc3b355ef10a355de8bb9b92efdc
https://github.com/qemu/qemu/commit/c191ad779372cc3b355ef10a355de8bb9b92efdc
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Factor out 4xx ppcemb_tlb_t flushing
Flushing the TCG TLB pages that cache a software TLB is a common
operation, factor it into its own function.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 372dbdb90c2cbe391d98649ca1f91a57b268b613
https://github.com/qemu/qemu/commit/372dbdb90c2cbe391d98649ca1f91a57b268b613
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: 4xx don't flush TLB for a newly written software TLB entry
BookE software TLB is implemented by flushing old translations from the
relevant TCG TLB whenever software TLB entries change. This means a new
software TLB entry should not have any corresponding cached TCG TLB
translations, so there is nothing to flush. The exception is multiple
software TLBs that cover the same address and address space, but that is
a programming error and results in undefined behaviour, and flushing
does not give an obviously better outcome in that case either.
Remove the unnecessary flush of a newly written software TLB entry.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 2ab03484819d529184927314f3b541d7c2221b4a
https://github.com/qemu/qemu/commit/2ab03484819d529184927314f3b541d7c2221b4a
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: 4xx optimise tlbwe_lo TLB flushing
Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
those corresponding to the old software TLB, and only if it was valid.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 1b72973d39b601b3766d157d3d9bf99033c35e7f
https://github.com/qemu/qemu/commit/1b72973d39b601b3766d157d3d9bf99033c35e7f
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: 440 optimise tlbwe TLB flushing
Have 440 tlbwe flush only the range corresponding to the addresses
covered by the software TLB entry being modified rather than the
entire TLB. This matches what 4xx does.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 4acc505d2236190efea94746e7f22e2c07bce5d6
https://github.com/qemu/qemu/commit/4acc505d2236190efea94746e7f22e2c07bce5d6
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: optimise ppcemb_tlb_t flushing
Filter TLB flushing by PID and mmuidx.
Zoltan reports that, together with the previous TLB flush changes,
performance of a sam460ex machine running 'lame' to convert a wav to
mp3 is improved nearly 10%:
CPU time TLB partial flushes TLB elided flushes
Before 37s 508238 7680722
After 34s 73 1143
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 91e3bf2e925671eb37e3b71cf7fdeb6b7f30248c
https://github.com/qemu/qemu/commit/91e3bf2e925671eb37e3b71cf7fdeb6b7f30248c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-23 (Fri, 23 Feb 2024)
Changed paths:
M MAINTAINERS
M docs/about/deprecated.rst
M docs/devel/testing.rst
M hw/misc/Kconfig
M hw/misc/meson.build
M hw/misc/pca9552.c
A hw/misc/pca9554.c
M hw/ppc/Kconfig
M hw/ppc/meson.build
M hw/ppc/pnv.c
A hw/ppc/pnv_chiptod.c
M hw/ppc/pnv_i2c.c
A hw/ppc/pnv_n1_chiplet.c
A hw/ppc/pnv_nest_pervasive.c
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_irq.c
R hw/ppc/spapr_softmmu.c
A hw/ppc/spapr_vhyp_mmu.c
M hw/ppc/trace-events
A include/hw/i2c/pnv_i2c_regs.h
M include/hw/misc/pca9552.h
A include/hw/misc/pca9554.h
A include/hw/misc/pca9554_regs.h
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_chip.h
A include/hw/ppc/pnv_chiptod.h
A include/hw/ppc/pnv_n1_chiplet.h
A include/hw/ppc/pnv_nest_pervasive.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
M pc-bios/skiboot.lid
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/gdbstub.c
M target/ppc/helper_regs.c
M target/ppc/mmu_helper.c
M target/ppc/ppc-qmp-cmds.c
M target/ppc/tcg-stub.c
M target/ppc/timebase_helper.c
M target/ppc/translate.c
M target/ppc/translate/vsx-impl.c.inc
M tests/avocado/boot_linux.py
M tests/avocado/boot_linux_console.py
M tests/avocado/migration.py
A tests/avocado/ppc_hv_tests.py
M tests/avocado/ppc_powernv.py
M tests/avocado/ppc_pseries.py
M tests/qtest/meson.build
M tests/qtest/pca9552-test.c
A tests/qtest/pnv-host-i2c-test.c
M tests/qtest/pnv-xscom-test.c
A tests/qtest/pnv-xscom.h
Log Message:
-----------
Merge tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu into
staging
* Avocado tests for ppc64 to boot FreeBSD, run guests with emulated
or nested hypervisor facilities, among other things.
* Update ppc64 CPU defaults to Power10.
* Add a new powernv10-rainier machine to better capture differences
between the different Power10 systems.
* Implement more device models for powernv.
* 4xx TLB flushing performance and correctness improvements.
* Correct gdb implementation to access some important SPRs.
* Misc cleanups and bug fixes.
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# gpg: Signature made Fri 23 Feb 2024 15:27:57 GMT
# gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE
* tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu: (47
commits)
target/ppc: optimise ppcemb_tlb_t flushing
target/ppc: 440 optimise tlbwe TLB flushing
target/ppc: 4xx optimise tlbwe_lo TLB flushing
target/ppc: 4xx don't flush TLB for a newly written software TLB entry
target/ppc: Factor out 4xx ppcemb_tlb_t flushing
target/ppc: Fix 440 tlbwe TLB invalidation gaps
target/ppc: Add SMT support to time facilities
target/ppc: Implement core timebase state machine and TFMR
ppc/pnv: Implement the ChipTOD to Core transfer
ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines
ppc/pnv: Add POWER9/10 chiptod model
target/ppc: Fix move-to timebase SPR access permissions
target/ppc: Improve timebase register defines naming
target/ppc: Rename TBL to TB on 64-bit
target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U
hw/ppc: N1 chiplet wiring
hw/ppc: Add N1 chiplet model
hw/ppc: Add pnv nest pervasive common chiplet model
ppc/pnv: Test pnv i2c master and connected devices
ppc/pnv: Add a pca9554 I2C device to powernv10-rainier
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/ffa951df7c7a...91e3bf2e9256
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- [Qemu-commits] [qemu/qemu] 2cc0e4: target/ppc: Fix lxv/stxv MSR facility check,
Peter Maydell <=