[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 4677ca: hw/block/tc58128: Don't emit deprecat
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 4677ca: hw/block/tc58128: Don't emit deprecation warning u... |
|
Date: |
Fri, 16 Feb 2024 05:31:40 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 4677ca5f25e3dd9e998089cefae6786482ed21d3
https://github.com/qemu/qemu/commit/4677ca5f25e3dd9e998089cefae6786482ed21d3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/block/tc58128.c
Log Message:
-----------
hw/block/tc58128: Don't emit deprecation warning under qtest
Suppress the deprecation warning when we're running under qtest,
to avoid "make check" including warning messages in its output.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240206154151.155620-1-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 8fd38e58f0288199b42d8d94d09593b74161c4ae
https://github.com/qemu/qemu/commit/8fd38e58f0288199b42d8d94d09593b74161c4ae
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/mips/Kconfig
Log Message:
-----------
hw/mips: remove unnecessary "select PTIMER"
There is no use of ptimer functions in mips_cps.c or any other related
code.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240129115811.1039965-1-pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 86468930a13400d94b1626f54355214da0daf504
https://github.com/qemu/qemu/commit/86468930a13400d94b1626f54355214da0daf504
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/mips/cpu.h
Log Message:
-----------
target/mips: Use qemu_irq typedef for CPUMIPSState::irq member
Missed during commit d537cf6c86 ("Unify IRQ handling")
when qemu_irq typedef was introduced for IRQState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240130111111.6372-1-philmd@linaro.org>
Commit: e1152f8166d34c36a1dec4c3e6532be02411a1ad
https://github.com/qemu/qemu/commit/e1152f8166d34c36a1dec4c3e6532be02411a1ad
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/mips/tcg/sysemu/cp0_helper.c
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Remove helpers accessing SAAR registers
DisasContext::saar boolean is never set, so this code
is not reachable. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-2-philmd@linaro.org>
Commit: 77599a696df748e89b8f6610fe8dafaa6986729d
https://github.com/qemu/qemu/commit/77599a696df748e89b8f6610fe8dafaa6986729d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/misc/mips_itu.c
M include/hw/misc/mips_itu.h
Log Message:
-----------
hw/misc/mips: Reduce itc_reconfigure() scope
Previous commit removed the MT*C0(SAAR) helpers which
were the only calls to itc_reconfigure() out of hw/,
we can reduce its scope and declare it statically.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-3-philmd@linaro.org>
Commit: b267e78908afd450433ef44d840c4ff30ba37676
https://github.com/qemu/qemu/commit/b267e78908afd450433ef44d840c4ff30ba37676
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/mips/cps.c
M target/mips/cpu.h
Log Message:
-----------
target/mips: Remove MIPSITUState::itu field
Previous commits removed the MT*C0(SAAR) helpers which
were using CPUMIPSState::itu, we can now remove it too.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-4-philmd@linaro.org>
Commit: c2bb8e1bcccb9d8228bc2ec55bbcbdb8f1ce774c
https://github.com/qemu/qemu/commit/c2bb8e1bcccb9d8228bc2ec55bbcbdb8f1ce774c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/misc/mips_itu.c
M target/mips/cpu.h
Log Message:
-----------
target/mips: Remove CPUMIPSState::saarp field
This field is never set, so remove the unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-5-philmd@linaro.org>
Commit: b8db6be27b2a31ec34640bc7812c4c7b691e71be
https://github.com/qemu/qemu/commit/b8db6be27b2a31ec34640bc7812c4c7b691e71be
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/mips/cps.c
M hw/misc/mips_itu.c
M include/hw/misc/mips_itu.h
Log Message:
-----------
hw/misc/mips_itu: Remove MIPSITUState::cpu0 field
Since previous commit the MIPSITUState::cpu0 field is not
used anymore. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-6-philmd@linaro.org>
Commit: 48e06b647155cc10ee8cc62fd1a70d8812eec850
https://github.com/qemu/qemu/commit/48e06b647155cc10ee8cc62fd1a70d8812eec850
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/misc/mips_itu.c
M include/hw/misc/mips_itu.h
Log Message:
-----------
hw/misc/mips_itu: Remove MIPSITUState::saar field
This field is not set. Remove it along with the dead
code it was guarding.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-7-philmd@linaro.org>
Commit: addd0c28741df1a503a97a45e9dc4976ea8e0b9a
https://github.com/qemu/qemu/commit/addd0c28741df1a503a97a45e9dc4976ea8e0b9a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/mips/internal.h
Log Message:
-----------
target/mips: Remove unused mips_def_t::SAARP field
The SAARP field added in commit 5fb2dcd179 ("target/mips: Provide
R/W access to SAARI and SAAR CP0 registers") has never been used,
remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240215080629.51190-1-philmd@linaro.org>
Commit: 5235993f98f2842253b59d3ce786290b4644ca51
https://github.com/qemu/qemu/commit/5235993f98f2842253b59d3ce786290b4644ca51
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/mips/cpu.h
M target/mips/sysemu/machine.c
Log Message:
-----------
target/mips: Remove CPUMIPSState::CP0_SAAR[2] field
Remove the unused CP0_SAAR[2] registers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-8-philmd@linaro.org>
Commit: ee58fddcbbb2374b62065cd97888e4478aa02a95
https://github.com/qemu/qemu/commit/ee58fddcbbb2374b62065cd97888e4478aa02a95
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/mips/tcg/sysemu/cp0_helper.c
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Remove helpers accessing SAARI register
DisasContext::saar boolean is never set, so this code
is not reachable. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-9-philmd@linaro.org>
Commit: fa82742621c3d26cde6383b1c0f891d23f01078f
https://github.com/qemu/qemu/commit/fa82742621c3d26cde6383b1c0f891d23f01078f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/mips/cpu.h
M target/mips/sysemu/machine.c
Log Message:
-----------
target/mips: Remove CPUMIPSState::CP0_SAARI field
Remove the unused CP0_SAARI register.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-10-philmd@linaro.org>
Commit: 747448d11a83af130b04b00e0ef62fc99a0b761a
https://github.com/qemu/qemu/commit/747448d11a83af130b04b00e0ef62fc99a0b761a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/mips/tcg/translate.h
Log Message:
-----------
target/mips: Remove the unused DisasContext::saar field
DisasContext::saar is not used, remove it.
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-11-philmd@linaro.org>
Commit: 5939fc749102c5bc0b6e87571ceba93610b2099c
https://github.com/qemu/qemu/commit/5939fc749102c5bc0b6e87571ceba93610b2099c
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/isa/Kconfig
Log Message:
-----------
hw/isa: clean up Kconfig selections for ISA_SUPERIO
All users of ISA_SUPERIO include a floppy disk controller, serial port
and parallel port via the automatic creation mechanism of isa-superio.c.
Select the symbol and remove it from the dependents.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <20240213155005.109954-3-pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e6f2193367a6b060b65c8898c02d0502f8aaa7e5
https://github.com/qemu/qemu/commit/e6f2193367a6b060b65c8898c02d0502f8aaa7e5
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/mips/Kconfig
M hw/mips/mipssim.c
Log Message:
-----------
hw/mips/Kconfig: Remove ISA dependencies from MIPSsim board
The board doesn't have a working ISA bus, only some I/O space.
Selecting ISA_BUS and including hw/isa/isa.h is not necessary.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20230109204124.102592-3-shentey@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240213155005.109954-4-pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: cf5f5f9235bca5f838087f63c1c1b3c5be591b1b
https://github.com/qemu/qemu/commit/cf5f5f9235bca5f838087f63c1c1b3c5be591b1b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/isa/Kconfig
Log Message:
-----------
hw/isa: fix ISA_SUPERIO dependencies
ISA_SUPERIO does not provide an ISA bus, so it should not select the symbol:
instead it requires one. Among its users, VT82C686 is the only one that
is a PCI-ISA bridge and does not already select ISA_BUS.
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <20240213155005.109954-5-pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 413d0ccb05de21491bc9d0c461e47034f50fd6af
https://github.com/qemu/qemu/commit/413d0ccb05de21491bc9d0c461e47034f50fd6af
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/isa/isa-superio.c
M hw/isa/smc37c669-superio.c
Log Message:
-----------
hw/isa: specify instance_size in isa_superio_type_info
Right now all subclasses of TYPE_ISA_SUPERIO have to specify an instance_size,
because the ISASuperIODevice struct adds fields to ISADevice but the type does
not include the increased instance size. Failure to do so results in an access
past the bounds of struct ISADevice as soon as isa_superio_realize is called.
Fix this by specifying the instance_size already in the superclass.
Fixes: 4c3119a6e3 ("hw/isa/superio: Factor out the parallel code from
pc87312.c")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <20240213155005.109954-6-pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: fbd758008f0f86caf703c2ba2bd6a45ddb37b9f0
https://github.com/qemu/qemu/commit/fbd758008f0f86caf703c2ba2bd6a45ddb37b9f0
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M MAINTAINERS
M hw/isa/Kconfig
A hw/isa/fdc37m81x-superio.c
M hw/isa/isa-superio.c
M hw/isa/meson.build
M hw/mips/Kconfig
Log Message:
-----------
hw/isa: extract FDC37M81X to a separate file
isa-superio.c currently defines a SuperIO chip that is not used
by any other user of the file. Extract the chip to a separate file.
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <20240213155005.109954-7-pbonzini@redhat.com>
[PMD: Update MAINTAINERS]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7188dfcda239ff2460fe8b0994e22e4b3a21dc17
https://github.com/qemu/qemu/commit/7188dfcda239ff2460fe8b0994e22e4b3a21dc17
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/rx/rx-gdbsim.c
M hw/rx/rx62n.c
M include/hw/rx/rx62n.h
Log Message:
-----------
hw/rx/rx62n: Reduce inclusion of 'qemu/units.h'
"qemu/units.h" is not used in the "hw/rx/rx62n.h"
header, include it in the source where it is.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-3-philmd@linaro.org>
Commit: 2e0b925a341ddaa4be577542c74aa19b992215c0
https://github.com/qemu/qemu/commit/2e0b925a341ddaa4be577542c74aa19b992215c0
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/rx/rx62n.c
M include/hw/rx/rx62n.h
Log Message:
-----------
hw/rx/rx62n: Only call qdev_get_gpio_in() when necessary
Instead of filling an array of all the possible IRQs, only call
qdev_get_gpio_in() when an IRQ is used. Remove the array from
RX62NState. Doing so we avoid calling qdev_get_gpio_in() on an
unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-4-philmd@linaro.org>
Commit: fc11ca08bc29d90ac7b18554c406145669c960c0
https://github.com/qemu/qemu/commit/fc11ca08bc29d90ac7b18554c406145669c960c0
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/i386/pc_q35.c
Log Message:
-----------
hw/i386/q35: Realize LPC PCI function before accessing it
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Damien Hedde <dhedde@kalrayinc.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-5-philmd@linaro.org>
Commit: 59ae6bcddc3651b55b96c2bf05a6cd4312e46d10
https://github.com/qemu/qemu/commit/59ae6bcddc3651b55b96c2bf05a6cd4312e46d10
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/ppc/prep.c
Log Message:
-----------
hw/ppc/prep: Realize ISA bridge before accessing it
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-6-philmd@linaro.org>
Commit: fc432ba0f58343c8912b80e9056315bb9bd8df92
https://github.com/qemu/qemu/commit/fc432ba0f58343c8912b80e9056315bb9bd8df92
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/misc/macio/macio.c
Log Message:
-----------
hw/misc/macio: Realize IDE controller before accessing it
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-7-philmd@linaro.org>
Commit: 3c5f86a22686ef475a8259c0d8ee714f61c770c9
https://github.com/qemu/qemu/commit/3c5f86a22686ef475a8259c0d8ee714f61c770c9
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sh4/r2d.c
Log Message:
-----------
hw/sh4/r2d: Realize IDE controller before accessing it
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-8-philmd@linaro.org>
Commit: 5e37bc4997c32a1c9a6621a060462c84df9f1b8f
https://github.com/qemu/qemu/commit/5e37bc4997c32a1c9a6621a060462c84df9f1b8f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/dma/i82374.c
M hw/dma/i8257.c
M hw/i386/pc_piix.c
M hw/isa/lpc_ich9.c
M hw/isa/piix.c
M hw/isa/vt82c686.c
M hw/mips/jazz.c
M include/hw/dma/i8257.h
Log Message:
-----------
hw/dma: Pass parent object to i8257_dma_init()
Set I8257 instances parent (migration isn't affected).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213114426.87836-1-philmd@linaro.org>
Commit: 73a143b3404c65e54c35d514b1917edda9469185
https://github.com/qemu/qemu/commit/73a143b3404c65e54c35d514b1917edda9469185
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/sun4m.c
Log Message:
-----------
hw/sparc/sun4m: Realize DMA controller before accessing it
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-9-philmd@linaro.org>
Commit: 0177d61bb576b46b37712f39bf8b898628c44848
https://github.com/qemu/qemu/commit/0177d61bb576b46b37712f39bf8b898628c44848
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc64/sparc64.c
Log Message:
-----------
hw/sparc64/cpu: Initialize GPIO before realizing CPU devices
Inline cpu_create() in order to call
qdev_init_gpio_in_named_with_opaque()
before the CPU is realized.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Damien Hedde <dhedde@kalrayinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213130341.1793-13-philmd@linaro.org>
Commit: d08b7af3f7f27f6f3da8446756bf0b9352026b1d
https://github.com/qemu/qemu/commit/d08b7af3f7f27f6f3da8446756bf0b9352026b1d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/sparc/cpu.h
Log Message:
-----------
target/sparc: Provide hint about CPUSPARCState::irq_manager member
CPUSPARCState::irq_manager holds a pointer to a QDev,
so declare it as DeviceState instead of void.
Move the comment about Leon3 fields.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Clément Chigot <chigot@adacore.com>
Message-Id: <20240130113102.6732-3-philmd@linaro.org>
Commit: c90e6e37083a7ca3b53838429591196db31fec0e
https://github.com/qemu/qemu/commit/c90e6e37083a7ca3b53838429591196db31fec0e
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: Remove duplicate code
Since commit b04d989054 ("SPARC: Emulation of Leon3") the
main_cpu_reset() handler sets both pc/npc when the CPU is
reset, after the machine is realized. It is pointless to
set it in leon3_generic_hw_init().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Clément Chigot <chigot@adacore.com>
Message-Id: <20240130113102.6732-3-philmd@linaro.org>
Commit: a7b3c3797e81872084fa533dc3faaebfd6434d79
https://github.com/qemu/qemu/commit/a7b3c3797e81872084fa533dc3faaebfd6434d79
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: Remove unused 'env' argument of write_bootloader()
'CPUSPARCState *env' argument is unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20240215132824.67363-2-philmd@linaro.org>
Commit: 047521050a857600838b2d4be4cde42d52cac4f1
https://github.com/qemu/qemu/commit/047521050a857600838b2d4be4cde42d52cac4f1
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: Have write_bootloader() take a void pointer argument
Directly use the void pointer argument returned
by memory_region_get_ram_ptr().
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240215132824.67363-3-philmd@linaro.org>
Commit: f432962e72de4d820b11294ae3e51f2aa5643265
https://github.com/qemu/qemu/commit/f432962e72de4d820b11294ae3e51f2aa5643265
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/char/grlib_apbuart.c
M hw/intc/grlib_irqmp.c
M hw/sparc/leon3.c
M hw/timer/grlib_gptimer.c
A include/hw/char/grlib_uart.h
A include/hw/intc/grlib_irqmp.h
R include/hw/sparc/grlib.h
A include/hw/timer/grlib_gptimer.h
Log Message:
-----------
hw/sparc/grlib: split out the headers for each peripherals
Split out the headers for each peripherals and move them in their
right hardware directory.
Update Copyright and add SPDX-License-Identifier at the same time.
Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-2-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 6bf147854395f39fe45abebe40529bf7f023aeb9
https://github.com/qemu/qemu/commit/6bf147854395f39fe45abebe40529bf7f023aeb9
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/intc/grlib_irqmp.c
M hw/sparc/leon3.c
Log Message:
-----------
hw/intc/grlib_irqmp: add ncpus property
This adds a "ncpus" property to the "grlib-irqmp" device to be used
later, this required a little refactoring of how we initialize the
device (ie: use realize instead of init).
Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-3-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7ed9a5f626a6c932a8c869a91e6a8b3e2029f5ef
https://github.com/qemu/qemu/commit/7ed9a5f626a6c932a8c869a91e6a8b3e2029f5ef
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/intc/grlib_irqmp.c
Log Message:
-----------
hw/intc/grlib_irqmp: implements the multiprocessor status register
This implements the multiprocessor status register in grlib-irqmp and
bind it to a start signal, which will be later wired in leon3-generic
to start a cpu.
The EIRQ and BA bits are not implemented.
Based on https://gaisler.com/doc/gr712rc-usermanual.pdf, §8.3.5.
Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-4-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0fa5cd4a6016c0dc13c2882f63b58787cf3283bb
https://github.com/qemu/qemu/commit/0fa5cd4a6016c0dc13c2882f63b58787cf3283bb
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/intc/grlib_irqmp.c
M hw/sparc/leon3.c
M include/hw/intc/grlib_irqmp.h
Log Message:
-----------
hw/intc/grlib_irqmp: implements multicore irq
Now there is an ncpus property, use it in order to deliver the IRQ to
multiple CPU.
Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-5-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: c92948f22b0ef62d7b5a6a73e943a110f761273b
https://github.com/qemu/qemu/commit/c92948f22b0ef62d7b5a6a73e943a110f761273b
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M target/sparc/helper.c
M target/sparc/helper.h
M target/sparc/translate.c
Log Message:
-----------
target/sparc: implement asr17 feature for smp
This allows the guest program to know its cpu id.
Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-6-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 92688a91c35852e7492d718d7872a6bc725ddff4
https://github.com/qemu/qemu/commit/92688a91c35852e7492d718d7872a6bc725ddff4
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: remove SP initialization
According to the doc (see §4.2.15 in [1]), the reset operation should
not impact %SP.
[1] https://gaisler.com/doc/gr712rc-usermanual.pdf
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-7-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: d65aba8286e40bc02f26f19e53fa20c9396d02e7
https://github.com/qemu/qemu/commit/d65aba8286e40bc02f26f19e53fa20c9396d02e7
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: implement multiprocessor
This allows to register more than one CPU on the leon3_generic machine.
Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Message-ID: <20240131085047.18458-8-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 56bd9678ef553498274f1d29ebb2839f220bce6d
https://github.com/qemu/qemu/commit/56bd9678ef553498274f1d29ebb2839f220bce6d
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: check cpu_id in the tiny bootloader
Now that SMP is possible, the asr17 must be checked in the little boot
code or the secondary CPU will reinitialize the Timer and the Uart.
Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-9-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 5c7127ee1ce1a4fefc13a12da12fb738b2b9174c
https://github.com/qemu/qemu/commit/5c7127ee1ce1a4fefc13a12da12fb738b2b9174c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: Pass DeviceState opaque argument to leon3_set_pil_in()
By passing a DeviceState context to a QDev IRQ handler,
we can simplify and use qdev_init_gpio_in_named() instead
of qdev_init_gpio_in_named_with_opaque().
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20240215144623.76233-2-philmd@linaro.org>
Commit: 08507399ab4d7a77c5a1b398eb37a06a2ebebd01
https://github.com/qemu/qemu/commit/08507399ab4d7a77c5a1b398eb37a06a2ebebd01
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: Pass DeviceState opaque argument to leon3_start_cpu()
By passing a DeviceState context to a QDev IRQ handler,
we can simplify and use qdev_init_gpio_in_named() instead
of qdev_init_gpio_in_named_with_opaque().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20240215144623.76233-3-philmd@linaro.org>
Commit: 0f0554c6fa1785f4f432992e4446becc75a7bbd9
https://github.com/qemu/qemu/commit/0f0554c6fa1785f4f432992e4446becc75a7bbd9
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: Initialize GPIO before realizing CPU devices
Inline cpu_create() in order to call qdev_init_gpio_in_named()
before the CPU is realized.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20240215144623.76233-4-philmd@linaro.org>
Commit: 9e2a7ca180f969e577b556c76e34e592e188bc9a
https://github.com/qemu/qemu/commit/9e2a7ca180f969e577b556c76e34e592e188bc9a
Author: Clément Chigot <chigot@adacore.com>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: replace Fabien by myself as Leon3 maintainer
CC: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
Message-ID: <20240131085047.18458-10-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1a8081d9bd7548bfb66bd0f6c12a1197ac37e12e
https://github.com/qemu/qemu/commit/1a8081d9bd7548bfb66bd0f6c12a1197ac37e12e
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add myself as reviewer for TCG Plugins
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20240118032400.3762658-14-pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 88ad980c0fa8fa47c844f4d8c09fdbcc5d3c8c1d
https://github.com/qemu/qemu/commit/88ad980c0fa8fa47c844f4d8c09fdbcc5d3c8c1d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/i386/pc_q35.c
Log Message:
-----------
hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled
We can not create the Q35 machine without PCI, so simplify
pc_q35_init() removing pointless checks.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213041952.58840-1-philmd@linaro.org>
Commit: 1a8e2f58c5dd721086284f827326b370d19ad9eb
https://github.com/qemu/qemu/commit/1a8e2f58c5dd721086284f827326b370d19ad9eb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/i386/pc_q35.c
Log Message:
-----------
hw/i386/q35: Use DEVICE() cast macro with PCIDevice object
QDev API provides the DEVICE() macro to access the
'qdev' parent field of the PCIDevice structure.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-2-philmd@linaro.org>
Commit: d407be0877d8397218c6b79e5ad8b25267f6f5f1
https://github.com/qemu/qemu/commit/d407be0877d8397218c6b79e5ad8b25267f6f5f1
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/i386/pc_q35.c
M hw/ide/ahci.c
M hw/ide/ahci_internal.h
M hw/ide/ich.c
M hw/mips/boston.c
A include/hw/ide/ahci-pci.h
M include/hw/ide/ahci.h
Log Message:
-----------
hw/ide/ahci: Expose AHCIPCIState structure
In order to be able to QOM-embed a structure, we need
its full definition. Move it from "ahci_internal.h"
to the new "hw/ide/ahci-pci.h" header.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-3-philmd@linaro.org>
Commit: 41c05b41e3b3c5b6b167c315d0f25eb355dcc326
https://github.com/qemu/qemu/commit/41c05b41e3b3c5b6b167c315d0f25eb355dcc326
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/i386/pc_q35.c
M hw/mips/boston.c
Log Message:
-----------
hw/ide/ahci: Rename AHCI PCI function as 'pdev'
We want to access AHCIPCIState::ahci field. In order to keep
the code simple (avoiding &ahci->ahci), rename the current
'ahci' variable as 'pdev'
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-4-philmd@linaro.org>
Commit: e6097f186416df368a7f87a37f0a7fd25de587ba
https://github.com/qemu/qemu/commit/e6097f186416df368a7f87a37f0a7fd25de587ba
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/i386/pc_q35.c
M hw/ide/ahci.c
M hw/mips/boston.c
M include/hw/ide/ahci.h
Log Message:
-----------
hw/ide/ahci: Inline ahci_get_num_ports()
Introduce the 'ich9' variable and inline ahci_get_num_ports().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-5-philmd@linaro.org>
Commit: e2f8d28005acdfa4e7edd6c842c6e9527a901ba5
https://github.com/qemu/qemu/commit/e2f8d28005acdfa4e7edd6c842c6e9527a901ba5
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/i386/pc_q35.c
M hw/ide/ahci.c
M hw/mips/boston.c
M include/hw/ide/ahci.h
Log Message:
-----------
hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs()
Since ahci_ide_create_devs() is not PCI specific, pass
it an AHCIState argument instead of PCIDevice.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-6-philmd@linaro.org>
Commit: 44c11b2e69d845e487d0184079899ef15ab626a5
https://github.com/qemu/qemu/commit/44c11b2e69d845e487d0184079899ef15ab626a5
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/ide/ahci.c
M include/hw/ide/ahci.h
Log Message:
-----------
hw/ide/ahci: Convert AHCIState::ports to unsigned
AHCIState::ports should be unsigned. Besides, we never
check it for negative value. It is unlikely it was ever
used with more than INT32_MAX ports, so it is safe to
convert it to unsigned.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-7-philmd@linaro.org>
Commit: be02150167044e34d3c5ec5d9e84e8470e9a8166
https://github.com/qemu/qemu/commit/be02150167044e34d3c5ec5d9e84e8470e9a8166
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/ide/ahci.c
M hw/ide/ahci_internal.h
M hw/ide/ich.c
Log Message:
-----------
hw/ide/ahci: Do not pass 'ports' argument to ahci_realize()
Explicitly set AHCIState::ports before calling ahci_realize().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-8-philmd@linaro.org>
Commit: b0bccc6a9af57d6adb73041e94d7cd5b1554fc0b
https://github.com/qemu/qemu/commit/b0bccc6a9af57d6adb73041e94d7cd5b1554fc0b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/ide/ahci.c
M include/hw/ide/ahci.h
Log Message:
-----------
hw/ide/ahci: Remove SysbusAHCIState::num_ports field
No need to duplicate AHCIState::ports, directly access it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240213081201.78951-9-philmd@linaro.org>
Commit: fbb5945e859301e375fb919cb72b86b06116b998
https://github.com/qemu/qemu/commit/fbb5945e859301e375fb919cb72b86b06116b998
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/arm/highbank.c
M hw/arm/sbsa-ref.c
M hw/ide/ahci-allwinner.c
M hw/ide/ahci.c
M include/hw/arm/allwinner-a10.h
M include/hw/arm/allwinner-r40.h
M include/hw/arm/xlnx-zynqmp.h
A include/hw/ide/ahci-sysbus.h
M include/hw/ide/ahci.h
Log Message:
-----------
hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h'
Keep "hw/ide/ahci.h" AHCI-generic.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20240213081201.78951-10-philmd@linaro.org>
Commit: 9a4b35f57eefbfc6977ed47d1f19d839e9e4784d
https://github.com/qemu/qemu/commit/9a4b35f57eefbfc6977ed47d1f19d839e9e4784d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-15 (Thu, 15 Feb 2024)
Changed paths:
M hw/ide/ich.c
Log Message:
-----------
hw/ide/ich9: Use AHCIPCIState typedef
QEMU coding style recommend using structure typedefs:
https://www.qemu.org/docs/master/devel/style.html#typedefs
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240208181245.96617-2-philmd@linaro.org>
Commit: 8e31b744fdf2c5d933681e4128acee72a83af4b8
https://github.com/qemu/qemu/commit/8e31b744fdf2c5d933681e4128acee72a83af4b8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-16 (Fri, 16 Feb 2024)
Changed paths:
M .gitlab-ci.d/windows.yml
Log Message:
-----------
.gitlab-ci/windows.yml: Don't install libusb or spice packages on 32-bit
When msys2 updated their libusb packages to libusb 1.0.27, they
dropped support for building them for mingw32, leaving only mingw64
packages. This broke our CI job, as the 'pacman' package install now
fails with:
error: target not found: mingw-w64-i686-libusb
error: target not found: mingw-w64-i686-usbredir
(both these binary packages are from the libusb source package).
Similarly, spice is now 64-bit only:
error: target not found: mingw-w64-i686-spice
Fix this by dropping these packages from the list we install for our
msys2-32bit build. We do this with a simple mechanism for the
msys2-64bit and msys2-32bit jobs to specify a list of extra packages
to install on top of the common ones we install for both jobs.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2160
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Message-id: 20240215155009.2422335-1-peter.maydell@linaro.org
Commit: da96ad4a6a2ef26c83b15fa95e7fceef5147269c
https://github.com/qemu/qemu/commit/da96ad4a6a2ef26c83b15fa95e7fceef5147269c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-16 (Fri, 16 Feb 2024)
Changed paths:
M MAINTAINERS
M hw/arm/highbank.c
M hw/arm/sbsa-ref.c
M hw/char/grlib_apbuart.c
M hw/dma/i82374.c
M hw/dma/i8257.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/ide/ahci-allwinner.c
M hw/ide/ahci.c
M hw/ide/ahci_internal.h
M hw/ide/ich.c
M hw/intc/grlib_irqmp.c
M hw/isa/Kconfig
A hw/isa/fdc37m81x-superio.c
M hw/isa/isa-superio.c
M hw/isa/lpc_ich9.c
M hw/isa/meson.build
M hw/isa/piix.c
M hw/isa/smc37c669-superio.c
M hw/isa/vt82c686.c
M hw/mips/Kconfig
M hw/mips/boston.c
M hw/mips/cps.c
M hw/mips/jazz.c
M hw/mips/mipssim.c
M hw/misc/macio/macio.c
M hw/misc/mips_itu.c
M hw/ppc/prep.c
M hw/rx/rx-gdbsim.c
M hw/rx/rx62n.c
M hw/sh4/r2d.c
M hw/sparc/leon3.c
M hw/sparc/sun4m.c
M hw/sparc64/sparc64.c
M hw/timer/grlib_gptimer.c
M include/hw/arm/allwinner-a10.h
M include/hw/arm/allwinner-r40.h
M include/hw/arm/xlnx-zynqmp.h
A include/hw/char/grlib_uart.h
M include/hw/dma/i8257.h
A include/hw/ide/ahci-pci.h
A include/hw/ide/ahci-sysbus.h
M include/hw/ide/ahci.h
A include/hw/intc/grlib_irqmp.h
M include/hw/misc/mips_itu.h
M include/hw/rx/rx62n.h
R include/hw/sparc/grlib.h
A include/hw/timer/grlib_gptimer.h
M target/mips/cpu.h
M target/mips/internal.h
M target/mips/sysemu/machine.c
M target/mips/tcg/sysemu/cp0_helper.c
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
M target/sparc/cpu.h
M target/sparc/helper.c
M target/sparc/helper.h
M target/sparc/translate.c
Log Message:
-----------
Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging
Misc HW patch queue
- Remove unused MIPS SAAR* registers (Phil)
- Remove warning when testing the TC58128 NAND EEPROM (Peter)
- KConfig cleanups around ISA SuperI/O and MIPS (Paolo)
- QDev API uses sanitization (Philippe)
- Split AHCI model as PCI / SysBus (Philippe)
- Add SMP support to SPARC Leon3 board (Clément)
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXOUD4ACgkQ4+MsLN6t
# wN6gWRAAjf+6Z9VUvvHqZoaSJW49k+GRUelTI2tyN+eGfetAx9dk8aIbpbV1X12d
# pc56jsSi6ICT7baCegtxHszhYJr2e9A2QLCAOJt+Oz87kEGes3ONVVKAk7pwjKxt
# m8pmU3uXWgFvU6PoFBhGBa6LiZBulgLNXBUwzmEhc9PpPkR49ULdDp/qxtWvxOV5
# xYBktFlkiT+AvHq3QWCnDIaw+pH5ghEq9BI4xFOvvvqSqdHEqsGAaiKPa9Po0Gfz
# Ap9qsm4FxKxhGoeQWtAIP8TvN3pFFSXMysziP6Xt1rffKsvF9ioghGKRM6BgQfqD
# ZetjcFbcf7dQu3zZVy8ljYcymMxfZcWWVVq4CMC68lPQE97hz1CT3PJjgd77dKfi
# z60uRkOGaiPW5iIGT9+vdQxZ5K3HivKyjuHOdV8V4HnWO3oqgfDtNHn5RKed0qUg
# g1FoWriJGsDixdx1vd0EoH2/oTxy4HIsFv7a1OjiZyBLjO+EeEZ3+H9pqUHqBxva
# +Dv70z9F1sv5dzcUXH+oCgTbnKlJ90Q+e3vj0wGdlBncVsgIwbtgqYelhUEl+xJX
# Mu6KNUo5ANVP38ZKG0GSMCZHfcUjc5s+5rG55NbTN0HiF56a6D2KlQAuXdUsGE1J
# 7i4cwipJmfxzbdPDlSb3kBxm5pFexEk6nROF9kTHQj3ZBMMvIls=
# =nOX+
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 15 Feb 2024 17:56:14 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20240215' of https://github.com/philmd/qemu: (56 commits)
hw/ide/ich9: Use AHCIPCIState typedef
hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h'
hw/ide/ahci: Remove SysbusAHCIState::num_ports field
hw/ide/ahci: Do not pass 'ports' argument to ahci_realize()
hw/ide/ahci: Convert AHCIState::ports to unsigned
hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs()
hw/ide/ahci: Inline ahci_get_num_ports()
hw/ide/ahci: Rename AHCI PCI function as 'pdev'
hw/ide/ahci: Expose AHCIPCIState structure
hw/i386/q35: Use DEVICE() cast macro with PCIDevice object
hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled
MAINTAINERS: Add myself as reviewer for TCG Plugins
MAINTAINERS: replace Fabien by myself as Leon3 maintainer
hw/sparc/leon3: Initialize GPIO before realizing CPU devices
hw/sparc/leon3: Pass DeviceState opaque argument to leon3_start_cpu()
hw/sparc/leon3: Pass DeviceState opaque argument to leon3_set_pil_in()
hw/sparc/leon3: check cpu_id in the tiny bootloader
hw/sparc/leon3: implement multiprocessor
hw/sparc/leon3: remove SP initialization
target/sparc: implement asr17 feature for smp
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/3ff11e4dcabe...da96ad4a6a2e