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[Qemu-commits] [qemu/qemu] 627598: virtio: split into vhost-user-base an
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 627598: virtio: split into vhost-user-base and vhost-user-... |
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Date: |
Wed, 14 Feb 2024 09:32:11 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 6275989647efb708f126eb4f880e593792301ed4
https://github.com/qemu/qemu/commit/6275989647efb708f126eb4f880e593792301ed4
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M MAINTAINERS
M hw/virtio/meson.build
A hw/virtio/vhost-user-base.c
M hw/virtio/vhost-user-device-pci.c
M hw/virtio/vhost-user-device.c
A include/hw/virtio/vhost-user-base.h
R include/hw/virtio/vhost-user-device.h
Log Message:
-----------
virtio: split into vhost-user-base and vhost-user-device
Lets keep a cleaner split between the base class and the derived
vhost-user-device which we can use for generic vhost-user stubs. This
includes an update to introduce the vq_size property so the number of
entries in a virtq can be defined.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-2-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 64a312a2737e3aab97f103b76f8e76a97770e670
https://github.com/qemu/qemu/commit/64a312a2737e3aab97f103b76f8e76a97770e670
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/virtio/vhost-user-base.c
Log Message:
-----------
hw/virtio: convert vhost-user-base to async shutdown
We are about to convert at least one stubs which was using the async
teardown so lets use it for all the cases.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-3-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 233412bf7a2b0349aa3b80ab7217e741c8acef3f
https://github.com/qemu/qemu/commit/233412bf7a2b0349aa3b80ab7217e741c8acef3f
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/virtio/meson.build
M hw/virtio/vhost-user-rng.c
M include/hw/virtio/vhost-user-rng.h
Log Message:
-----------
hw/virtio: derive vhost-user-rng from vhost-user-base
Now we can take advantage of our new base class and make
vhost-user-rng a much simpler boilerplate wrapper. Also as this
doesn't require any target specific hacks we only need to build the
stubs once.
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-4-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5ba587580db55bd310dc64d0eb89b4f7b19c6404
https://github.com/qemu/qemu/commit/5ba587580db55bd310dc64d0eb89b4f7b19c6404
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/virtio/meson.build
M hw/virtio/vhost-user-gpio.c
M include/hw/virtio/vhost-user-gpio.h
Log Message:
-----------
hw/virtio: derive vhost-user-gpio from vhost-user-base
Now the new base class supports config handling we can take advantage
and make vhost-user-gpio a much simpler boilerplate wrapper. Also as
this doesn't require any target specific hacks we only need to build
the stubs once.
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-5-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a50616b50d0107c3bbdf9fae5ac1f3659dfc70f3
https://github.com/qemu/qemu/commit/a50616b50d0107c3bbdf9fae5ac1f3659dfc70f3
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/virtio/meson.build
M hw/virtio/vhost-user-i2c.c
M include/hw/virtio/vhost-user-i2c.h
Log Message:
-----------
hw/virtio: derive vhost-user-i2c from vhost-user-base
Now we can take advantage of the new base class and make
vhost-user-i2c a much simpler boilerplate wrapper. Also as this
doesn't require any target specific hacks we only need to build the
stubs once.
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-6-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4ae0fc18a1dc91bfe3a494292faf3c4c1b2cc16c
https://github.com/qemu/qemu/commit/4ae0fc18a1dc91bfe3a494292faf3c4c1b2cc16c
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M MAINTAINERS
M hw/virtio/Kconfig
M hw/virtio/meson.build
A hw/virtio/vhost-user-snd-pci.c
A hw/virtio/vhost-user-snd.c
A include/hw/virtio/vhost-user-snd.h
Log Message:
-----------
hw/virtio: add vhost-user-snd and vhost-user-snd-pci devices
Tested with rust-vmm vhost-user-sound daemon:
RUST_LOG=trace cargo run --bin vhost-user-sound -- --socket /tmp/snd.sock
--backend null
Invocation:
qemu-system-x86_64 \
-qmp unix:./qmp-sock,server,wait=off \
-m 4096 \
-numa node,memdev=mem \
-object
memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on \
-D qemu.log \
-d guest_errors,trace:\*snd\*,trace:\*sound\*,trace:\*vhost\* \
-chardev socket,id=vsnd,path=/tmp/snd.sock \
-device vhost-user-snd-pci,chardev=vsnd,id=snd \
/path/to/disk
[AJB: imported from
https://github.com/epilys/qemu-virtio-snd/commit/54ae1cdd15fef2d88e9e387a175f099a38c636f4.patch]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20240104210945.1223134-7-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e7fe912276c0b5859404327b6ab9ce332a2a887b
https://github.com/qemu/qemu/commit/e7fe912276c0b5859404327b6ab9ce332a2a887b
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M docs/system/devices/vhost-user-rng.rst
M docs/system/devices/vhost-user.rst
Log Message:
-----------
docs/system: add a basic enumeration of vhost-user devices
Make it clear the vhost-user-device is intended for expert use only.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-8-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a26105dd56a11d5aec618fc5429ae7932d3221c5
https://github.com/qemu/qemu/commit/a26105dd56a11d5aec618fc5429ae7932d3221c5
Author: Leo Yan <leo.yan@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/virtio/vhost-user-base.c
Log Message:
-----------
hw/virtio: Support set_config() callback in vhost-user-base
The Virtio input device invokes set_config() callback for retrieving
the event configuration info, but the callback is not supported in
vhost-user-base.
This patch adds support set_config() callback in vhost-user-base.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20231120043721.50555-2-leo.yan@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-9-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 887d5775863b8804bacba6fe1a860ed3ea5cfdd9
https://github.com/qemu/qemu/commit/887d5775863b8804bacba6fe1a860ed3ea5cfdd9
Author: Leo Yan <leo.yan@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M MAINTAINERS
M docs/system/device-emulation.rst
A docs/system/devices/vhost-user-input.rst
M docs/system/devices/vhost-user.rst
Log Message:
-----------
docs/system: Add vhost-user-input documentation
This adds basic documentation for vhost-user-input.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Message-Id: <20231120043721.50555-3-leo.yan@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-10-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 87c7fb7819962e052a69046167949fe266611abf
https://github.com/qemu/qemu/commit/87c7fb7819962e052a69046167949fe266611abf
Author: Leo Yan <leo.yan@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M MAINTAINERS
M hw/input/meson.build
R hw/input/vhost-user-input.c
M hw/virtio/meson.build
A hw/virtio/vhost-user-input.c
Log Message:
-----------
hw/virtio: Move vhost-user-input into virtio folder
vhost-user-input is in the input folder. On the other hand, the folder
'hw/virtio' maintains other virtio stubs (e.g. I2C, RNG, GPIO, etc).
This patch moves vhost-user-input into the virtio folder for better code
organization. No functionality change.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20231120043721.50555-4-leo.yan@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-11-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: bad38726e9dc52d840d151a1ba38b5614b521feb
https://github.com/qemu/qemu/commit/bad38726e9dc52d840d151a1ba38b5614b521feb
Author: Leo Yan <leo.yan@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/virtio/vhost-user-input-pci.c
M hw/virtio/vhost-user-input.c
M include/hw/virtio/virtio-input.h
Log Message:
-----------
hw/virtio: derive vhost-user-input from vhost-user-base
This patch derives vhost-user-input from vhost-user-base class, so make
the input stub as a simpler boilerplate wrapper.
With the refactoring, vhost-user-input adds the property 'chardev', this
leads to conflict with the vhost-user-input-pci adds the same property.
To resolve the error, remove the duplicate property from
vhost-user-input-pci.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20231120043721.50555-5-leo.yan@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240104210945.1223134-12-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b2101358e591c9f0a93739dd3aee72935a79af80
https://github.com/qemu/qemu/commit/b2101358e591c9f0a93739dd3aee72935a79af80
Author: Bui Quang Minh <minhquangbui99@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/intc/apic.c
M hw/intc/trace-events
M include/hw/i386/apic.h
M target/i386/cpu.h
M target/i386/tcg/sysemu/misc_helper.c
Log Message:
-----------
i386/tcg: implement x2APIC registers MSR access
This commit creates apic_register_read/write which are used by both
apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access.
The apic_msr_read/write returns -1 on error, accelerator can use this to
raise the appropriate exception.
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-2-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b5ee0468e9d28c6bd47cce70f90b5032dd10ecc2
https://github.com/qemu/qemu/commit/b5ee0468e9d28c6bd47cce70f90b5032dd10ecc2
Author: Bui Quang Minh <minhquangbui99@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/i386/x86.c
M hw/intc/apic.c
M hw/intc/apic_common.c
M include/hw/i386/apic.h
M include/hw/i386/apic_internal.h
M target/i386/cpu-sysemu.c
M target/i386/cpu.h
Log Message:
-----------
apic: add support for x2APIC mode
This commit extends the APIC ID to 32-bit long and remove the 255 max APIC
ID limit in userspace APIC. The array that manages local APICs is now
dynamically allocated based on the max APIC ID of created x86 machine.
Also, new x2APIC IPI destination determination scheme, self IPI and x2APIC
mode register access are supported.
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-3-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 774204cf9874e58dc7fc13394a505452357750ad
https://github.com/qemu/qemu/commit/774204cf9874e58dc7fc13394a505452357750ad
Author: Bui Quang Minh <minhquangbui99@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/i386/kvm/apic.c
M hw/i386/xen/xen_apic.c
M hw/intc/apic.c
M hw/intc/apic_common.c
M include/hw/i386/apic.h
M include/hw/i386/apic_internal.h
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/whpx/whpx-apic.c
Log Message:
-----------
apic, i386/tcg: add x2apic transitions
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
The set_base in APICCommonClass now returns an integer to indicate error in
execution. apic_set_base return -1 on invalid APIC state transition,
accelerator can use this to raise appropriate exception.
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-4-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2cf16205290bdb6d92bade3590adec6e08fd26c9
https://github.com/qemu/qemu/commit/2cf16205290bdb6d92bade3590adec6e08fd26c9
Author: Bui Quang Minh <minhquangbui99@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: allow Extended Interrupt Mode when using userspace APIC
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins <joao.m.martins@oracle.com>
Acked-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-5-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 595cd6fd9dffe51ef3fdb3077979a87ff2947b1f
https://github.com/qemu/qemu/commit/595cd6fd9dffe51ef3fdb3077979a87ff2947b1f
Author: Bui Quang Minh <minhquangbui99@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
test: bios-tables-test: prepare IVRS change in ACPI table
Following the instructions in bios-tables-test, this lists that IVRS.ivrs
in ACPI table will be changed to add new IVHD type 0x11.
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-6-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 328a11a08a70ca9e565cee807eb74e1e59e1b5d9
https://github.com/qemu/qemu/commit/328a11a08a70ca9e565cee807eb74e1e59e1b5d9
Author: Bui Quang Minh <minhquangbui99@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/i386/acpi-build.c
A hw/i386/amd_iommu-stub.c
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
M hw/i386/meson.build
Log Message:
-----------
amd_iommu: report x2APIC support to the operating system
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used to support 32-bit destination id.
Additionally, this commit exports IVHD type 0x11 besides the old IVHD type
0x10 in ACPI table. IVHD type 0x10 does not report full set of IOMMU
features only the legacy ones, so operating system (e.g. Linux) may only
detects x2APIC support if IVHD type 0x11 is available. The IVHD type 0x10
is kept so that old operating system that only parses type 0x10 can detect
the IOMMU device.
Besides, an amd_iommu-stub.c file is created to provide the definition for
amdvi_extended_feature_register when CONFIG_AMD_IOMMU=n. This function is
used by acpi-build.c to get the extended feature register value for
building the ACPI table. When CONFIG_AMD_IOMMU=y, this function is defined
in amd_iommu.c.
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-7-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7618fffdf16e03377390e51c033f0b14d772333a
https://github.com/qemu/qemu/commit/7618fffdf16e03377390e51c033f0b14d772333a
Author: Bui Quang Minh <minhquangbui99@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M tests/data/acpi/q35/IVRS.ivrs
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
test: bios-tables-test: add IVRS changed binary
Following the instructions in bios-tables-test, this adds the changed
IVRS.ivrs binary.
New IVRS differs in length, checksum, it enables EFRSup in Virtualization
Info and adds IVHD type 0x11 with the same device entries as in IVHD type
0x10.
ASL diff:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20230628 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/IVRS.ivrs, Wed Nov 8 21:39:58 2023
+ * Disassembly of /tmp/aml-2ODND2, Wed Nov 8 21:39:58 2023
*
* ACPI Data Table [IVRS]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in
hex)
*/
[000h 0000 004h] Signature : "IVRS" [I/O Virtualization
Reporting Structure]
-[004h 0004 004h] Table Length : 00000068
+[004h 0004 004h] Table Length : 000000B0
[008h 0008 001h] Revision : 01
-[009h 0009 001h] Checksum : 43
+[009h 0009 001h] Checksum : 74
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
-[024h 0036 004h] Virtualization Info : 00002800
+[024h 0036 004h] Virtualization Info : 00002801
[028h 0040 008h] Reserved : 0000000000000000
[030h 0048 001h] Subtable Type : 10 [Hardware Definition Block
(IVHD)]
[031h 0049 001h] Flags (decoded below) : D1
HtTunEn : 1
PassPW : 0
ResPassPW : 0
Isoc Control : 0
Iotlb Support : 1
Coherent : 0
Prefetch Support : 1
PPR Support : 1
[032h 0050 002h] Length : 0038
[034h 0052 002h] DeviceId : 0010
[036h 0054 002h] Capability Offset : 0040
[038h 0056 008h] Base Address : 00000000FED80000
@@ -108,25 +108,129 @@
LINT1 Pass : 0
[060h 0096 001h] Subtable Type : 48 [Device Entry: Special
Device]
[061h 0097 002h] Device ID : 0000
[063h 0099 001h] Data Setting (decoded below) : 00
INITPass : 0
EIntPass : 0
NMIPass : 0
Reserved : 0
System MGMT : 0
LINT0 Pass : 0
LINT1 Pass : 0
[064h 0100 001h] Handle : 00
[065h 0101 002h] Source Used Device ID : 00A0
[067h 0103 001h] Variety : 01
-Raw Table Data: Length 104 (0x68)
+[068h 0104 001h] Subtable Type : 11 [Hardware Definition Block
(IVHD)]
+[069h 0105 001h] Flags (decoded below) : 11
+ HtTunEn : 1
+ PassPW : 0
+ ResPassPW : 0
+ Isoc Control : 0
+ Iotlb Support : 1
+ Coherent : 0
+ Prefetch Support : 0
+ PPR Support : 0
+[06Ah 0106 002h] Length : 0048
+[06Ch 0108 002h] DeviceId : 0010
+[06Eh 0110 002h] Capability Offset : 0040
+[070h 0112 008h] Base Address : 00000000FED80000
+[078h 0120 002h] PCI Segment Group : 0000
+[07Ah 0122 002h] Virtualization Info : 0000
+[07Ch 0124 004h] Attributes : 00000000
+[080h 0128 008h] EFR Image : 00000000000029D3
+[088h 0136 008h] Reserved : 0000000000000000
+
+[090h 0144 001h] Subtable Type : 02 [Device Entry: Select One
Device]
+[091h 0145 002h] Device ID : 0000
+[093h 0147 001h] Data Setting (decoded below) : 00
+ INITPass : 0
+ EIntPass : 0
+ NMIPass : 0
+ Reserved : 0
+ System MGMT : 0
+ LINT0 Pass : 0
+ LINT1 Pass : 0
+
+[094h 0148 001h] Subtable Type : 02 [Device Entry: Select One
Device]
+[095h 0149 002h] Device ID : 0008
+[097h 0151 001h] Data Setting (decoded below) : 00
+ INITPass : 0
+ EIntPass : 0
+ NMIPass : 0
+ Reserved : 0
+ System MGMT : 0
+ LINT0 Pass : 0
+ LINT1 Pass : 0
+
+[098h 0152 001h] Subtable Type : 02 [Device Entry: Select One
Device]
+[099h 0153 002h] Device ID : 0010
+[09Bh 0155 001h] Data Setting (decoded below) : 00
+ INITPass : 0
+ EIntPass : 0
+ NMIPass : 0
+ Reserved : 0
+ System MGMT : 0
+ LINT0 Pass : 0
+ LINT1 Pass : 0
+
+[09Ch 0156 001h] Subtable Type : 02 [Device Entry: Select One
Device]
+[09Dh 0157 002h] Device ID : 00F8
+[09Fh 0159 001h] Data Setting (decoded below) : 00
+ INITPass : 0
+ EIntPass : 0
+ NMIPass : 0
+ Reserved : 0
+ System MGMT : 0
+ LINT0 Pass : 0
+ LINT1 Pass : 0
+
+[0A0h 0160 001h] Subtable Type : 02 [Device Entry: Select One
Device]
+[0A1h 0161 002h] Device ID : 00FA
+[0A3h 0163 001h] Data Setting (decoded below) : 00
+ INITPass : 0
+ EIntPass : 0
+ NMIPass : 0
+ Reserved : 0
+ System MGMT : 0
+ LINT0 Pass : 0
+ LINT1 Pass : 0
+
+[0A4h 0164 001h] Subtable Type : 02 [Device Entry: Select One
Device]
+[0A5h 0165 002h] Device ID : 00FB
+[0A7h 0167 001h] Data Setting (decoded below) : 00
+ INITPass : 0
+ EIntPass : 0
+ NMIPass : 0
+ Reserved : 0
+ System MGMT : 0
+ LINT0 Pass : 0
+ LINT1 Pass : 0
+
+[0A8h 0168 001h] Subtable Type : 48 [Device Entry: Special
Device]
+[0A9h 0169 002h] Device ID : 0000
+[0ABh 0171 001h] Data Setting (decoded below) : 00
+ INITPass : 0
+ EIntPass : 0
+ NMIPass : 0
+ Reserved : 0
+ System MGMT : 0
+ LINT0 Pass : 0
+ LINT1 Pass : 0
+[0ACh 0172 001h] Handle : 00
+[0ADh 0173 002h] Source Used Device ID : 00A0
+[0AFh 0175 001h] Variety : 01
+
+Raw Table Data: Length 176 (0xB0)
- 0000: 49 56 52 53 68 00 00 00 01 43 42 4F 43 48 53 20 // IVRSh....CBOCHS
+ 0000: 49 56 52 53 B0 00 00 00 01 74 42 4F 43 48 53 20 // IVRS.....tBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 00 28 00 00 00 00 00 00 00 00 00 00 // .....(..........
+ 0020: 01 00 00 00 01 28 00 00 00 00 00 00 00 00 00 00 // .....(..........
0030: 10 D1 38 00 10 00 40 00 00 00 D8 FE 00 00 00 00 // ..8...@.........
0040: 00 00 00 00 44 00 00 00 02 00 00 00 02 08 00 00 // ....D...........
0050: 02 10 00 00 02 F8 00 00 02 FA 00 00 02 FB 00 00 // ................
- 0060: 48 00 00 00 00 A0 00 01 // H.......
+ 0060: 48 00 00 00 00 A0 00 01 11 11 48 00 10 00 40 00 // H.........H...@.
+ 0070: 00 00 D8 FE 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: D3 29 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .)..............
+ 0090: 02 00 00 00 02 08 00 00 02 10 00 00 02 F8 00 00 // ................
+ 00A0: 02 FA 00 00 02 FB 00 00 48 00 00 00 00 A0 00 01 // ........H.......
Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com>
Message-Id: <20240111154404.5333-8-minhquangbui99@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f22f3a92eb728497dcd0f43e31b9148992db99bd
https://github.com/qemu/qemu/commit/f22f3a92eb728497dcd0f43e31b9148992db99bd
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/i386/x86.c
Log Message:
-----------
hw/i386/x86: Reverse if statement
The if statement currently uses double negation when executing the else branch.
So swap the branches and simplify the condition to make the code more
comprehensible.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240106132546.21248-2-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c2e6d7d8e7fc270a90c61944ef36574b1549ddcf
https://github.com/qemu/qemu/commit/c2e6d7d8e7fc270a90c61944ef36574b1549ddcf
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/i386/x86.c
M hw/intc/apic_common.c
M include/hw/i386/apic.h
Log Message:
-----------
hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled
QEMU populates the apic_state attribute of x86 CPUs if supported by real
hardware or if SMP is active. When handling interrupts, it just checks whether
apic_state is populated to route the interrupt to the PIC or to the APIC.
However, chapter 10.4.3 of [1] requires that:
When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an
IA-32 processor without an on-chip APIC.
This means that when apic_state is populated, QEMU needs to check for the
MSR_IA32_APICBASE_ENABLE flag in addition. Implement this which fixes some
real-world BIOSes.
[1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A:
System Programming Guide, Part 1
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240106132546.21248-3-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f70c1c068dbe5bb17f34c8b9c2195cd7f707f07e
https://github.com/qemu/qemu/commit/f70c1c068dbe5bb17f34c8b9c2195cd7f707f07e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386/cpu: Fix typo in comment
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240106132546.21248-4-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 271c5bb3780773008a936f424cccf181a11b592c
https://github.com/qemu/qemu/commit/271c5bb3780773008a936f424cccf181a11b592c
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/block/fdc-internal.h
M hw/block/fdc-isa.c
Log Message:
-----------
hw/block/fdc-isa: Move portio_list from FDCtrl to FDCtrlISABus
FDCtrl::portio_list isn't used inside FDCtrl context but only inside
FDCtrlISABus context, so move it there.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20240114123911.4877-2-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ff453ce2819434d08fcaadca5d71b6e9a951ebdd
https://github.com/qemu/qemu/commit/ff453ce2819434d08fcaadca5d71b6e9a951ebdd
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/block/fdc-internal.h
M hw/block/fdc-sysbus.c
Log Message:
-----------
hw/block/fdc-sysbus: Move iomem from FDCtrl to FDCtrlSysBus
FDCtrl::iomem isn't used inside FDCtrl context but only inside FDCtrlSysBus
context, so move it there.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20240114123911.4877-3-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ee3d1f1b46e0c304ee4065b3099734158f322860
https://github.com/qemu/qemu/commit/ee3d1f1b46e0c304ee4065b3099734158f322860
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/char/parallel.c
M include/hw/char/parallel-isa.h
M include/hw/char/parallel.h
Log Message:
-----------
hw/char/parallel: Move portio_list from ParallelState to ISAParallelState
ParallelState::portio_list isn't used inside ParallelState context but only
inside ISAParallelState context, so move it there.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20240114123911.4877-4-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4edee342f81397e8938ba7a80d1908c5103b66c8
https://github.com/qemu/qemu/commit/4edee342f81397e8938ba7a80d1908c5103b66c8
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M include/exec/ioport.h
M system/ioport.c
Log Message:
-----------
exec/ioport: Resolve redundant .base attribute in struct MemoryRegionPortio
portio_list_add_1() creates a MemoryRegionPortioList instance which holds a
MemoryRegion `mr` and an array of MemoryRegionPortio elements named `ports`.
Each element in the array gets assigned the same value for its .base attribute.
The same value also ends up as the .addr attribute of `mr` due to the
memory_region_add_subregion() call. This means that all .base attributes are
the same as `mr.addr`.
The only usages of MemoryRegionPortio::base were in portio_read() and
portio_write(). Both functions get above MemoryRegionPortioList as their
opaque parameter. In both cases find_portio() can only return one of the
MemoryRegionPortio elements of the `ports` array. Due to above observation any
element will have the same .base value equal to `mr.addr` which is also
accessible.
Hence, `mrpio->mr.addr` is equivalent to `mrp->base` and
MemoryRegionPortio::base is redundant and can be removed.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240114123911.4877-5-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ad2b652341f4257e2fb7ebf3834724f91173a07a
https://github.com/qemu/qemu/commit/ad2b652341f4257e2fb7ebf3834724f91173a07a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M docs/devel/migration/main.rst
M include/exec/ioport.h
M system/ioport.c
Log Message:
-----------
exec/ioport: Add portio_list_set_address()
Some SuperI/O devices such as the VIA south bridges or the PC87312 controller
are able to relocate their SuperI/O functions. Add a convenience function for
implementing this in the VIA south bridges.
This convenience function relies on previous simplifications in exec/ioport
which avoids some duplicate synchronization of I/O port base addresses. The
naming of the function is inspired by its memory_region_set_address() pendant.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240114123911.4877-6-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f165cdf102bb93c255c63b77617ba371d73344e0
https://github.com/qemu/qemu/commit/f165cdf102bb93c255c63b77617ba371d73344e0
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M docs/devel/migration/main.rst
M include/exec/ioport.h
M system/ioport.c
Log Message:
-----------
exec/ioport: Add portio_list_set_enabled()
Some SuperI/O devices such as the VIA south bridges or the PC87312 controller
allow to enable or disable their SuperI/O functions. Add a convenience function
for implementing this in the VIA south bridges.
The naming of the functions is inspired by its memory_region_set_enabled()
pendant.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240114123911.4877-7-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8c4d239139e93268884f9d385a0966ef40db422f
https://github.com/qemu/qemu/commit/8c4d239139e93268884f9d385a0966ef40db422f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/block/fdc-isa.c
M include/hw/block/fdc.h
Log Message:
-----------
hw/block/fdc-isa: Implement relocation and enabling/disabling for TYPE_ISA_FDC
The real SuperI/O chips emulated by QEMU allow for relocating and enabling or
disabling their SuperI/O functions via software. So far this is not implemented.
Prepare for that by adding isa_fdc_set_{enabled,iobase}.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240114123911.4877-8-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7812dbc54c72f71df2644d0cec52a1e8d6b19584
https://github.com/qemu/qemu/commit/7812dbc54c72f71df2644d0cec52a1e8d6b19584
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/char/serial-isa.c
M include/hw/char/serial.h
Log Message:
-----------
hw/char/serial-isa: Implement relocation and enabling/disabling for
TYPE_ISA_SERIAL
The real SuperI/O chips emulated by QEMU allow for relocating and enabling or
disabling their SuperI/O functions via software. So far this is not implemented.
Prepare for that by adding isa_serial_set_{enabled,iobase}.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240114123911.4877-9-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1d1afd9ff7264c7ed35f3ca25cc4bf9dd82a6b06
https://github.com/qemu/qemu/commit/1d1afd9ff7264c7ed35f3ca25cc4bf9dd82a6b06
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/char/parallel-isa.c
M include/hw/char/parallel-isa.h
Log Message:
-----------
hw/char/parallel-isa: Implement relocation and enabling/disabling for
TYPE_ISA_PARALLEL
The real SuperI/O chips emulated by QEMU allow for relocating and enabling or
disabling their SuperI/O functions via software. So far this is not implemented.
Prepare for that by adding isa_parallel_set_{enabled,iobase}.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240114123911.4877-10-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 79a7f53065abea95b33e2212dcfb58e1de4be479
https://github.com/qemu/qemu/commit/79a7f53065abea95b33e2212dcfb58e1de4be479
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Let pegasos2 machine configure SuperI/O functions
This is a preparation for implementing relocation and toggling of SuperI/O
functions in the VT8231 device model. Upon reset, all SuperI/O functions will be
deactivated, so in case if no -bios is given, let the machine configure those
functions the same way Pegasos II firmware would do.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20240114123911.4877-11-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 35a6380b4ed27f8355330b1fb0918b20c728d30e
https://github.com/qemu/qemu/commit/35a6380b4ed27f8355330b1fb0918b20c728d30e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Implement relocation and toggling of SuperI/O functions
The VIA south bridges are able to relocate and toggle (enable or disable) their
SuperI/O functions. So far this is hardcoded such that all functions are always
enabled and are located at fixed addresses.
Some PC BIOSes seem to probe for I/O occupancy before activating such a function
and issue an error in case of a conflict. Since the functions are currently
enabled on reset, conflicts are always detected. Prevent that by implementing
relocation and toggling of the SuperI/O functions.
Note that all SuperI/O functions are now deactivated upon reset (except for
VT82C686B's serial ports where Fuloong 2e's rescue-yl seems to expect them to be
enabled by default). Rely on firmware to configure the functions accordingly.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20240114123911.4877-12-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aa05bd9ef4073ccb72d04ad78de32916af31c7c3
https://github.com/qemu/qemu/commit/aa05bd9ef4073ccb72d04ad78de32916af31c7c3
Author: Andrey Ignatov <rdna@apple.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user.rst: Fix vring address description
There is no "size" field in vring address structure. Remove it.
Fixes: 5fc0e00291 ("Add vhost-user protocol documentation")
Signed-off-by: Andrey Ignatov <rdna@apple.com>
Message-Id: <20240112004555.64900-1-rdna@apple.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e8058c6d65252d920abf0bee027c455e8ffe41ff
https://github.com/qemu/qemu/commit/e8058c6d65252d920abf0bee027c455e8ffe41ff
Author: Peter Xu <peterx@redhat.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Drop myself as VT-d maintainers
Due to my own limitation on bandwidth, I noticed that unfortunately I won't
have time to review VT-d patches at least in the near future. Meanwhile I
expect a lot of possibilities could actually happen in this area in the
near future.
To reflect that reality, I decided to drop myself from the VT-d role. It
shouldn't affect much since we still have Jason around like usual, and
Michael on top. But I assume it'll always be good if anyone would like to
fill this role up.
I'll still work on QEMU. So I suppose anyone can still copy me if one
thinks essential.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Jason Wang <jasowang@redhat.com>
Signed-off-by: Peter Xu <peterx@redhat.com>
Message-Id: <20240118091035.48178-1-peterx@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Jason Wang <jasowang@redhat.com>
Commit: 9a457383ce9d309d4679b079fafb51f0a2d949aa
https://github.com/qemu/qemu/commit/9a457383ce9d309d4679b079fafb51f0a2d949aa
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/virtio/virtio-iommu.c
Log Message:
-----------
virtio_iommu: Clear IOMMUPciBus pointer cache when system reset
s->iommu_pcibus_by_bus_num is a IOMMUPciBus pointer cache indexed
by bus number, bus number may not always be a fixed value,
i.e., guest reboot to different kernel which set bus number with
different algorithm.
This could lead to endpoint binding to wrong iommu MR in
virtio_iommu_get_endpoint(), then vfio device setup wrong
mapping from other device.
Remove the memset in virtio_iommu_device_realize() to avoid
redundancy with memset in system reset.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Message-Id: <20240125073706.339369-2-zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8a6b3f4dc95a064e88adaca86374108da0ecb38d
https://github.com/qemu/qemu/commit/8a6b3f4dc95a064e88adaca86374108da0ecb38d
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/arm/smmu-common.c
Log Message:
-----------
smmu: Clear SMMUPciBus pointer cache when system reset
s->smmu_pcibus_by_bus_num is a SMMUPciBus pointer cache indexed
by bus number, bus number may not always be a fixed value,
i.e., guest reboot to different kernel which set bus number with
different algorithm.
This could lead to smmu_iommu_mr() providing the wrong iommu MR.
Suggested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Message-Id: <20240125073706.339369-3-zhenzhong.duan@intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c62926f730d08450502d36548e28dd727c998ace
https://github.com/qemu/qemu/commit/c62926f730d08450502d36548e28dd727c998ace
Author: Ira Weiny <ira.weiny@intel.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-cdat.c
Log Message:
-----------
cxl/cdat: Handle cdat table build errors
The callback for building CDAT tables may return negative error codes.
This was previously unhandled and will result in potentially huge
allocations later on in ct3_build_cdat()
Detect the negative error code and defer cdat building.
Fixes: f5ee7413d592 ("hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange")
Cc: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0dbcc0ce2f7b7a98a11224add69b2f2f2b8125da
https://github.com/qemu/qemu/commit/0dbcc0ce2f7b7a98a11224add69b2f2f2b8125da
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/mem/cxl_type3: Drop handling of failure of g_malloc0() and g_malloc()
As g_malloc0/g_malloc() will just exit QEMU on failure there is no
point in checking for it failing.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 99747b71baf278068b5938ccdc66d6c906ed437e
https://github.com/qemu/qemu/commit/99747b71baf278068b5938ccdc66d6c906ed437e
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/pci-bridge/cxl_upstream.c
Log Message:
-----------
hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handling
As a failure of g_malloc() will result in QEMU exiting, it
won't return a NULL to check. As such, drop the incorrect handling
of such NULL returns in the cdat table building code.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 64fdad5e67587e88c2f1d8f294e89403856a4a31
https://github.com/qemu/qemu/commit/64fdad5e67587e88c2f1d8f294e89403856a4a31
Author: Ira Weiny <ira.weiny@intel.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-cdat.c
Log Message:
-----------
cxl/cdat: Fix header sum value in CDAT checksum
The addition of the DCD support for CXL type-3 devices extended the CDAT
table large enough that the checksum being returned was incorrect.[1]
This was because the checksum value was using the header length field
rather than each of the 4 bytes of the length field. This was
previously not seen because the length of the CDAT data was less than
256 thus resulting in an equivalent checksum value.
Properly calculate the checksum for the CDAT header.
[1]
https://lore.kernel.org/all/20231116-fix-cdat-devm-free-v1-1-b148b40707d7@intel.com/
Fixes: aba578bdace5 ("hw/cxl/cdat: CXL CDAT Data Object Exchange
implementation")
Cc: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7031ee540b7e25a8f38d7b855ed99c7c5f68200d
https://github.com/qemu/qemu/commit/7031ee540b7e25a8f38d7b855ed99c7c5f68200d
Author: Davidlohr Bueso <dave@stgolabs.net>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/mbox: Remove dead code
Two functions were reported to have dead code, remove the bogus
branches altogether, as well as a misplaced qemu_log call.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f7509f462c788a347521f90f19d623908c4fbcc5
https://github.com/qemu/qemu/commit/f7509f462c788a347521f90f19d623908c4fbcc5
Author: Hyeonggon Yoo <42.hyeyoo@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-device-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: read from register values in mdev_reg_read()
In the current mdev_reg_read() implementation, it consistently returns
that the Media Status is Ready (01b). This was fine until commit
25a52959f99d ("hw/cxl: Add support for device sanitation") because the
media was presumed to be ready.
However, as per the CXL 3.0 spec "8.2.9.8.5.1 Sanitize (Opcode 4400h)",
during sanitation, the Media State should be set to Disabled (11b). The
mentioned commit correctly sets it to Disabled, but mdev_reg_read()
still returns Media Status as Ready.
To address this, update mdev_reg_read() to read register values instead
of returning dummy values.
Note that __toggle_media() managed to not only write something
that no one read, it did it to the wrong register storage and
so changed the reported mailbox size which was definitely not
the intent. That gets fixed as a side effect of allocating
separate state storage for this register.
Fixes: commit 25a52959f99d ("hw/cxl: Add support for device sanitation")
Signed-off-by: Hyeonggon Yoo <42.hyeyoo@gmail.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 729d45a6af06753d3e330f589c248fe9687c5cd5
https://github.com/qemu/qemu/commit/729d45a6af06753d3e330f589c248fe9687c5cd5
Author: Li Zhijian <lizhijian@fujitsu.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-component-utils.c
Log Message:
-----------
hw/cxl: Pass CXLComponentState to cache_mem_ops
cache_mem_ops.{read,write}() interprets opaque as
CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs).
Fortunately, cregs is the first member of cxl_cstate, so their values are
the same.
Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)")
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f8b02dd655cc20ca7f321c42acbffb143eb8372a
https://github.com/qemu/qemu/commit/f8b02dd655cc20ca7f321c42acbffb143eb8372a
Author: Li Zhijian <lizhijian@fujitsu.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-component-utils.c
Log Message:
-----------
hw/cxl: Pass NULL for a NULL MemoryRegionOps
a NULL parameter is enough for a NULL MemoryRegionOps
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 48461825af1bdc68cfa25fa0b698c958b65f7368
https://github.com/qemu/qemu/commit/48461825af1bdc68cfa25fa0b698c958b65f7368
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/mem/cxl_type3: Fix potential divide by zero reported by coverity
Fixes Coverity ID 1522368.
Currently error_fatal is set if interleave_ways_dec() is going to return 0
but we should handle that zero return explicitly.
Reported-by: Stefan Hajnoczi <stefanha@gmail.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 14ec4ff3e4293635240ba5a7afe7a0f3ba447d31
https://github.com/qemu/qemu/commit/14ec4ff3e4293635240ba5a7afe7a0f3ba447d31
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Allow update of DSDT.cxl
The _STA value returned currently indicates the ACPI0017 device
is not enabled. Whilst this isn't a real device, setting _STA
like this may prevent an OS from enumerating it correctly and
hence from parsing the CEDT table.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-11-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d9ae5802f656f6fb53b788747ba557a826b6e740
https://github.com/qemu/qemu/commit/d9ae5802f656f6fb53b788747ba557a826b6e740
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386: Fix _STA return value for ACPI0017
Found whilst testing a series for the linux kernel that actually
bothers to check if enabled is set. 0xB is the option used
for vast majority of DSDT entries in QEMU.
It is a little odd for a device that doesn't really exist and
is simply a hook to tell the OS there is a CEDT table but 0xB
seems a reasonable choice and avoids need to special case
this device in the OS.
Means:
* Device present.
* Device enabled and decoding it's resources.
* Not shown in UI
* Functioning properly
* No battery (on this device!)
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-12-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b24a981b9f1c4767aaea815e504a2c7aeb405d72
https://github.com/qemu/qemu/commit/b24a981b9f1c4767aaea815e504a2c7aeb405d72
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Update DSDT.cxl to reflect change _STA return value.
_STA will now return 0xB (in common with most other devices)
rather than not setting the bits to indicate this fake device
has not been enabled, and self tests haven't passed.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-13-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ae243dbfc45eb6d91b34d0ecb73b104a9ee0d058
https://github.com/qemu/qemu/commit/ae243dbfc45eb6d91b34d0ecb73b104a9ee0d058
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-component-utils.c
M include/hw/cxl/cxl_component.h
Log Message:
-----------
hw/cxl: Update HDM Decoder capability to version 3
Part of standardizing the QEMU code on CXL r3.1.
No fuctional changes as everything added is optional and
it is set as not implemented.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 40ecac10c03aa74deada32a1ee7af1ad9750d483
https://github.com/qemu/qemu/commit/40ecac10c03aa74deada32a1ee7af1ad9750d483
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M include/hw/cxl/cxl_component.h
Log Message:
-----------
hw/cxl: Update link register definitions.
Not actually implemented, but we need to reserve more space for
the larger version of the structure in CXL r3.1.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a185ff05fed2aa445f81d16a472e809d2cbea91b
https://github.com/qemu/qemu/commit/a185ff05fed2aa445f81d16a472e809d2cbea91b
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-component-utils.c
M include/hw/cxl/cxl_component.h
Log Message:
-----------
hw/cxl: Update RAS Capability Definitions for version 3.
Part of bringing all of CXL emulation inline with CXL r3.1.
No functional changes.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 202f651469b7a6440577cb6a985cf1eb538ea899
https://github.com/qemu/qemu/commit/202f651469b7a6440577cb6a985cf1eb538ea899
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/cxl/cxl-device-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl: Update mailbox status registers.
Whilst the reported version was 1 so there should be no changes,
a couple of fields (where the value 0 was valid) were not
defined. Make those explicit and update references to be based
on CXL r3.1.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8700ee15de465a55e5c7281f87618ca4b4827441
https://github.com/qemu/qemu/commit/8700ee15de465a55e5c7281f87618ca4b4827441
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M docs/system/devices/cxl.rst
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-events.c
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M include/hw/cxl/cxl_cdat.h
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
M include/hw/cxl/cxl_pci.h
Log Message:
-----------
hw/cxl: Standardize all references on CXL r3.1 and minor updates
Previously not all references mentioned any spec version at all.
Given r3.1 is the current specification available for evaluation at
www.computeexpresslink.org update references to refer to that.
Hopefully this won't become a never ending job.
A few structure definitions have been updated to add new fields.
Defaults of 0 and read only are valid choices for these new DVSEC
registers so go with that for now.
There are additional error codes and some of the 'questions' in
the comments are resolved now.
Update documentation reference to point to the CXL r3.1 specification
with naming closer to what is on the cover.
For cases where there are structure version numbers, add defines
so they can be found next to the register definitions.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 574b64aa6754ba491f51024c5a823a674d48a658
https://github.com/qemu/qemu/commit/574b64aa6754ba491f51024c5a823a674d48a658
Author: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M contrib/vhost-user-gpu/virgl.c
M hw/display/virtio-gpu-virgl.c
Log Message:
-----------
virtio-gpu: Correct virgl_renderer_resource_get_info() error check
virgl_renderer_resource_get_info() returns errno and not -1 on error.
Correct the return-value check.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Message-Id: <20240129073921.446869-1-dmitry.osipenko@collabora.com>
Cc: qemu-stable@nongnu.org
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e8ddec58053e9361b2cc18ec6d17b6c95590bf3c
https://github.com/qemu/qemu/commit/e8ddec58053e9361b2cc18ec6d17b6c95590bf3c
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/smbios/smbios.c
Log Message:
-----------
hw/smbios: Fix OEM strings table option validation
qemu_smbios_type11_opts did not have the list terminator and that
resulted in out-of-bound memory access. It also needs to have an element
for the type option.
Cc: qemu-stable@nongnu.org
Fixes: 2d6dcbf93fb0 ("smbios: support setting OEM strings table")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20240129-smbios-v2-1-9ee6fede0d10@daynix.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 33b081e2947db6117b27f8c76544a756053f5514
https://github.com/qemu/qemu/commit/33b081e2947db6117b27f8c76544a756053f5514
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/smbios/smbios.c
Log Message:
-----------
hw/smbios: Fix port connector option validation
qemu_smbios_type8_opts did not have the list terminator and that
resulted in out-of-bound memory access. It also needs to have an element
for the type option.
Cc: qemu-stable@nongnu.org
Fixes: fd8caa253c56 ("hw/smbios: support for type 8 (port connector)")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20240129-smbios-v2-2-9ee6fede0d10@daynix.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8b162082cb2d495f8661b7ee3239a36936dab2ee
https://github.com/qemu/qemu/commit/8b162082cb2d495f8661b7ee3239a36936dab2ee
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/display/virtio-gpu.c
Log Message:
-----------
hw/display/virtio-gpu.c: use reset_bh class method
While the VirtioGPU type has a reset_bh field to specify a reset
callback, it's never used. virtio_gpu_reset() calls the general
virtio_gpu_reset_bh() function for all devices that inherit from
VirtioGPU.
While no devices override reset_bh at the moment, a device reset might
require special logic for implementations in the future.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id:
<87fb4fa72ce5b341a6f957513a00dcb79fd5997f.1706626470.git.manos.pitsidianakis@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 330399bd8935c9c2100c40e168781f405545d05a
https://github.com/qemu/qemu/commit/330399bd8935c9c2100c40e168781f405545d05a
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/display/virtio-gpu.c
M include/hw/virtio/virtio-gpu.h
Log Message:
-----------
virtio-gpu.c: add resource_destroy class method
When destroying/unrefing resources, devices such as virtio-gpu-rutabaga
need to do their own bookkeeping (free rutabaga resources that are
associated with the virtio_gpu_simple_resource).
This commit adds a class method so that virtio-gpu-rutabaga can override
it in the next commit.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id:
<b0a86630c4d601f3a269fd7e08cfefc13bd4e219.1706626470.git.manos.pitsidianakis@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 588a09dace4f9f9163bfdd6426ed3718d166b992
https://github.com/qemu/qemu/commit/588a09dace4f9f9163bfdd6426ed3718d166b992
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M hw/display/virtio-gpu-rutabaga.c
Log Message:
-----------
virtio-gpu-rutabaga.c: override resource_destroy method
When the Rutabaga GPU device frees resources, it calls
rutabaga_resource_unref for that resource_id. However, when the generic
VirtIOGPU functions destroys resources, it only removes the
virtio_gpu_simple_resource from the device's VirtIOGPU->reslist list.
The rutabaga resource associated with that resource_id is then leaked.
This commit overrides the resource_destroy class method introduced in
the previous commit to fix this.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id:
<e3778e44c98a35839de2f4938e5355449fa3aa14.1706626470.git.manos.pitsidianakis@linaro.org>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1dd6954c3f5c5c610cf94b6f740118e565957293
https://github.com/qemu/qemu/commit/1dd6954c3f5c5c610cf94b6f740118e565957293
Author: Raphael Norwitz <raphael.s.norwitz@gmail.com>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Switch to my Enfabrica email
I'd prefer to use my new work email so this change updates MAINTAINERS
with it.
Signed-off-by: Raphael Norwitz <raphael.s.norwitz@gmail.com>
Message-Id: <20240204023758.83191-1-raphael.s.norwitz@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5767815218efd3cbfd409505ed824d5f356044ae
https://github.com/qemu/qemu/commit/5767815218efd3cbfd409505ed824d5f356044ae
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-14 (Wed, 14 Feb 2024)
Changed paths:
M MAINTAINERS
M contrib/vhost-user-gpu/virgl.c
M docs/devel/migration/main.rst
M docs/interop/vhost-user.rst
M docs/system/device-emulation.rst
M docs/system/devices/cxl.rst
A docs/system/devices/vhost-user-input.rst
M docs/system/devices/vhost-user-rng.rst
M docs/system/devices/vhost-user.rst
M hw/arm/smmu-common.c
M hw/block/fdc-internal.h
M hw/block/fdc-isa.c
M hw/block/fdc-sysbus.c
M hw/char/parallel-isa.c
M hw/char/parallel.c
M hw/char/serial-isa.c
M hw/cxl/cxl-cdat.c
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-events.c
M hw/cxl/cxl-mailbox-utils.c
M hw/display/virtio-gpu-rutabaga.c
M hw/display/virtio-gpu-virgl.c
M hw/display/virtio-gpu.c
M hw/i386/acpi-build.c
A hw/i386/amd_iommu-stub.c
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
M hw/i386/intel_iommu.c
M hw/i386/kvm/apic.c
M hw/i386/meson.build
M hw/i386/x86.c
M hw/i386/xen/xen_apic.c
M hw/input/meson.build
R hw/input/vhost-user-input.c
M hw/intc/apic.c
M hw/intc/apic_common.c
M hw/intc/trace-events
M hw/isa/vt82c686.c
M hw/mem/cxl_type3.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M hw/ppc/pegasos2.c
M hw/virtio/Kconfig
M hw/virtio/meson.build
A hw/virtio/vhost-user-base.c
M hw/virtio/vhost-user-device-pci.c
M hw/virtio/vhost-user-device.c
M hw/virtio/vhost-user-gpio.c
M hw/virtio/vhost-user-i2c.c
M hw/virtio/vhost-user-input-pci.c
A hw/virtio/vhost-user-input.c
M hw/virtio/vhost-user-rng.c
A hw/virtio/vhost-user-snd-pci.c
A hw/virtio/vhost-user-snd.c
M hw/virtio/virtio-iommu.c
M include/exec/ioport.h
M include/hw/block/fdc.h
M include/hw/char/parallel-isa.h
M include/hw/char/parallel.h
M include/hw/char/serial.h
M include/hw/cxl/cxl_cdat.h
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
M include/hw/cxl/cxl_pci.h
M include/hw/i386/apic.h
M include/hw/i386/apic_internal.h
A include/hw/virtio/vhost-user-base.h
R include/hw/virtio/vhost-user-device.h
M include/hw/virtio/vhost-user-gpio.h
M include/hw/virtio/vhost-user-i2c.h
M include/hw/virtio/vhost-user-rng.h
A include/hw/virtio/vhost-user-snd.h
M include/hw/virtio/virtio-gpu.h
M include/hw/virtio/virtio-input.h
M system/ioport.c
M target/i386/cpu-sysemu.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/whpx/whpx-apic.c
M tests/data/acpi/q35/DSDT.cxl
M tests/data/acpi/q35/IVRS.ivrs
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: features, cleanups, fixes
vhost-user-snd support
x2APIC mode with TCG support
CXL update to r3.1
fixes, cleanups all over the place.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (60
commits)
MAINTAINERS: Switch to my Enfabrica email
virtio-gpu-rutabaga.c: override resource_destroy method
virtio-gpu.c: add resource_destroy class method
hw/display/virtio-gpu.c: use reset_bh class method
hw/smbios: Fix port connector option validation
hw/smbios: Fix OEM strings table option validation
virtio-gpu: Correct virgl_renderer_resource_get_info() error check
hw/cxl: Standardize all references on CXL r3.1 and minor updates
hw/cxl: Update mailbox status registers.
hw/cxl: Update RAS Capability Definitions for version 3.
hw/cxl: Update link register definitions.
hw/cxl: Update HDM Decoder capability to version 3
tests/acpi: Update DSDT.cxl to reflect change _STA return value.
hw/i386: Fix _STA return value for ACPI0017
tests/acpi: Allow update of DSDT.cxl
hw/mem/cxl_type3: Fix potential divide by zero reported by coverity
hw/cxl: Pass NULL for a NULL MemoryRegionOps
hw/cxl: Pass CXLComponentState to cache_mem_ops
hw/cxl/device: read from register values in mdev_reg_read()
hw/cxl/mbox: Remove dead code
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/708322660e15...5767815218ef