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[Qemu-commits] [qemu/qemu] 878502: target/riscv: Check for 'A' extension
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 878502: target/riscv: Check for 'A' extension on all atomi... |
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Date: |
Mon, 12 Feb 2024 06:13:15 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 878502e5fe58b7061a631275c1db9fa4f1442479
https://github.com/qemu/qemu/commit/878502e5fe58b7061a631275c1db9fa4f1442479
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
Log Message:
-----------
target/riscv: Check for 'A' extension on all atomic instructions
Add requirement that 'A' is enabled for all atomic instructions that
lack the check. This makes the 64-bit versions consistent with the
32-bit versions in the same file.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240110163959.31291-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2317ba9fa7f39402fec17847afe11b99e361d9a0
https://github.com/qemu/qemu/commit/2317ba9fa7f39402fec17847afe11b99e361d9a0
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add infrastructure for 'B' MISA extension
Add the infrastructure for the 'B' extension which is the union of the
Zba, Zbb and Zbs instructions.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240111161644.33630-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 45982b2897ed51645fa9f054b2d2af8881dc96fb
https://github.com/qemu/qemu/commit/45982b2897ed51645fa9f054b2d2af8881dc96fb
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add step to validate 'B' extension
If the B extension is enabled warn if the user has disabled any of the
required extensions that are part of the 'B' extension. Conversely
enable the extensions that make up the 'B' extension if it is enabled.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240111161644.33630-3-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 237a2f8bcf598094f89f1c0526581d9057b392d2
https://github.com/qemu/qemu/commit/237a2f8bcf598094f89f1c0526581d9057b392d2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv/cpu_cfg.h: remove unused fields
user_spec, bext_spec and bext_ver aren't being used.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b62b86a106382c64866ba8e93170a545037027ba
https://github.com/qemu/qemu/commit/b62b86a106382c64866ba8e93170a545037027ba
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: make riscv_cpu_is_vendor() public
We'll use this function in target/riscv/cpu.c to implement setters that
won't allow vendor CPU options to be changed.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d167a2247edefc640e95497321e571721cd7952e
https://github.com/qemu/qemu/commit/d167a2247edefc640e95497321e571721cd7952e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]
Every property in riscv_cpu_options[] will be migrated to
riscv_cpu_properties[]. This will make their default values init
earlier, allowing cpu_init() functions to overwrite them. We'll also
implement common getters and setters that both accelerators will use,
allowing them to share validations that TCG is doing.
At the same time, some options (namely 'vlen', 'elen' and the cache
blocksizes) need a way of tracking if the user set a value for them.
This is benign for TCG since the cost of always validating these values
are small, but for KVM we need syscalls to read the host values to make
the validations, thus knowing whether the user didn't touch the values
makes a difference.
We'll track user setting for these properties using a hash, like we do
in the TCG driver. All riscv cpu options will update this hash in case
the user sets it. The KVM driver will use this hash to minimize the
amount of syscalls done.
For now, both 'pmu-mask' and 'pmu-num' shouldn't be changed for vendor
CPUs. The existing setter for 'pmu-num' is changed to add this
restriction. New getters and setters are required for 'pmu-mask'
While we're at it, add a 'static' modifier to 'prop_pmu_num' since we're
not exporting it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d06f28db60c536b9d7f159adedca397979f6e5ca
https://github.com/qemu/qemu/commit/d06f28db60c536b9d7f159adedca397979f6e5ca
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: move 'mmu' to riscv_cpu_properties[]
Commit 7f0bdfb5bfc ("target/riscv/cpu.c: remove cfg setup from
riscv_cpu_init()") already did some of the work by making some
cpu_init() functions to explictly enable their own 'mmu' default.
The generic CPUs didn't get update by that commit, so they are still
relying on the defaults set by the 'mmu' option. But having 'mmu' and
'pmp' being default=true will force CPUs that doesn't implement these
options to set them to 'false' in their cpu_init(), which isn't ideal.
We'll move 'mmu' to riscv_cpu_properties[] without any defaults, i.e.
the default will be 'false'. Compensate it by manually setting 'mmu =
true' to the generic CPUs that requires it.
Implement a setter for it to forbid the 'mmu' setting to be changed for
vendor CPUs. This will allow the option to exist for all CPUs and, at
the same time, protect vendor CPUs from undesired changes:
$ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,mmu=true
qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.mmu=true:
CPU 'sifive-e51' does not allow changing the value of 'mmu'
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 11097be4a571f80b387ab12381fd308eec13dfe7
https://github.com/qemu/qemu/commit/11097be4a571f80b387ab12381fd308eec13dfe7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: move 'pmp' to riscv_cpu_properties[]
Move 'pmp' to riscv_cpu_properties[], creating a new setter() for it
that forbids 'pmp' to be changed in vendor CPUs, like we did with the
'mmu' option.
We'll also have to manually set 'pmp = true' to generic CPUs that were
still relying on the previous default to set it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fefc294baa008d12a49460111227c4deef7e4d2d
https://github.com/qemu/qemu/commit/fefc294baa008d12a49460111227c4deef7e4d2d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: rework 'priv_spec'
'priv_spec' and 'vext_spec' are two string options used as a fancy way
of setting integers in the CPU state (cpu->env.priv_ver and
cpu->env.vext_ver). It requires us to deal with string parsing and to
store them in cpu_cfg.
We must support these string options, but we don't need to store them.
We have a precedence for this kind of arrangement in target/ppc/compat.c,
ppc_compat_prop_get|set, getters and setters used for the
'max-cpu-compat' class property of the pseries ppc64 machine. We'll do
the same with both 'priv_spec' and 'vext_spec'.
For 'priv_spec', the validation from riscv_cpu_validate_priv_spec() will
be done by the prop_priv_spec_set() setter, while also preventing it to
be changed for vendor CPUs. Add two helpers that converts env->priv_ver
back and forth to its string representation. These helpers allow us to
get a string and set 'env->priv_ver' and return a string giving the
current env->priv_ver value. In other words, make the cpu->cfg.priv_spec
string obsolete.
Last but not the least, move the reworked 'priv_spec' option to
riscv_cpu_properties[].
After all said and done, we don't need to store the 'priv_spec' string in
the CPU state, and we're now protecting vendor CPUs from priv_ver
changes:
$ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,priv_spec="v1.12.0"
qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.priv_spec=v1.12.0:
CPU 'sifive-e51' does not allow changing the value of 'priv_spec'
Current 'priv_spec' val: v1.10.0
$
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 41f2b94ee067b00993b0dd6c7ad3c681b093a30a
https://github.com/qemu/qemu/commit/41f2b94ee067b00993b0dd6c7ad3c681b093a30a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: rework 'vext_spec'
The same rework did in 'priv_spec' is done for 'vext_spec'. This time is
simpler, since we only accept one value ("v1.0") and we'll always have
env->vext_ver set to VEXT_VERSION_1_00_0, thus we don't need helpers to
convert string to 'vext_ver' back and forth like we needed for
'priv_spec'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fae0b5336004efcdc1dbaa0734dd89f73e5e5be5
https://github.com/qemu/qemu/commit/fae0b5336004efcdc1dbaa0734dd89f73e5e5be5
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: move 'vlen' to riscv_cpu_properties[]
Turning 'vlen' into a class property will allow its default value to be
overwritten by cpu_init() later on, solving the issue we have now where
CPU specific settings are getting overwritten by the default.
Common validation bits are moved from riscv_cpu_validate_v() to
prop_vlen_set() to be shared with KVM.
And, as done with every option we migrated to riscv_cpu_properties[],
vendor CPUs can't have their 'vlen' value changed.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9d1173d20d86b4bbeda4166b3b709b5dbb4c507d
https://github.com/qemu/qemu/commit/9d1173d20d86b4bbeda4166b3b709b5dbb4c507d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: move 'elen' to riscv_cpu_properties[]
Do the same thing we did with 'vlen' in the previous patch with 'elen'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bbef914044f6db3aaaa9eb8bee64446a679f0387
https://github.com/qemu/qemu/commit/bbef914044f6db3aaaa9eb8bee64446a679f0387
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm/kvm-cpu.c
M target/riscv/kvm/kvm_riscv.h
Log Message:
-----------
target/riscv: create finalize_features() for KVM
To turn cbom_blocksize and cboz_blocksize into class properties we need
KVM specific changes.
KVM is creating its own version of these options with a customized
setter() that prevents users from picking an invalid value during init()
time. This comes at the cost of duplicating each option that KVM
supports. This will keep happening for each new shared option KVM
implements in the future.
We can avoid that by using the same property TCG uses and adding
specific KVM handling during finalize() time, like TCG already does with
riscv_tcg_cpu_finalize_features(). To do that, the common CPU property
offers a way of knowing if an option was user set or not, sparing us
from doing unneeded syscalls.
riscv_kvm_cpu_finalize_features() is then created using the same
KVMScratch CPU we already use during init() time, since finalize() time
is still too early to use the official KVM CPU for it. cbom_blocksize
and cboz_blocksize are then handled during finalize() in the same way
they're handled by their KVM specific setter.
With this change we can proceed with the blocksize changes in the common
code without breaking the KVM driver.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b84efa39a0cb1c8661da478d9d52d5fb80c95154
https://github.com/qemu/qemu/commit/b84efa39a0cb1c8661da478d9d52d5fb80c95154
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]
After adding a KVM finalize() implementation, turn cbom_blocksize into a
class property. Follow the same design we used with 'vlen' and 'elen'.
The duplicated 'cbom_blocksize' KVM property can be removed from
kvm_riscv_add_cpu_user_properties().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 811ef85324561b322b81d0c3ae610ab5a8881d7c
https://github.com/qemu/qemu/commit/811ef85324561b322b81d0c3ae610ab5a8881d7c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]
Do the same we did with 'cbom_blocksize' in the previous patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 82f7b1d40495584f526f826e9e6607500a4d391e
https://github.com/qemu/qemu/commit/82f7b1d40495584f526f826e9e6607500a4d391e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]
And remove the now unused kvm_cpu_set_cbomz_blksize() setter.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 08a2538710e5bd8c13c85b18fed31ff25e53f4e2
https://github.com/qemu/qemu/commit/08a2538710e5bd8c13c85b18fed31ff25e53f4e2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm/kvm-cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: remove riscv_cpu_options[]
The array is empty and can be removed.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a9a25939c22a05dd66ea4554534aa007d2f0dddd
https://github.com/qemu/qemu/commit/a9a25939c22a05dd66ea4554534aa007d2f0dddd
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]
Keep all class properties in riscv_cpu_properties[].
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9bb9d424296e6350142c9e4e31b14dcd4c0442ae
https://github.com/qemu/qemu/commit/9bb9d424296e6350142c9e4e31b14dcd4c0442ae
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]
Keep all class properties in riscv_cpu_properties[].
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 10efbe01ce40845aa2324d2abecd6664c7d8bf1c
https://github.com/qemu/qemu/commit/10efbe01ce40845aa2324d2abecd6664c7d8bf1c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]
Keep all class properties in riscv_cpu_properties[].
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0c4e579aac30abd26818ebaec8e1b633eb9f3952
https://github.com/qemu/qemu/commit/0c4e579aac30abd26818ebaec8e1b633eb9f3952
Author: Alvin Chang <alvinga@andestech.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/csr.c
M target/riscv/debug.c
Log Message:
-----------
target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231219123244.290935-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 04eb30a03cfc4195161996746d18a715457e0b42
https://github.com/qemu/qemu/commit/04eb30a03cfc4195161996746d18a715457e0b42
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: add 'vlenb' field in cpu->cfg
Our usage of 'vlenb' is overwhelming superior than the use of 'vlen'.
We're using 'vlenb' most of the time, having to do 'vlen >> 3' or
'vlen / 8' in every instance.
In hindsight we would be better if the 'vlenb' property was introduced
instead of 'vlen'. That's not what happened, and now we can't easily get
rid of it due to user scripts all around. What we can do, however, is to
change our internal representation to use 'vlenb'.
Add a 'vlenb' field in cpu->cfg. It'll be set via the existing 'vlen'
property, i.e. setting 'vlen' will also set 'vlenb'.
We'll replace all 'vlen >> 3' code to use 'vlenb' directly. Start with
the single instance we have in target/riscv/cpu.c.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 39b5efa5b8fd60f80101cb0f04447a4679097096
https://github.com/qemu/qemu/commit/39b5efa5b8fd60f80101cb0f04447a4679097096
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv/csr.c: use 'vlenb' instead of 'vlen'
As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
reading CSR_VLENB.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7cb59921c05a6ac5c3a06cb2a9a7a76c00045239
https://github.com/qemu/qemu/commit/7cb59921c05a6ac5c3a06cb2a9a7a76c00045239
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 33383193c87a11054b51f30e74d105a994b39103
https://github.com/qemu/qemu/commit/33383193c87a11054b51f30e74d105a994b39103
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvbf16.c.inc
Log Message:
-----------
target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
Use ctx->cfg_ptr->vlenb instead of ctx->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 81b9ef995a3b2fa5b08fab0615a1c9ed7cbe053e
https://github.com/qemu/qemu/commit/81b9ef995a3b2fa5b08fab0615a1c9ed7cbe053e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
"s->cfg_ptr->vlen >> 3".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f5a5e71e015266015e21dbd4894583e2fe471ba6
https://github.com/qemu/qemu/commit/f5a5e71e015266015e21dbd4894583e2fe471ba6
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvvk.c.inc
Log Message:
-----------
target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 58bc9063ec06c7b1812ae787b748f05838cae193
https://github.com/qemu/qemu/commit/58bc9063ec06c7b1812ae787b748f05838cae193
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: use 'vlenb'
Use 'cpu->cfg.vlenb' instead of 'cpu->cfg.vlen >> 3'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7aa4d519cba610876abac027a5812af87c834d22
https://github.com/qemu/qemu/commit/7aa4d519cba610876abac027a5812af87c834d22
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
to use vlenb.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bd2c82283d21e3400d7d89676a221935904c2fe6
https://github.com/qemu/qemu/commit/bd2c82283d21e3400d7d89676a221935904c2fe6
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
Calculate the maximum vector size possible, 'max_sz', which is the size
in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when
s->lmul = 3).
'max_sz' is then shifted right by 'scale', expressed as '3 - s->lmul',
which is clearer than doing 'scale = lmul - 3' and then using '-scale'
in the shift right.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 24a6aeecfe2721f953bb3d8ebca71ec7688041b7
https://github.com/qemu/qemu/commit/24a6aeecfe2721f953bb3d8ebca71ec7688041b7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
Rename the existing 'sew' variable to 'vsew' for extra clarity.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cd21576de6f0bef735186dfde10ae70db730d852
https://github.com/qemu/qemu/commit/cd21576de6f0bef735186dfde10ae70db730d852
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: change vext_get_vlmax() arguments
We'll re-use the logic froim vext_get_vlmax() in 2 other occurrences in
the next patch, but first we need to make it independent of both 'cpu'
and 'vtype'. To do that, add 'vlenb', 'vsew' and 'lmul' as parameters
instead.
Adapt the two existing callers. In cpu_get_tb_cpu_state(), rename 'sew'
to 'vsew' to be less ambiguous about what we're encoding into *pflags.
In HELPER(vsetvl) the following changes were made:
- add a 'vsew' var to store vsew. Use it in the shift to get 'sew';
- the existing 'lmul' var was renamed to 'vlmul';
- add a new 'lmul' var to store 'lmul' encoded like DisasContext:lmul.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 25669d275ce70346b94e3d5e4475d619eb979f5e
https://github.com/qemu/qemu/commit/25669d275ce70346b94e3d5e4475d619eb979f5e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()
Use the helper instead of calculating vlmax by hand.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4f6d036cccf84180bca7e45156f3a04032b624e1
https://github.com/qemu/qemu/commit/4f6d036cccf84180bca7e45156f3a04032b624e1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/cpu.c: remove cpu->cfg.vlen
There is no need to keep both 'vlen' and 'vlenb'. All existing code
that requires 'vlen' is retrieving it via 'vlenb << 3'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fafb0dc4d4805da596b0ad39281fa6df504d05b3
https://github.com/qemu/qemu/commit/fafb0dc4d4805da596b0ad39281fa6df504d05b3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: change kvm_reg_id to uint64_t
The field isn't big enough to hold an uint64_t kvm register and Vector
registers will end up overflowing it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240123161714.160149-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d4ff3da8f45c52670941c6e1b94e771d69d887e9
https://github.com/qemu/qemu/commit/d4ff3da8f45c52670941c6e1b94e771d69d887e9
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: initialize 'vlenb' via get-reg-list
KVM will check for the correct 'reg_size' when accessing the vector
registers, erroring with EINVAL if we encode the wrong size in reg ID.
Vector registers varies in size with the vector length in bytes, or
'vlenb'. This means that we need the current 'vlenb' being used by the
host, otherwise we won't be able to fetch all vector regs.
We'll deal with 'vlenb' first. Its support was added in Linux 6.8 as a
get-reg-list register. We'll read 'vlenb' via get-reg-list and mark the
register as 'supported'. All 'vlenb' ops via kvm_arch_get_registers()
and kvm_arch_put_registers() will only be done if the reg is supported,
i.e. we fetched it in get-reg-list during init.
If the user sets a new vlenb value using the 'vlen' property, throw an
error if the user value differs from the host.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240123161714.160149-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6f4a6248bb647d4fc6a349b448038a24eceb4d95
https://github.com/qemu/qemu/commit/6f4a6248bb647d4fc6a349b448038a24eceb4d95
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: get/set vector vregs[]
vregs[] have variable size that depends on the current vlenb set by the
host, meaning we can't use our regular kvm_riscv_reg_id() to retrieve
it.
Create a generic kvm_encode_reg_size_id() helper to encode any given
size in bytes into a given kvm reg id. kvm_riscv_vector_reg_id() will
use it to encode vlenb into a given vreg ID.
kvm_riscv_(get|set)_vector() can then get/set all 32 vregs.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240123161714.160149-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0e350c1adab597ecb194a0c091c2180deed96d59
https://github.com/qemu/qemu/commit/0e350c1adab597ecb194a0c091c2180deed96d59
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Remove misa_mxl validation
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240203-riscv-v11-1-a23f4848a628@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 742cc269c7e67352ebeecc528b0ade547a24de72
https://github.com/qemu/qemu/commit/742cc269c7e67352ebeecc528b0ade547a24de72
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/boot.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Move misa_mxl_max to class
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240203-riscv-v11-2-a23f4848a628@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1563cdb439e93a37c9bf8570ed80abc3a429d71b
https://github.com/qemu/qemu/commit/1563cdb439e93a37c9bf8570ed80abc3a429d71b
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Validate misa_mxl_max only once
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240203-riscv-v11-3-a23f4848a628@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ac8c8b6d1e5618f8fd293d9e451d87fb0d3867b3
https://github.com/qemu/qemu/commit/ac8c8b6d1e5618f8fd293d9e451d87fb0d3867b3
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu_bits.h
Log Message:
-----------
target/riscv: FCSR doesn't contain vxrm and vxsat
vxrm and vxsat have been moved into a special register vcsr since
RVV v1.0. So remove them from FCSR for vector 1.0.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240130110945.486-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a5cb044ca4fef8f24b1a585f3dd3719da88aa9e3
https://github.com/qemu/qemu/commit/a5cb044ca4fef8f24b1a585f3dd3719da88aa9e3
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Use RISCVException as return type for all csr ops
The real return value type has been converted to RISCVException,
but some function declarations still not. This patch makes all
csr operation declarations use RISCVExcetion.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240130110844.437-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1a49762c07d001ce291e4fc6773317f5611af3a4
https://github.com/qemu/qemu/commit/1a49762c07d001ce291e4fc6773317f5611af3a4
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/virt-acpi-build.c
Log Message:
-----------
hw/riscv/virt-acpi-build.c: fix leak in build_rhct()
The 'isa' char pointer isn't being freed after use.
Issue detected by Valgrind:
==38752== 128 bytes in 1 blocks are definitely lost in loss record 3,190 of
3,884
==38752== at 0x484280F: malloc (vg_replace_malloc.c:442)
==38752== by 0x5189619: g_malloc (gmem.c:130)
==38752== by 0x51A5BF2: g_strconcat (gstrfuncs.c:628)
==38752== by 0x6C1E3E: riscv_isa_string_ext (cpu.c:2321)
==38752== by 0x6C1E3E: riscv_isa_string (cpu.c:2343)
==38752== by 0x6BD2EA: build_rhct (virt-acpi-build.c:232)
==38752== by 0x6BD2EA: virt_acpi_build (virt-acpi-build.c:556)
==38752== by 0x6BDC86: virt_acpi_setup (virt-acpi-build.c:662)
==38752== by 0x9C8DC6: notifier_list_notify (notify.c:39)
==38752== by 0x4A595A: qdev_machine_creation_done (machine.c:1589)
==38752== by 0x61E052: qemu_machine_creation_done (vl.c:2680)
==38752== by 0x61E052: qmp_x_exit_preconfig.part.0 (vl.c:2709)
==38752== by 0x6220C6: qmp_x_exit_preconfig (vl.c:2702)
==38752== by 0x6220C6: qemu_init (vl.c:3758)
==38752== by 0x425858: main (main.c:47)
Fixes: ebfd392893 ("hw/riscv/virt: virt-acpi-build.c: Add RHCT Table")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122221529.86562-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 74416394b57e4bcd73c5d90eb7f2bd4d9a6e1ac8
https://github.com/qemu/qemu/commit/74416394b57e4bcd73c5d90eb7f2bd4d9a6e1ac8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/numa.c
Log Message:
-----------
hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()
Use g_autofree in 'dist_matrix' to avoid the manual g_free().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122221529.86562-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 73cdf38a92674768d2351cb4137a5dc9f116132b
https://github.com/qemu/qemu/commit/73cdf38a92674768d2351cb4137a5dc9f116132b
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus()
Move all char pointers to the loop. Use g_autofree in all of them to
avoid the g_free() calls.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240122221529.86562-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5d0e3bcb6648253f00e51c8240ff1998ab94f3f3
https://github.com/qemu/qemu/commit/5d0e3bcb6648253f00e51c8240ff1998ab94f3f3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use g_autofree in create_fdt_sockets()
Move 'clust_name' inside the loop, and g_autofree, to avoid having to
g_free() manually in each loop iteration.
'intc_phandles' is also g_autofreed to avoid another manual g_free().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122221529.86562-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1d873c6ecf984b69f69e918a8b1ced4de2097fbe
https://github.com/qemu/qemu/commit/1d873c6ecf984b69f69e918a8b1ced4de2097fbe
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use g_autofree in create_fdt_virtio()
Put 'name' declaration inside the loop, with g_autofree, to avoid
manually doing g_free() in each iteration.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240122221529.86562-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c70dc31f3010931e700e4786e2a3d8ab474c6a05
https://github.com/qemu/qemu/commit/c70dc31f3010931e700e4786e2a3d8ab474c6a05
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use g_autofree in virt_machine_init()
Move 'soc_name' to the loop, and give it g_autofree, to avoid the manual
g_free().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240122221529.86562-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5fb20f76008e13f99ec42867f4ebd4089b71ba96
https://github.com/qemu/qemu/commit/5fb20f76008e13f99ec42867f4ebd4089b71ba96
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use g_autofree in create_fdt_*
We have a lot of cases where a char or an uint32_t pointer is used once
to alloc a string/array, read/written during the function, and then
g_free() at the end. There's no pointer re-use - a single alloc, a
single g_free().
Use 'g_autofree' to avoid the g_free() calls.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122221529.86562-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8caeda5bf5ba73b080a79ca09203372a94d36e49
https://github.com/qemu/qemu/commit/8caeda5bf5ba73b080a79ca09203372a94d36e49
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add Zaamo and Zalrsc extension infrastructure
These extensions represent the atomic operations from A (Zaamo) and the
Load-Reserved/Store-Conditional operations from A (Zalrsc)
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240123111030.15074-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4f75d81225676268ce4cc8f81dd77df22dcedca0
https://github.com/qemu/qemu/commit/4f75d81225676268ce4cc8f81dd77df22dcedca0
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
Log Message:
-----------
target/riscv: Check 'A' and split extensions for atomic instructions
Following the pattern for 'M' and Zmmul check if either the 'A'
extension is enabled or the appropriate split extension for the
instruction.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240123111030.15074-3-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 79b50e2c80e50391b7f06b275fbc11f9a4ee168a
https://github.com/qemu/qemu/commit/79b50e2c80e50391b7f06b275fbc11f9a4ee168a
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose Zaamo and Zalrsc extensions
Expose the newly added extensions to the guest and allow their control
through the CPU properties.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240123111030.15074-4-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: afa42c21b5984bb9846e498bb00b1bdc28f56ab5
https://github.com/qemu/qemu/commit/afa42c21b5984bb9846e498bb00b1bdc28f56ab5
Author: Conor Dooley <conor.dooley@microchip.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: use misa_mxl_max to populate isa string rather than
TARGET_LONG_BITS
A cpu may not have the same xlen as the compile time target, and
misa_mxl_max is the source of truth for what the hart supports.
The conversion from misa_mxl_max to xlen already has one user, so
introduce a helper and use that to populate the isa string.
Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240124-swear-monthly-56c281f809a6@spud>
[ Changes by AF:
- Convert to use RISCVCPUClass *mcc
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1c8e491c457128f9b55b7093c8c0e3d66baf415f
https://github.com/qemu/qemu/commit/1c8e491c457128f9b55b7093c8c0e3d66baf415f
Author: Conor Dooley <conor.dooley@microchip.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: support new isa extension detection devicetree properties
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal was to replace "riscv,isa" with a new
set of properties that allowed for strictly defining the meaning of
various extensions, where "riscv,isa" was tied to whatever definitions
inflicted upon us by the ISA manual, which have seen some variance over
time.
Two new properties were introduced: "riscv,isa-base" and
"riscv,isa-extensions". The former is a simple string to communicate the
base ISA implemented by a hart and the latter an array of strings used
to communicate the set of ISA extensions supported, per the definitions
of each substring in extensions.yaml [1]. A beneficial side effect was
also the ability to define vendor extensions in a more "official" way,
as the ISA manual and other RVI specifications only covered the format
for vendor extensions in the ISA string, but not the meaning of vendor
extensions, for obvious reasons.
Add support for setting these two new properties in the devicetrees for
the various devicetree platforms supported by QEMU for RISC-V. The Linux
kernel already supports parsing ISA extensions from these new
properties, and documenting them in the dt-binding is a requirement for
new extension detection being added to the kernel.
A side effect of the implementation is that the meaning for elements in
"riscv,isa" and in "riscv,isa-extensions" are now tied together as they
are constructed from the same source. The same applies to the ISA string
provided in ACPI tables, but there does not appear to be any strict
definitions of meanings in ACPI land either.
Link:
https://lore.kernel.org/qemu-riscv/20230702-eats-scorebook-c951f170d29f@spud/
[0]
Link:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/extensions.yaml
[1]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240124-unvarying-foothold-9dde2aaf95d4@spud>
[ Changes by AF:
- Rebase on recent changes
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b5831d79671cea3f7bd42cffab93fe6eab8c3db0
https://github.com/qemu/qemu/commit/b5831d79671cea3f7bd42cffab93fe6eab8c3db0
Author: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/smbios/smbios.c
M qemu-options.hx
Log Message:
-----------
smbios: add processor-family option
For RISC-V the SMBIOS standard requires specific values of the processor
family value depending on the bitness of the CPU.
Add a processor-family option for SMBIOS table 4.
The value of processor-family may exceed 255 and therefore must be provided
in the Processor Family 2 field. Set the Processor Family field to 0xFE
which signals that the Processor Family 2 is used.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240123184229.10415-2-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6f3b727bcc867688034ef1489a58e958142973b1
https://github.com/qemu/qemu/commit/6f3b727bcc867688034ef1489a58e958142973b1
Author: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/smbios/smbios.c
M include/hw/firmware/smbios.h
Log Message:
-----------
smbios: function to set default processor family
Provide a function to set the default processor family.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240123184229.10415-3-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ecf286478475d11ae4cdef7e52d9c8e1672f2868
https://github.com/qemu/qemu/commit/ecf286478475d11ae4cdef7e52d9c8e1672f2868
Author: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
Log Message:
-----------
target/riscv: SMBIOS support for RISC-V virt machine
Generate SMBIOS tables for the RISC-V mach-virt.
Add CONFIG_SMBIOS=y to the RISC-V default config.
Set the default processor family in the type 4 table.
The implementation is based on the corresponding ARM and Loongson code.
With the patch the following firmware tables are provided:
etc/smbios/smbios-anchor
etc/smbios/smbios-tables
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240123184229.10415-4-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e2ff0dec156eff4e109c678654df1225d384fd14
https://github.com/qemu/qemu/commit/e2ff0dec156eff4e109c678654df1225d384fd14
Author: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options: enable -smbios option on RISC-V
With SMBIOS support added for RISC-V we also should enable the command line
option.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240123184229.10415-5-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a65d51707d891bfe99c448fa0a6c80341b64ac12
https://github.com/qemu/qemu/commit/a65d51707d891bfe99c448fa0a6c80341b64ac12
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Enable xtheadsync under user mode
According to xtheadsync[1][2] documentation, it can be used in user mode and
the behavior is same with other priviledges.
[1]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsync/sync.adoc
[2]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsync/sync_i.adoc
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240204055228.900-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b077aec9c980a1b67adc63c8475d42d50ed8ac37
https://github.com/qemu/qemu/commit/b077aec9c980a1b67adc63c8475d42d50ed8ac37
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add riscv_bare_cpu_init()
Next patch will add more bare CPUs. Their cpu_init() functions would be
glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a
riscv_cpu_set_misa() call.
Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this
code repetition. While we're at it, add a better explanation on why
we're disabling the timing extensions for bare CPUs.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122123348.973288-2-dbarboza@ventanamicro.com>
[ Changes by AF:
- Rebase on latest changes
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: deb0ff0c777d20602ecc5b6f74f18cb7ecc0b91f
https://github.com/qemu/qemu/commit/deb0ff0c777d20602ecc5b6f74f18cb7ecc0b91f
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add rv32i, rv32e and rv64e CPUs
A bare bones 32 bit RVI CPU, rv32i, will make users lives easier when a
full customized 32 bit CPU is desired, and users won't need to disable
defaults by hand as they would with the rv32 CPU. [1] has an example of
a situation that would be avoided with rv32i.
In fact, add bare bones CPUs for RVE as well. Trying to use RVE in QEMU
requires one to disable every single default extension, including RVI,
and then add the desirable extension set. Adding rv32e/rv64e makes it
more pleasant to use embedded CPUs in QEMU.
[1]
https://lore.kernel.org/qemu-riscv/258be47f-97be-4308-bed5-dc34ef7ff954@Spark/
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122123348.973288-3-dbarboza@ventanamicro.com>
[ Changes by AF:
- Rebase on latest changes
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: df50424b4dcfde823047d3717abd6a61224ea205
https://github.com/qemu/qemu/commit/df50424b4dcfde823047d3717abd6a61224ea205
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/boot.c
M hw/riscv/numa.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt-acpi-build.c
M hw/riscv/virt.c
M hw/smbios/smbios.c
M include/hw/firmware/smbios.h
M qemu-options.hx
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/gdbstub.c
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/kvm/kvm-cpu.c
M target/riscv/kvm/kvm_riscv.h
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20240209' of
https://github.com/alistair23/qemu into staging
RISC-V PR for 9.0
* Check for 'A' extension on all atomic instructions
* Add support for 'B' extension
* Internally deprecate riscv_cpu_options
* Implement optional CSR mcontext of debug Sdtrig extension
* Internally add cpu->cfg.vlenb and remove cpu->cfg.vlen
* Support vlenb and vregs[] in KVM
* RISC-V gdbstub and TCG plugin improvements
* Remove vxrm and vxsat from FCSR
* Use RISCVException as return type for all csr ops
* Use g_autofree more and fix a memory leak
* Add support for Zaamo and Zalrsc
* Support new isa extension detection devicetree properties
* SMBIOS support for RISC-V virt machine
* Enable xtheadsync under user mode
* Add rv32i,rv32e and rv64e CPUs
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# gpg: Signature made Fri 09 Feb 2024 10:57:20 GMT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240209' of https://github.com/alistair23/qemu: (61
commits)
target/riscv: add rv32i, rv32e and rv64e CPUs
target/riscv/cpu.c: add riscv_bare_cpu_init()
target/riscv: Enable xtheadsync under user mode
qemu-options: enable -smbios option on RISC-V
target/riscv: SMBIOS support for RISC-V virt machine
smbios: function to set default processor family
smbios: add processor-family option
target/riscv: support new isa extension detection devicetree properties
target/riscv: use misa_mxl_max to populate isa string rather than
TARGET_LONG_BITS
target/riscv: Expose Zaamo and Zalrsc extensions
target/riscv: Check 'A' and split extensions for atomic instructions
target/riscv: Add Zaamo and Zalrsc extension infrastructure
hw/riscv/virt.c: use g_autofree in create_fdt_*
hw/riscv/virt.c: use g_autofree in virt_machine_init()
hw/riscv/virt.c: use g_autofree in create_fdt_virtio()
hw/riscv/virt.c: use g_autofree in create_fdt_sockets()
hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus()
hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()
hw/riscv/virt-acpi-build.c: fix leak in build_rhct()
target/riscv: Use RISCVException as return type for all csr ops
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/5d1fc614413b...df50424b4dcf