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[Qemu-commits] [qemu/qemu] f670be: target/arm: fix exception syndrome fo
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] f670be: target/arm: fix exception syndrome for AArch32 bkp... |
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Date: |
Fri, 02 Feb 2024 11:02:12 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: f670be1aad33e801779af580398895b9455747ee
https://github.com/qemu/qemu/commit/f670be1aad33e801779af580398895b9455747ee
Author: Jan Klötzke <jan.kloetzke@kernkonzept.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M target/arm/helper.c
M target/arm/syndrome.h
Log Message:
-----------
target/arm: fix exception syndrome for AArch32 bkpt insn
Debug exceptions that target AArch32 Hyp mode are reported differently
than on AAarch64. Internally, Qemu uses the AArch64 syndromes. Therefore
such exceptions need to be either converted to a prefetch abort
(breakpoints, vector catch) or a data abort (watchpoints).
Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Klötzke <jan.kloetzke@kernkonzept.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240127202758.3326381-1-jan.kloetzke@kernkonzept.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e6c03989af6dcdfdd64ff717a8b4b47f3848c0b7
https://github.com/qemu/qemu/commit/e6c03989af6dcdfdd64ff717a8b4b47f3848c0b7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/pci/pci.c
Log Message:
-----------
pci: Switch bus reset to 3-phase-reset
Switch the PCI bus from using BusClass::reset to the Resettable
interface.
This has no behavioural change, because the BusClass code to support
subclasses that use the legacy BusClass::reset will call that method
in the hold phase of 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-2-peter.maydell@linaro.org
Commit: d7f35529287abf0ed66e83eb0614bc24186f6957
https://github.com/qemu/qemu/commit/d7f35529287abf0ed66e83eb0614bc24186f6957
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/hyperv/vmbus.c
Log Message:
-----------
vmbus: Switch bus reset to 3-phase-reset
Switch vmbus from using BusClass::reset to the Resettable interface.
This has no behavioural change, because the BusClass code to support
subclasses that use the legacy BusClass::reset will call that method
in the hold phase of 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-3-peter.maydell@linaro.org
Commit: 5c9ca5d72b312b53ed85e434e381608129d632c9
https://github.com/qemu/qemu/commit/5c9ca5d72b312b53ed85e434e381608129d632c9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/input/adb.c
Log Message:
-----------
adb: Switch bus reset to 3-phase-reset
Switch the ADB bus from using BusClass::reset to the Resettable
interface.
This has no behavioural change, because the BusClass code to support
subclasses that use the legacy BusClass::reset will call that method
in the hold phase of 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-4-peter.maydell@linaro.org
Commit: 412a91f67c7482408a650bc6580c2c695e71ff44
https://github.com/qemu/qemu/commit/412a91f67c7482408a650bc6580c2c695e71ff44
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/s390x/css-bridge.c
Log Message:
-----------
hw/s390x/css-bridge: switch virtual-css bus to 3-phase-reset
Switch the s390x virtual-css bus from using BusClass::reset to the
Resettable interface.
This has no behavioural change, because the BusClass code to support
subclasses that use the legacy BusClass::reset will call that method
in the hold phase of 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Halil Pasic <pasic@linux.ibm.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-5-peter.maydell@linaro.org
Commit: cb711a6d7f852b6a61b8c83c4538b93c7b91ebe8
https://github.com/qemu/qemu/commit/cb711a6d7f852b6a61b8c83c4538b93c7b91ebe8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/core/bus.c
M include/hw/qdev-core.h
Log Message:
-----------
hw/core: Remove transitional infrastructure from BusClass
BusClass currently has transitional infrastructure to support
subclasses which implement the legacy BusClass::reset method rather
than the Resettable interface. We have now removed all the users of
BusClass::reset in the tree, so we can remove the transitional
infrastructure.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-6-peter.maydell@linaro.org
Commit: d2019a9d0c34a4fdcb5b5df550d73040dc0637d9
https://github.com/qemu/qemu/commit/d2019a9d0c34a4fdcb5b5df550d73040dc0637d9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M system/vl.c
Log Message:
-----------
system/vl.c: Fix handling of '-serial none -serial something'
Currently if the user passes multiple -serial options on the command
line, we mostly treat those as applying to the different serial
devices in order, so that for example
-serial stdio -serial file:filename
will connect the first serial port to stdio and the second to the
named file.
The exception to this is the '-serial none' serial device type. This
means "don't allocate this serial device", but a bug means that
following -serial options are not correctly handled, so that
-serial none -serial stdio
has the unexpected effect that stdio is connected to the first serial
port, not the second.
This is a very long-standing bug that dates back at least as far as
commit 998bbd74b9d81 from 2009.
Make the 'none' serial type move forward in the indexing of serial
devices like all the other serial types, so that any subsequent
-serial options are correctly handled.
Note that if your commandline mistakenly had a '-serial none' that
was being overridden by a following '-serial something' option, you
should delete the unnecessary '-serial none'. This will give you the
same behaviour as before, on QEMU versions both with and without this
bug fix.
Cc: qemu-stable@nongnu.org
Reported-by: Bohdan Kostiv <bohdan.kostiv@tii.ae>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240122163607.459769-2-peter.maydell@linaro.org
Fixes: 998bbd74b9d81 ("default devices: core code & serial lines")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 747bfaf3a9d2f3cd51674763dc1f7575100cd200
https://github.com/qemu/qemu/commit/747bfaf3a9d2f3cd51674763dc1f7575100cd200
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options.hx: Improve -serial option documentation
The -serial option documentation is a bit brief about '-serial none'
and '-serial null'. In particular it's not very clear about the
difference between them, and it doesn't mention that it's up to
the machine model whether '-serial none' means "don't create the
serial port" or "don't wire the serial port up to anything".
Expand on these points.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240122163607.459769-3-peter.maydell@linaro.org
Commit: 9f2e8ac0900fd5645f6a5f38ca0fc751fa602f45
https://github.com/qemu/qemu/commit/9f2e8ac0900fd5645f6a5f38ca0fc751fa602f45
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M target/arm/helper.c
M tests/tcg/aarch64/sysregs.c
Log Message:
-----------
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
In kernel commit 5d5b4e8c2d9ec ("arm64/sve: Report FEAT_SVE_B16B16 to
userspace") Linux added ID_AA64ZFR0_el1.B16B16 to the set of ID
register fields which it exposes to userspace. Update our
exported_bits mask to include this.
(This doesn't yet change any behaviour for us, because we don't yet
have any CPUs that implement this feature, which is part of SVE2.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240125134304.1470404-1-peter.maydell@linaro.org
Commit: cabe58b0f8542d5c3dd1eca0b4def50bee1ffab4
https://github.com/qemu/qemu/commit/cabe58b0f8542d5c3dd1eca0b4def50bee1ffab4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M tests/qtest/xlnx-versal-trng-test.c
Log Message:
-----------
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
This test program is the last use of any variable length array in the
codebase. If we can get rid of all uses of VLAs we can make the
compiler error on new additions. This is a defensive measure against
security bugs where an on-stack dynamic allocation isn't correctly
size-checked (e.g. CVE-2021-3527).
In this case the test code didn't even want a variable-sized
array, it was just accidentally using syntax that gave it one.
(The array size for C has to be an actual constant expression,
not just something that happens to be known to be constant...)
Remove the VLA usage.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240125173211.1786196-2-peter.maydell@linaro.org
Commit: 185e3fdf8d106cb2f7d234d5e6453939c66db2a9
https://github.com/qemu/qemu/commit/185e3fdf8d106cb2f7d234d5e6453939c66db2a9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Reinstate "vfp" property on AArch32 CPUs
In commit 4315f7c614743 we restructured the logic for creating the
VFP related properties to avoid testing the aa32_simd_r32 feature on
AArch64 CPUs. However in the process we accidentally stopped
exposing the "vfp" QOM property on AArch32 TCG CPUs.
This mostly hasn't had any ill effects because not many people want
to disable VFP, but it wasn't intentional. Reinstate the property.
Cc: qemu-stable@nongnu.org
Fixes: 4315f7c614743 ("target/arm: Restructure has_vfp_d32 test")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2098
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240126193432.2210558-1-peter.maydell@linaro.org
Commit: 1eeb432a953b0fc7744f119107230ae1892d2dd2
https://github.com/qemu/qemu/commit/1eeb432a953b0fc7744f119107230ae1892d2dd2
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M docs/devel/docs.rst
M docs/sphinx/hxtool.py
M docs/system/i386/xen.rst
M qemu-options.hx
Log Message:
-----------
doc/sphinx/hxtool.py: add optional label argument to SRST directive
We can't just embed labels directly into files like qemu-options.hx which
are included from multiple top-level rST files, because Sphinx sees the
labels as duplicate: https://github.com/sphinx-doc/sphinx/issues/9707
So add an optional argument to the SRST directive which causes a label
of the form '.. _DOCNAME-HXFILE-LABEL:' to be emitted, where 'DOCNAME'
is the name of the top level rST file, 'HXFILE' is the filename of the
.hx file, and 'LABEL' is the text provided within the 'SRST()' directive.
Using the DOCNAME of the top-level rST document means that it is unique
even when the .hx file is included from two different documents, as is
the case for qemu-options.hx
Now where the Xen PV documentation refers to the documentation for the
-initrd command line option, it can emit a link directly to it as
'<system/invocation-qemu-options-initrd>'.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240130190348.682912-1-dwmw2@infradead.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f57d3baa9c836c196f4164dde0d95ecee8d335dd
https://github.com/qemu/qemu/commit/f57d3baa9c836c196f4164dde0d95ecee8d335dd
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/exynos4210.c
Log Message:
-----------
hw/arm/exynos: Add missing QOM parent for CPU cores
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 56d69aaf511db5995f8939019c4373ebd04cde08
https://github.com/qemu/qemu/commit/56d69aaf511db5995f8939019c4373ebd04cde08
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/exynos4_boards.c
Log Message:
-----------
hw/arm/exynos: Check for CPU types in machine_run_board_init()
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Instead of ignoring invalid CPU type requested by the user:
$ qemu-system-arm -M nuri -cpu cortex-a7 -S -monitor stdio
QEMU 8.2.50 monitor - type 'help' for more information
(qemu) info qom-tree
/machine (nuri-machine)
/soc (exynos4210)
/cpu[0] (cortex-a9-arm-cpu)
...
We now display an error:
$ qemu-system-arm -M nuri -cpu cortex-a7
qemu-system-arm: Invalid CPU model: cortex-a7
The only valid type is: cortex-a9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6a4e61170f2b7769cd9034c0fdf05f6c64a74fbf
https://github.com/qemu/qemu/commit/6a4e61170f2b7769cd9034c0fdf05f6c64a74fbf
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/highbank.c
Log Message:
-----------
hw/arm/highbank: Add missing QOM parent for CPU cores
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 104395bc661b41055aaae1d8eb95bd2d99bdd20f
https://github.com/qemu/qemu/commit/104395bc661b41055aaae1d8eb95bd2d99bdd20f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/highbank.c
Log Message:
-----------
hw/arm/highbank: Check for CPU types in machine_run_board_init()
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU types.
Instead of ignoring invalid CPU type requested by the user:
$ qemu-system-arm -M midway -cpu cortex-a7 -S -monitor stdio
QEMU 8.2.50 monitor - type 'help' for more information
(qemu) info qom-tree
/machine (midway-machine)
/cpu[0] (cortex-a15-arm-cpu)
...
we now display an error:
$ qemu-system-arm -M midway -cpu cortex-a7
qemu-system-arm: Invalid CPU model: cortex-a7
The only valid type is: cortex-a15
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 04f4915424743671ca70c405ab69bc0a3ed8d937
https://github.com/qemu/qemu/commit/04f4915424743671ca70c405ab69bc0a3ed8d937
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/msf2-soc.c
M hw/arm/msf2-som.c
M include/hw/arm/msf2-soc.h
Log Message:
-----------
hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]
The M2Sxxx SoC family can only be used with Cortex-M3.
Propagating the CPU type from the board level is pointless.
Hard-code the CPU type at the SoC level.
Remove the now ignored MachineClass::default_cpu_type field.
Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 858ab7140db46cfe14f38ce5c0643c289df0a515
https://github.com/qemu/qemu/commit/858ab7140db46cfe14f38ce5c0643c289df0a515
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/musca.c
Log Message:
-----------
hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]
Musca boards use the embedded subsystems (SSE) tied to a specific
Cortex core. Our models only use the Cortex-M33.
Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.
Remove the now unused MachineClass::default_cpu_type field.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 467c6f84f91c387c56837995cc0293258174efdb
https://github.com/qemu/qemu/commit/467c6f84f91c387c56837995cc0293258174efdb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/npcm7xx_boards.c
Log Message:
-----------
hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]
The npcm7xx Soc is created with a Cortex-A9 core, see in
hw/arm/npcm7xx.c:
static void npcm7xx_init(Object *obj)
{
NPCM7xxState *s = NPCM7XX(obj);
for (int i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[i],
ARM_CPU_TYPE_NAME("cortex-a9"));
}
The MachineClass::default_cpu_type field is ignored: delete it.
Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: de71271a2d94f16f873c333c5962fcf8568580c6
https://github.com/qemu/qemu/commit/de71271a2d94f16f873c333c5962fcf8568580c6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/vexpress.c
Log Message:
-----------
hw/arm/vexpress: Check for CPU types in machine_run_board_init()
Leverage the common code introduced in commit c9cf636d48 ("machine:
Add a valid_cpu_types property") to check for the single valid CPU
type. Remove the now unused MachineClass::default_cpu_type field.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 12af201a59e4cfc55381aae4ccb8cd071f026b0d
https://github.com/qemu/qemu/commit/12af201a59e4cfc55381aae4ccb8cd071f026b0d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/xilinx_zynq.c
Log Message:
-----------
hw/arm/zynq: Check for CPU types in machine_run_board_init()
Leverage the common code introduced in commit c9cf636d48 ("machine:
Add a valid_cpu_types property") to check for the single valid CPU
type. Remove the now unused MachineClass::default_cpu_type field.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8a73152020337a7fbf34daf0a006d4d89ec1494e
https://github.com/qemu/qemu/commit/8a73152020337a7fbf34daf0a006d4d89ec1494e
Author: Guenter Roeck <linux@roeck-us.net>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/pci-host/designware.c
Log Message:
-----------
pci-host: designware: Limit value range of iATU viewport register
The latest version of qemu (v8.2.0-869-g7a1dc45af5) crashes when booting
the mcimx7d-sabre emulation with Linux v5.11 and later.
qemu-system-arm: ../system/memory.c:2750: memory_region_set_alias_offset:
Assertion `mr->alias' failed.
Problem is that the Designware PCIe emulation accepts the full value range
for the iATU Viewport Register. However, both hardware and emulation only
support four inbound and four outbound viewports.
The Linux kernel determines the number of supported viewports by writing
0xff into the viewport register and reading the value back. The expected
value when reading the register is the highest supported viewport index.
Match that code by masking the supported viewport value range when the
register is written. With this change, the Linux kernel reports
imx6q-pcie 33800000.pcie: iATU: unroll F, 4 ob, 4 ib, align 0K, limit 4G
as expected and supported.
Fixes: d64e5eabc4c7 ("pci: Add support for Designware IP block")
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20240129060055.2616989-1-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5e5deca183388c31c28d600e9a2d97792fc1f211
https://github.com/qemu/qemu/commit/5e5deca183388c31c28d600e9a2d97792fc1f211
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/strongarm.c
M hw/arm/trace-events
Log Message:
-----------
hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors
Tracing DPRINTFs to stderr might not be desired. A developer that relies
on trace events should be able to opt-in to each trace event and rely on
QEMU's log redirection, instead of stderr by default.
This commit converts DPRINTFs in this file that are used for tracing
into trace events. DPRINTFs that report guest errors are logged with
LOG_GUEST_ERROR.#
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
39db71dd87bf2007cf7812f3d91dde53887f1f2f.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fcc554c7afb0613bf1a0a355e8123e818bfaf833
https://github.com/qemu/qemu/commit/fcc554c7afb0613bf1a0a355e8123e818bfaf833
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/trace-events
M hw/arm/z2.c
Log Message:
-----------
hw/arm/z2: convert DPRINTF to trace events and guest errors
Tracing DPRINTFs to stderr might not be desired. A developer that relies
on trace events should be able to opt-in to each trace event and rely on
QEMU's log redirection, instead of stderr by default.
This commit converts DPRINTFs in this file that are used for tracing
into trace events. DPRINTFs that report guest errors are logged with
LOG_GUEST_ERROR.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
799c5141c5751cf2341e1d095349612e046424a8.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6b4a990b42e647b3b2ad5991cd8b931036531f3f
https://github.com/qemu/qemu/commit/6b4a990b42e647b3b2ad5991cd8b931036531f3f
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/trace-events
M hw/arm/xen_arm.c
Log Message:
-----------
hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports
Tracing DPRINTFs to stderr might not be desired. A developer that relies
on trace events should be able to opt-in to each trace event and rely on
QEMU's log redirection, instead of stderr by default.
This commit converts DPRINTFs in this file that are used for tracing
into trace events. Errors or warnings are converted to error_report and
warn_report calls.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
fe5e3bd54231abe933f95a24e0e88208cd8cfd8f.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0402b96830dbc282c6d52e90eacb7b9da1da503c
https://github.com/qemu/qemu/commit/0402b96830dbc282c6d52e90eacb7b9da1da503c
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/xen/trace-events
M hw/xen/xen-mapcache.c
Log Message:
-----------
hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints
Tracing DPRINTFs to stderr might not be desired. A developer that relies
on tracepoints should be able to opt-in to each tracepoint and rely on
QEMU's log redirection, instead of stderr by default.
This commit converts DPRINTFs in this file that are used for tracing
into tracepoints.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
2fbe1fbc59078e384761c932e97cfa4276a53d75.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9a1f02a3549b1e4d97233a99c9c96ca0a061d047
https://github.com/qemu/qemu/commit/9a1f02a3549b1e4d97233a99c9c96ca0a061d047
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/xen/trace-events
M hw/xen/xen-hvm-common.c
Log Message:
-----------
hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints
Tracing DPRINTFs to stderr might not be desired. A developer that relies
on tracepoints should be able to opt-in to each tracepoint and rely on
QEMU's log redirection, instead of stderr by default.
This commit converts DPRINTFs in this file that are used for tracing
into tracepoints.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
b000ab73022dfeb7a7ab0ee8fd0f41fb208adaf0.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d0e16850eed350b1eac562f52bf81f2341923b4c
https://github.com/qemu/qemu/commit/d0e16850eed350b1eac562f52bf81f2341923b4c
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/xen/xen-hvm-common.c
M hw/xen/xen-mapcache.c
Log Message:
-----------
hw/xen: convert stderr prints to error/warn reports
According to the QEMU Coding Style document:
> Do not use printf(), fprintf() or monitor_printf(). Instead, use
> error_report() or error_vreport() from error-report.h. This ensures the
> error is reported in the right place (current monitor or stderr), and in
> a uniform format.
> Use error_printf() & friends to print additional information.
This commit changes fprintfs that report warnings and errors to the
appropriate report functions.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
42a8953553cf68e8bacada966f93af4fbce45919.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 08f787a34cbeca333bd9a79a5d6723c750abd56e
https://github.com/qemu/qemu/commit/08f787a34cbeca333bd9a79a5d6723c750abd56e
Author: Hao Wu <wuhaotsh@google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/net/meson.build
A hw/net/npcm_gmac.c
M hw/net/trace-events
A include/hw/net/npcm_gmac.h
Log Message:
-----------
hw/net: Add NPCMXXX GMAC device
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Squashed IRQ Implementation patch into this one for compliation.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Change-Id: If71c6d486b95edcccba109ba454870714d7e0940
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-2-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 21e5326a7c178fc50bba986d8091e6c5e0a0469c
https://github.com/qemu/qemu/commit/21e5326a7c178fc50bba986d8091e6c5e0a0469c
Author: Hao Wu <wuhaotsh@google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/npcm7xx.c
M include/hw/arm/npcm7xx.h
Log Message:
-----------
hw/arm: Add GMAC devices to NPCM7XX SoC
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-3-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 327b680877b79c4b5473b5d59265194f35a24c6f
https://github.com/qemu/qemu/commit/327b680877b79c4b5473b5d59265194f35a24c6f
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/npcm_gmac-test.c
Log Message:
-----------
tests/qtest: Creating qtest for GMAC Module
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-4-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a4dd7a1dad1d3d0ca270a403212ea93c801927db
https://github.com/qemu/qemu/commit/a4dd7a1dad1d3d0ca270a403212ea93c801927db
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/net/npcm_gmac.c
M hw/net/trace-events
Log Message:
-----------
hw/net: GMAC Rx Implementation
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP NIC device.
When RX descriptor list is full, it returns a DMA_STATUS for
software to handle it. But there's no way to indicate the software has
handled all RX descriptors and the whole pipeline stalls.
We do something similar to NPCM7XX EMC to handle this case.
1. Return packet size when RX descriptor is full, effectively dropping
these packets in such a case.
2. When software clears RX descriptor full bit, continue receiving
further packets by flushing QEMU packet queue.
Added relevant trace-events
Change-Id: I132aa254a94cda1a586aba2ea33bbfc74ecdb831
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-5-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1c51c571998a669712235cb35093ae817e19b3ff
https://github.com/qemu/qemu/commit/1c51c571998a669712235cb35093ae817e19b3ff
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/net/npcm_gmac.c
M hw/net/trace-events
Log Message:
-----------
hw/net: GMAC Tx Implementation
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
Change-Id: Icf14f9fcc6cc7808a41acd872bca67c9832087e6
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-6-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d710b337514d996db15e854e57a6f38b2685fbc0
https://github.com/qemu/qemu/commit/d710b337514d996db15e854e57a6f38b2685fbc0
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M tests/qtest/npcm_gmac-test.c
Log Message:
-----------
tests/qtest: Adding PCS Module test to GMAC Qtest
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-7-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 28004fb741343b77b1044a0f01d27d8b36b59651
https://github.com/qemu/qemu/commit/28004fb741343b77b1044a0f01d27d8b36b59651
Author: Rayhan Faizel <rayhan.faizel@gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M docs/system/arm/raspi.rst
M hw/ssi/Kconfig
A hw/ssi/bcm2835_spi.c
M hw/ssi/meson.build
A include/hw/ssi/bcm2835_spi.h
Log Message:
-----------
hw/ssi: Implement BCM2835 SPI Controller
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes
of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Message-id: 20240129221807.2983148-2-rayhan.faizel@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f09c2b7ba9908714a3e2f1decd989462536cf731
https://github.com/qemu/qemu/commit/f09c2b7ba9908714a3e2f1decd989462536cf731
Author: Rayhan Faizel <rayhan.faizel@gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M hw/arm/Kconfig
M hw/arm/bcm2835_peripherals.c
M include/hw/arm/bcm2835_peripherals.h
Log Message:
-----------
hw/arm: Connect SPI Controller to BCM2835
This patch will allow the SPI controller to be accessible from BCM2835 based
boards as SPI0. SPI driver is usually disabled by default and config.txt does
not work.
Instead, dtmerge can be used to apply spi=on on a bcm2835 dtb file.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Message-id: 20240129221807.2983148-3-rayhan.faizel@gmail.com
[PMM: indent tweak]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4f2fdb10b5f78ba95300648fce74c42d3e4511c7
https://github.com/qemu/qemu/commit/4f2fdb10b5f78ba95300648fce74c42d3e4511c7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M docs/devel/docs.rst
M docs/sphinx/hxtool.py
M docs/system/arm/raspi.rst
M docs/system/i386/xen.rst
M hw/arm/Kconfig
M hw/arm/bcm2835_peripherals.c
M hw/arm/exynos4210.c
M hw/arm/exynos4_boards.c
M hw/arm/highbank.c
M hw/arm/msf2-soc.c
M hw/arm/msf2-som.c
M hw/arm/musca.c
M hw/arm/npcm7xx.c
M hw/arm/npcm7xx_boards.c
M hw/arm/strongarm.c
M hw/arm/trace-events
M hw/arm/vexpress.c
M hw/arm/xen_arm.c
M hw/arm/xilinx_zynq.c
M hw/arm/z2.c
M hw/core/bus.c
M hw/hyperv/vmbus.c
M hw/input/adb.c
M hw/net/meson.build
A hw/net/npcm_gmac.c
M hw/net/trace-events
M hw/pci-host/designware.c
M hw/pci/pci.c
M hw/s390x/css-bridge.c
M hw/ssi/Kconfig
A hw/ssi/bcm2835_spi.c
M hw/ssi/meson.build
M hw/xen/trace-events
M hw/xen/xen-hvm-common.c
M hw/xen/xen-mapcache.c
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/msf2-soc.h
M include/hw/arm/npcm7xx.h
A include/hw/net/npcm_gmac.h
M include/hw/qdev-core.h
A include/hw/ssi/bcm2835_spi.h
M qemu-options.hx
M system/vl.c
M target/arm/cpu.c
M target/arm/helper.c
M target/arm/syndrome.h
M tests/qtest/meson.build
A tests/qtest/npcm_gmac-test.c
M tests/qtest/xlnx-versal-trng-test.c
M tests/tcg/aarch64/sysregs.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240202' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target/arm: fix exception syndrome for AArch32 bkpt insn
pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset
system/vl.c: Fix handling of '-serial none -serial something'
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
target/arm: Reinstate "vfp" property on AArch32 CPUs
doc/sphinx/hxtool.py: add optional label argument to SRST directive
hw/arm: Check for CPU types in machine_run_board_init() for various boards
pci-host: designware: Limit value range of iATU viewport register
hw/arm: Convert some DPRINTF macros to trace events and guest errors
hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices
hw/arm: Implement BCM2835 SPI Controller
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# y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq
# yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD
# jGjDBz6mryWvP2H0xSmERQ==
# =azdP
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240202' of
https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
hw/arm: Connect SPI Controller to BCM2835
hw/ssi: Implement BCM2835 SPI Controller
tests/qtest: Adding PCS Module test to GMAC Qtest
hw/net: GMAC Tx Implementation
hw/net: GMAC Rx Implementation
tests/qtest: Creating qtest for GMAC Module
hw/arm: Add GMAC devices to NPCM7XX SoC
hw/net: Add NPCMXXX GMAC device
hw/xen: convert stderr prints to error/warn reports
hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints
hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints
hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports
hw/arm/z2: convert DPRINTF to trace events and guest errors
hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors
pci-host: designware: Limit value range of iATU viewport register
hw/arm/zynq: Check for CPU types in machine_run_board_init()
hw/arm/vexpress: Check for CPU types in machine_run_board_init()
hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/29b008927ef6...4f2fdb10b5f7
- [Qemu-commits] [qemu/qemu] f670be: target/arm: fix exception syndrome for AArch32 bkp...,
Peter Maydell <=