[Qemu-commits] [qemu/qemu] 967071: include/hw/core: Add mmu

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[Qemu-commits] [qemu/qemu] 967071: include/hw/core: Add mmu_index to CPU

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 967071: include/hw/core: Add mmu_index to CPUClass
Date:	Fri, 02 Feb 2024 08:29:30 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 9670716be0b7c48cfb05ea07c489791804ae1a47
      
https://github.com/qemu/qemu/commit/9670716be0b7c48cfb05ea07c489791804ae1a47
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M include/hw/core/cpu.h

  Log Message:
  -----------
  include/hw/core: Add mmu_index to CPUClass

To be used after all targets have populated the hook.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f63b762a3da7b1b8d31d659616ad968b409a48df
      
https://github.com/qemu/qemu/commit/f63b762a3da7b1b8d31d659616ad968b409a48df
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/alpha/cpu.h
    M target/alpha/translate.c

  Log Message:
  -----------
  target/alpha: Split out alpha_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cc517f67f41a63008bdc6375249fae1b8f1c3315
      
https://github.com/qemu/qemu/commit/cc517f67f41a63008bdc6375249fae1b8f1c3315
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/alpha/cpu.c

  Log Message:
  -----------
  target/alpha: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f8a72a778625fc02425152eb73cb88298f100ac3
      
https://github.com/qemu/qemu/commit/f8a72a778625fc02425152eb73cb88298f100ac3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/tcg/helper-a64.c
    M target/arm/tcg/mte_helper.c
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/tlb_helper.c

  Log Message:
  -----------
  target/arm: Split out arm_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 70e5429273bc529c40f92d8de1716e35ab2ebae0
      
https://github.com/qemu/qemu/commit/70e5429273bc529c40f92d8de1716e35ab2ebae0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 81406d06ecc05db84e6d688e5275969dc199d4ac
      
https://github.com/qemu/qemu/commit/81406d06ecc05db84e6d688e5275969dc199d4ac
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/avr/cpu.c
    M target/avr/cpu.h

  Log Message:
  -----------
  target/avr: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d2e1d5cebe3676aaa6e2ea820c3eef1a9b6fe049
      
https://github.com/qemu/qemu/commit/d2e1d5cebe3676aaa6e2ea820c3eef1a9b6fe049
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/cris/translate.c
    M target/cris/translate_v10.c.inc

  Log Message:
  -----------
  target/cris: Cache mem_index in DisasContext

Compute this value once for each translation.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 92c1ab5d7046484eff4bf0b929f19be841c248d9
      
https://github.com/qemu/qemu/commit/92c1ab5d7046484eff4bf0b929f19be841c248d9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/cris/cpu.c

  Log Message:
  -----------
  target/cris: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 495befd4fba41cc9e072a7d2c4920d1992c0974c
      
https://github.com/qemu/qemu/commit/495befd4fba41cc9e072a7d2c4920d1992c0974c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/hppa/cpu.c
    M target/hppa/cpu.h

  Log Message:
  -----------
  target/hppa: Populate CPUClass.mmu_index

Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9f438778c90253a62ca9bf91a8c48baa78ac037f
      
https://github.com/qemu/qemu/commit/9f438778c90253a62ca9bf91a8c48baa78ac037f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  target/i386: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7619a0edced39f196b592f97af4fb5dc416c7299
      
https://github.com/qemu/qemu/commit/7619a0edced39f196b592f97af4fb5dc416c7299
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/loongarch/cpu.c
    M target/loongarch/cpu.h

  Log Message:
  -----------
  target/loongarch: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6761bdbd11202269e800ca4f2a0a03e822d18e30
      
https://github.com/qemu/qemu/commit/6761bdbd11202269e800ca4f2a0a03e822d18e30
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/loongarch/cpu.c
    M target/loongarch/cpu.h
    M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
    M target/loongarch/tcg/tlb_helper.c
    M target/loongarch/tcg/translate.c

  Log Message:
  -----------
  target/loongarch: Rename MMU_IDX_*

The expected form is MMU_FOO_IDX, not MMU_IDX_FOO.
Rename to match generic code.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 39e616ff933241f9cb4158efec07166996b7a83d
      
https://github.com/qemu/qemu/commit/39e616ff933241f9cb4158efec07166996b7a83d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/m68k/cpu.c

  Log Message:
  -----------
  target/m68k: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 19ab06b6b158a3d2885b95fda1f7f12ab7dec1f6
      
https://github.com/qemu/qemu/commit/19ab06b6b158a3d2885b95fda1f7f12ab7dec1f6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/microblaze/cpu.c
    M target/microblaze/cpu.h

  Log Message:
  -----------
  target/microblaze: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f071b8fb05ded1c82a82a147dff5af6789c8d6fc
      
https://github.com/qemu/qemu/commit/f071b8fb05ded1c82a82a147dff5af6789c8d6fc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/tcg/sysemu/tlb_helper.c

  Log Message:
  -----------
  target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill

Rather than adjust env->hflags so that the value computed
by cpu_mmu_index() changes, compute the mmu_idx that we
want directly and pass it down.

Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e7fe5ed5cb173db1dcc15edd8100186e04bf625a
      
https://github.com/qemu/qemu/commit/e7fe5ed5cb173db1dcc15edd8100186e04bf625a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/sysemu/physaddr.c
    M target/mips/tcg/msa_helper.c
    M target/mips/tcg/sysemu/cp0_helper.c
    M target/mips/tcg/sysemu/special_helper.c
    M target/mips/tcg/sysemu/tlb_helper.c

  Log Message:
  -----------
  target/mips: Split out mips_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d5bdacd4f75a7e2d8aec5c9c2b1aeec4734ac6d7
      
https://github.com/qemu/qemu/commit/d5bdacd4f75a7e2d8aec5c9c2b1aeec4734ac6d7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/mips/cpu.c

  Log Message:
  -----------
  target/mips: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b9acdc1577cab29caf338214ef431d8066e4fdf6
      
https://github.com/qemu/qemu/commit/b9acdc1577cab29caf338214ef431d8066e4fdf6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/nios2/cpu.c
    M target/nios2/cpu.h

  Log Message:
  -----------
  target/nios2: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ad933c0187e71a41dee15498bb5ab5fe24365684
      
https://github.com/qemu/qemu/commit/ad933c0187e71a41dee15498bb5ab5fe24365684
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h

  Log Message:
  -----------
  target/openrisc: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b0d4e0423c16a1b1442055d61e7c7348f4c98912
      
https://github.com/qemu/qemu/commit/b0d4e0423c16a1b1442055d61e7c7348f4c98912
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/mem_helper.c
    M target/ppc/mmu_common.c

  Log Message:
  -----------
  target/ppc: Split out ppc_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ec06218cc371d45be0bbe4883ed09cdfd764725b
      
https://github.com/qemu/qemu/commit/ec06218cc371d45be0bbe4883ed09cdfd764725b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1df3642774d1ad833c4e8a146378aabf784b8a1f
      
https://github.com/qemu/qemu/commit/1df3642774d1ad833c4e8a146378aabf784b8a1f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index

Free up the riscv_cpu_mmu_index name for other usage;
emphasize that the argument is 'env'.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 139b971ab310c9f94ecaea9f9b83c09854e85aff
      
https://github.com/qemu/qemu/commit/139b971ab310c9f94ecaea9f9b83c09854e85aff
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/op_helper.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index

Use the target-specific function name in preference
to the generic name.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 743ca7480764397d10585f3a8570cc6939f2ad27
      
https://github.com/qemu/qemu/commit/743ca7480764397d10585f3a8570cc6939f2ad27
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Populate CPUClass.mmu_index

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 857676fe3c9375f7a13c7910e08aa96633455b29
      
https://github.com/qemu/qemu/commit/857676fe3c9375f7a13c7910e08aa96633455b29
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/rx/cpu.c

  Log Message:
  -----------
  target/rx: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8b8a17a77d6facd1816161b4c6ed9c8ae99388a9
      
https://github.com/qemu/qemu/commit/8b8a17a77d6facd1816161b4c6ed9c8ae99388a9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/s390x/cpu.h
    M target/s390x/tcg/mem_helper.c

  Log Message:
  -----------
  target/s390x: Split out s390x_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fe2ee82c144d18b4924e0a90516d31f9ec1801c0
      
https://github.com/qemu/qemu/commit/fe2ee82c144d18b4924e0a90516d31f9ec1801c0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/s390x/cpu.c

  Log Message:
  -----------
  target/s390x: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b34184dc482959e81d7fab4a24460928ef25637a
      
https://github.com/qemu/qemu/commit/b34184dc482959e81d7fab4a24460928ef25637a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sh4/cpu.c
    M target/sh4/cpu.h

  Log Message:
  -----------
  target/sh4: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a98bcb73982c35fdf64c7cb6017a114342d7e911
      
https://github.com/qemu/qemu/commit/a98bcb73982c35fdf64c7cb6017a114342d7e911
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/cpu.c
    M target/sparc/cpu.h

  Log Message:
  -----------
  target/sparc: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 59e2b8740c4b70758310bb1602ecba3921862ea1
      
https://github.com/qemu/qemu/commit/59e2b8740c4b70758310bb1602ecba3921862ea1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/tricore/cpu.c

  Log Message:
  -----------
  target/tricore: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c0d85b7f449e90d3fb1dec1c54f1314153e5ae67
      
https://github.com/qemu/qemu/commit/c0d85b7f449e90d3fb1dec1c54f1314153e5ae67
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/xtensa/cpu.c

  Log Message:
  -----------
  target/xtensa: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 848e0bddb8c5fd04554ad473756e36450e4e1498
      
https://github.com/qemu/qemu/commit/848e0bddb8c5fd04554ad473756e36450e4e1498
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M include/exec/cpu-all.h
    M include/exec/cpu-common.h
    M target/alpha/cpu.h
    M target/arm/cpu.h
    M target/avr/cpu.h
    M target/cris/cpu.h
    M target/hexagon/cpu.h
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/loongarch/cpu.c
    M target/loongarch/cpu.h
    M target/m68k/cpu.h
    M target/microblaze/cpu.c
    M target/microblaze/cpu.h
    M target/mips/cpu.h
    M target/nios2/cpu.c
    M target/nios2/cpu.h
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/ppc/cpu.h
    M target/riscv/cpu.h
    M target/rx/cpu.h
    M target/s390x/cpu.h
    M target/sh4/cpu.c
    M target/sh4/cpu.h
    M target/sparc/cpu.c
    M target/sparc/cpu.h
    M target/tricore/cpu.h
    M target/xtensa/cpu.h

  Log Message:
  -----------
  include/exec: Implement cpu_mmu_index generically

For user-only mode, use MMU_USER_IDX.
For system mode, use CPUClass.mmu_index.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 451fe23c17eb3616f23d7cda8eb06b2ec2b95f97
      
https://github.com/qemu/qemu/commit/451fe23c17eb3616f23d7cda8eb06b2ec2b95f97
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_common.c.inc
    M include/exec/cpu-all.h
    M include/exec/cpu-common.h
    M semihosting/uaccess.c
    M target/cris/translate.c
    M target/hppa/mem_helper.c
    M target/hppa/op_helper.c
    M target/i386/tcg/translate.c
    M target/loongarch/tcg/tlb_helper.c
    M target/m68k/op_helper.c
    M target/microblaze/helper.c
    M target/microblaze/mmu.c
    M target/microblaze/translate.c
    M target/nios2/translate.c
    M target/openrisc/translate.c
    M target/sparc/cpu.h
    M target/sparc/ldst_helper.c
    M target/sparc/mmu_helper.c
    M target/tricore/helper.c
    M target/tricore/translate.c
    M target/xtensa/mmu_helper.c

  Log Message:
  -----------
  include/exec: Change cpu_mmu_index argument to CPUState

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 86282b1c7b166644f5fcf518ba34ae93bd9b8a4b
      
https://github.com/qemu/qemu/commit/86282b1c7b166644f5fcf518ba34ae93bd9b8a4b
  Author: Ilya Leoshkevich <iii@linux.ibm.com>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M tests/tcg/multiarch/gdbstub/prot-none.py

  Log Message:
  -----------
  tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test

The `if not probe_proc_self_mem` check never passes, because
probe_proc_self_mem is a function object, which is a truthy value.
Add parentheses in order to perform a function call.

Fixes: dc84d50a7f9b ("tests/tcg: Add the PROT_NONE gdbstub test")
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20240131220245.235993-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e45bc7e2ef1f456b165bd1cac90515406b5bbd2b
      
https://github.com/qemu/qemu/commit/e45bc7e2ef1f456b165bd1cac90515406b5bbd2b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Set vector registers call clobbered

Because there are more call clobbered registers than
call saved registers, we begin with all registers as
call clobbered and then reset those that are saved.

This was missed when we introduced the LSX support.

Cc: qemu-stable@nongnu.org
Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org>


  Commit: ecc5180400d5a0e92d8a0107550aa5c1da1fc8eb
      
https://github.com/qemu/qemu/commit/ecc5180400d5a0e92d8a0107550aa5c1da1fc8eb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY

Align the operation to the 32-byte cacheline.
Use 2 pair of i128 instead of 8 pair of i32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-2-richard.henderson@linaro.org>


  Commit: ff5c4bb0450a9d3ad2a299f7ff82b8633ae3e368
      
https://github.com/qemu/qemu/commit/ff5c4bb0450a9d3ad2a299f7ff82b8633ae3e368
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL

Align the operation to the 32-byte cacheline.
Use 2 i128 instead of 4 i64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-3-richard.henderson@linaro.org>


  Commit: a24fd37705dc396690a5ccb3bff63a70961a5413
      
https://github.com/qemu/qemu/commit/a24fd37705dc396690a5ccb3bff63a70961a5413
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Remove gen_dest_fpr_F

Replace with tcg_temp_new_i32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-4-richard.henderson@linaro.org>


  Commit: 1addfac3b84ac5f21539c6b75d7b55260c531ab2
      
https://github.com/qemu/qemu/commit/1addfac3b84ac5f21539c6b75d7b55260c531ab2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Introduce gen_{load,store}_fpr_Q

Use them for trans_FMOVq.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-5-richard.henderson@linaro.org>


  Commit: a6bc1417d9c6c1cf926d0a3e20da293365c73bd5
      
https://github.com/qemu/qemu/commit/a6bc1417d9c6c1cf926d0a3e20da293365c73bd5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Inline FNEG, FABS

These are simple bit manipulation insns.
Begin using i128 for float128.
Implement FMOVq with do_qq.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org>


  Commit: 7acf81990343de4080a722cd323db102c949da44
      
https://github.com/qemu/qemu/commit/7acf81990343de4080a722cd323db102c949da44
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for FSQRTq

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org>


  Commit: 038cd4964b0e0168338bd2f80526ab53faf793dc
      
https://github.com/qemu/qemu/commit/038cd4964b0e0168338bd2f80526ab53faf793dc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-8-richard.henderson@linaro.org>


  Commit: 468ed8231ff525898cf0359cf96b301c372f0fa8
      
https://github.com/qemu/qemu/commit/468ed8231ff525898cf0359cf96b301c372f0fa8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for FqTOs, FqTOi

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org>


  Commit: 785121b5c2d3d0d1c382fce524cf37013b55630c
      
https://github.com/qemu/qemu/commit/785121b5c2d3d0d1c382fce524cf37013b55630c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for FqTOd, FqTOx

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-10-richard.henderson@linaro.org>


  Commit: 89dd9d25d45e7131d233cdbdd438ad724bce677f
      
https://github.com/qemu/qemu/commit/89dd9d25d45e7131d233cdbdd438ad724bce677f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for FCMPq, FCMPEq

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-11-richard.henderson@linaro.org>


  Commit: 72e9c76cd3d63bfda5bd5e77c115b29033280a51
      
https://github.com/qemu/qemu/commit/72e9c76cd3d63bfda5bd5e77c115b29033280a51
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for FsTOq, FiTOq

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-12-richard.henderson@linaro.org>


  Commit: 91350849ef74a1b01dd09aaccd1eafa144628b33
      
https://github.com/qemu/qemu/commit/91350849ef74a1b01dd09aaccd1eafa144628b33
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for FdTOq, FxTOq

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-13-richard.henderson@linaro.org>


  Commit: 6d0abe22ce90b2c9675c278b00a2fea16d414c94
      
https://github.com/qemu/qemu/commit/6d0abe22ce90b2c9675c278b00a2fea16d414c94
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Use i128 for Fdmulq

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org>


  Commit: 04b17faafd57e83f9fa5ecf3c0dea1a41c545610
      
https://github.com/qemu/qemu/commit/04b17faafd57e83f9fa5ecf3c0dea1a41c545610
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/cpu.h
    M target/sparc/fop_helper.c
    M target/sparc/ldst_helper.c

  Log Message:
  -----------
  target/sparc: Remove qt0, qt1 temporaries

These are no longer used for passing data to/from helpers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-15-richard.henderson@linaro.org>


  Commit: c9475a9855f65d0b0395cc8c29f9e2bee96bea5c
      
https://github.com/qemu/qemu/commit/c9475a9855f65d0b0395cc8c29f9e2bee96bea5c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M linux-user/sparc/cpu_loop.c
    M linux-user/sparc/signal.c
    M target/sparc/cpu.c
    M target/sparc/cpu.h
    M target/sparc/fop_helper.c
    M target/sparc/gdbstub.c
    M target/sparc/helper.h
    M target/sparc/machine.c
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Introduce cpu_get_fsr, cpu_put_fsr

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org>


  Commit: 7a4e99d97670fdad0fd1da4ca7be4b00c8569364
      
https://github.com/qemu/qemu/commit/7a4e99d97670fdad0fd1da4ca7be4b00c8569364
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/cpu.c
    M target/sparc/cpu.h
    M target/sparc/fop_helper.c

  Log Message:
  -----------
  target/sparc: Split ver from env->fsr

This field is read-only.  It is easier to store it separately
and merge it only upon read.

While we're at it, use FSR_VER_SHIFT to initialize fpu_version.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-17-richard.henderson@linaro.org>


  Commit: 863920bb24afec4e2e8fabf6af265ed933c0fc41
      
https://github.com/qemu/qemu/commit/863920bb24afec4e2e8fabf6af265ed933c0fc41
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Clear cexc and ftt in do_check_ieee_exceptions

Don't do the clearing explicitly before each FPop,
rather do it as part of the rest of exception handling.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-18-richard.henderson@linaro.org>


  Commit: 4eb6645dd75bdc7516089e91f8e1ac37beef4c51
      
https://github.com/qemu/qemu/commit/4eb6645dd75bdc7516089e91f8e1ac37beef4c51
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Merge check_ieee_exceptions with FPop helpers

If an exception is to be raised, the destination fp register
should be unmodified.  The current implementation is incorrect,
in that double results will be written back before calling
gen_helper_check_ieee_exceptions, despite the placement of
gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[].

We can simplify the entire implementation by having each
FPOp helper call check_ieee_exceptions.  For the moment this
requires that all FPop helpers write to the TCG global cpu_fsr,
so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org>


  Commit: 9248367bae5dc2b83965b934157d9bfde9c5d096
      
https://github.com/qemu/qemu/commit/9248367bae5dc2b83965b934157d9bfde9c5d096
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/cpu.h
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Split cexc and ftt from env->fsr

These two fields are adjusted by all FPop insns.
Having them separate makes it easier to set without masking.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org>


  Commit: d8dc88b8cb4c55f37a94d85eccbb6ec418438f8d
      
https://github.com/qemu/qemu/commit/d8dc88b8cb4c55f37a94d85eccbb6ec418438f8d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Remove cpu_fsr

Drop this field as a tcg global, loading it explicitly in the
few places required.  This means that all FPop helpers may
once again be TCG_CALL_NO_WG.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org>


  Commit: 581628e5aa811556d46028defd98134eb38765e0
      
https://github.com/qemu/qemu/commit/581628e5aa811556d46028defd98134eb38765e0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/cpu.h
    M target/sparc/fop_helper.c
    M target/sparc/helper.h
    M target/sparc/translate.c

  Log Message:
  -----------
  target/sparc: Split fcc out of env->fsr

Represent each fcc field separately from the rest of fsr.
This vastly simplifies floating-point comparisons.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org>


  Commit: 73e095fc71dfeb8f5f767d9ac71078e562d935b0
      
https://github.com/qemu/qemu/commit/73e095fc71dfeb8f5f767d9ac71078e562d935b0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M target/sparc/cpu.h

  Log Message:
  -----------
  target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK

These macros are no longer used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-23-richard.henderson@linaro.org>


  Commit: b783e8c97ec147647b1f4ca484e0796bb1740d2d
      
https://github.com/qemu/qemu/commit/b783e8c97ec147647b1f4ca484e0796bb1740d2d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_common.c.inc
    M include/exec/cpu-all.h
    M include/exec/cpu-common.h
    M include/hw/core/cpu.h
    M linux-user/sparc/cpu_loop.c
    M linux-user/sparc/signal.c
    M semihosting/uaccess.c
    M target/alpha/cpu.c
    M target/alpha/cpu.h
    M target/alpha/translate.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/tcg/helper-a64.c
    M target/arm/tcg/mte_helper.c
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/tlb_helper.c
    M target/avr/cpu.c
    M target/avr/cpu.h
    M target/cris/cpu.c
    M target/cris/cpu.h
    M target/cris/translate.c
    M target/cris/translate_v10.c.inc
    M target/hexagon/cpu.h
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/mem_helper.c
    M target/hppa/op_helper.c
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/i386/tcg/translate.c
    M target/loongarch/cpu.c
    M target/loongarch/cpu.h
    M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
    M target/loongarch/tcg/tlb_helper.c
    M target/loongarch/tcg/translate.c
    M target/m68k/cpu.c
    M target/m68k/cpu.h
    M target/m68k/op_helper.c
    M target/microblaze/cpu.c
    M target/microblaze/cpu.h
    M target/microblaze/helper.c
    M target/microblaze/mmu.c
    M target/microblaze/translate.c
    M target/mips/cpu.c
    M target/mips/cpu.h
    M target/mips/sysemu/physaddr.c
    M target/mips/tcg/msa_helper.c
    M target/mips/tcg/sysemu/cp0_helper.c
    M target/mips/tcg/sysemu/special_helper.c
    M target/mips/tcg/sysemu/tlb_helper.c
    M target/nios2/cpu.c
    M target/nios2/cpu.h
    M target/nios2/translate.c
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/translate.c
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/mem_helper.c
    M target/ppc/mmu_common.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/op_helper.c
    M target/riscv/vector_helper.c
    M target/rx/cpu.c
    M target/rx/cpu.h
    M target/s390x/cpu.c
    M target/s390x/cpu.h
    M target/s390x/tcg/mem_helper.c
    M target/sh4/cpu.c
    M target/sh4/cpu.h
    M target/sparc/cpu.c
    M target/sparc/cpu.h
    M target/sparc/fop_helper.c
    M target/sparc/gdbstub.c
    M target/sparc/helper.h
    M target/sparc/ldst_helper.c
    M target/sparc/machine.c
    M target/sparc/mmu_helper.c
    M target/sparc/translate.c
    M target/tricore/cpu.c
    M target/tricore/cpu.h
    M target/tricore/helper.c
    M target/tricore/translate.c
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/mmu_helper.c
    M tcg/loongarch64/tcg-target.c.inc
    M tests/tcg/multiarch/gdbstub/prot-none.py

  Log Message:
  -----------
  Merge tag 'pull-tcg-20240202' of https://gitlab.com/rth7680/qemu into staging

tests/tcg: Fix multiarch/gdbstub/prot-none.py
hw/core: Convert cpu_mmu_index to a CPUClass hook
tcg/loongarch64: Set vector registers call clobbered
target/sparc: floating-point cleanup

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmW8gj4dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9fwgf+OsqAtW6f7dXFHxHa
# qblY7mL6TIBDTn//aMWrRHP3NPlNn9BihC6E1RD2TPsnACGlDZPuG79Nm1LO9PJJ
# IErPrTRWiUAqekApxmlyhfBwQ5+qNhooU++wP7O1IRoQnNDqSq9dOk7ayyCDA0iP
# QHpEpaFOIqX2MvxmE+NAoGvL2pi12YPjhhItg2bjAFmW7Np3tSMeNxICdpCM5fij
# +7lGAR3rLy2X0+u/VYaFu9Rrz96kSI9hYbkGC4nePABb0Dk/fgIbQU3jRXGse41R
# NdkC3EQcTKqqN0iXe/W3NQec62ch8p0f1WLpD10R1/AKECUUfYsvkN7WbqOwLio5
# JYDcJg==
# =x9I9
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 02 Feb 2024 05:48:46 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240202' of https://gitlab.com/rth7680/qemu: (57 commits)
  target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK
  target/sparc: Split fcc out of env->fsr
  target/sparc: Remove cpu_fsr
  target/sparc: Split cexc and ftt from env->fsr
  target/sparc: Merge check_ieee_exceptions with FPop helpers
  target/sparc: Clear cexc and ftt in do_check_ieee_exceptions
  target/sparc: Split ver from env->fsr
  target/sparc: Introduce cpu_get_fsr, cpu_put_fsr
  target/sparc: Remove qt0, qt1 temporaries
  target/sparc: Use i128 for Fdmulq
  target/sparc: Use i128 for FdTOq, FxTOq
  target/sparc: Use i128 for FsTOq, FiTOq
  target/sparc: Use i128 for FCMPq, FCMPEq
  target/sparc: Use i128 for FqTOd, FqTOx
  target/sparc: Use i128 for FqTOs, FqTOi
  target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq
  target/sparc: Use i128 for FSQRTq
  target/sparc: Inline FNEG, FABS
  target/sparc: Introduce gen_{load,store}_fpr_Q
  target/sparc: Remove gen_dest_fpr_F
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#       target/loongarch/tcg/tlb_helper.c


Compare: https://github.com/qemu/qemu/compare/17e0f9d6bd89...b783e8c97ec1
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