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[Qemu-commits] [qemu/qemu] d95f26: docs/devel/docs: Document .hx file sy
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] d95f26: docs/devel/docs: Document .hx file syntax |
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Date: |
Tue, 16 Jan 2024 08:40:12 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: d95f260aee3ea1b12779cdede7456480ea9ea3d1
https://github.com/qemu/qemu/commit/d95f260aee3ea1b12779cdede7456480ea9ea3d1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M MAINTAINERS
A docs/devel/docs.rst
M docs/devel/index-build.rst
M hmp-commands-info.hx
M hmp-commands.hx
M qemu-img-cmds.hx
M qemu-options.hx
Log Message:
-----------
docs/devel/docs: Document .hx file syntax
We don't currently document the syntax of .hx files anywhere
except in a few comments at the top of individual .hx files.
We don't even have somewhere in the developer docs where we
could do this.
Add a new files docs/devel/docs.rst which can be a place to
document how our docs build process works. For the moment,
put in only a brief introductory paragraph and the documentation
of the .hx files. We could later add to this file by for
example describing how the QAPI-schema-to-docs process works,
or anything else that developers might need to know about
how to add documentation.
Make the .hx files refer to this doc file, and clean
up their header comments to be more accurate for the
usage in each file and less cut-n-pasted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Message-id: 20231212162313.1742462-1-peter.maydell@linaro.org
Commit: 71e269fb7bd14b5e4b055b6978a4ab193e11ee8e
https://github.com/qemu/qemu/commit/71e269fb7bd14b5e4b055b6978a4ab193e11ee8e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: arm_pamax() no longer needs to do feature propagation
In arm_pamax(), we need to cope with the virt board calling this
function on a CPU object which has been inited but not realize.
We used to do propagation of feature-flag implications (such as
"V7VE implies LPAE") at realize, so we have some code in arm_pamax()
which manually checks for both V7VE and LPAE feature flags.
In commit b8f7959f28c4f36 we moved the feature propagation for
almost all features from realize to post-init. That means that
now when the virt board calls arm_pamax(), the feature propagation
has been done. So we can drop the manual propagation handling
and check only for the feature we actually care about, which
is ARM_FEATURE_LPAE.
Retain the comment that the virt board is calling this function
with a not completely realized CPU object, because that is a
potential beartrap for later changes which is worth calling out.
(Note that b8f7959f28c4f36 actually fixed a bug in the arm_pamax()
handling: arm_pamax() was missing a check for ARM_FEATURE_V8, so it
incorrectly thought that the qemu-system-arm 'max' CPU did not have
LPAE and turned off 'highmem' support in the virt board. Following
b8f7959f28c4f36 qemu-system-arm 'max' is treated the same as
'cortex-a15' and other v7 LPAE CPUs, because the generic feature
propagation code does correctly propagate V8 -> V7VE -> LPAE.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240109143804.1118307-1-peter.maydell@linaro.org
Commit: 8cf1da729170b7cc47ebaca46912a4f37675dc95
https://github.com/qemu/qemu/commit/8cf1da729170b7cc47ebaca46912a4f37675dc95
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M docs/system/arm/virt.rst
Log Message:
-----------
docs/system/arm/virt.rst: Improve 'highmem' option docs
Improve the 'highmem' option docs to note that by default we assume
that a 32-bit kernel on an LPAE-capable CPU has LPAE enabled, and
what the consequences are.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20240109170834.1387457-1-peter.maydell@linaro.org
Commit: c9948fdd023dd2031d868c8e26f387e6705c918c
https://github.com/qemu/qemu/commit/c9948fdd023dd2031d868c8e26f387e6705c918c
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M docs/system/arm/b-l475e-iot01a.rst
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/stm32l4x5_exti.c
M hw/misc/trace-events
A include/hw/misc/stm32l4x5_exti.h
Log Message:
-----------
hw/misc: Implement STM32L4x5 EXTI
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates
more than 32 event/interrupt requests and thus uses more registers
than STM32F4xx EXTI which generates 23 event/interrupt requests.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240109160658.311932-2-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 52671f69f7a4cdc235903fd9005ac4b2e4770593
https://github.com/qemu/qemu/commit/52671f69f7a4cdc235903fd9005ac4b2e4770593
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/arm/Kconfig
M hw/arm/stm32l4x5_soc.c
M include/hw/arm/stm32l4x5_soc.h
Log Message:
-----------
hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240109160658.311932-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4cb445717eed79b3b1db0bfe5c4ccf838f895751
https://github.com/qemu/qemu/commit/4cb445717eed79b3b1db0bfe5c4ccf838f895751
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_exti-test.c
Log Message:
-----------
tests/qtest: Add STM32L4x5 EXTI QTest testcase
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240109160658.311932-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 20936684b6dd02eec35591661553a57f3515cf5b
https://github.com/qemu/qemu/commit/20936684b6dd02eec35591661553a57f3515cf5b
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M docs/system/arm/b-l475e-iot01a.rst
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/stm32l4x5_syscfg.c
M hw/misc/trace-events
A include/hw/misc/stm32l4x5_syscfg.h
Log Message:
-----------
hw/misc: Implement STM32L4x5 SYSCFG
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240109194438.70934-2-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7dfe2312e4653dd796dc2731668ad65237563e39
https://github.com/qemu/qemu/commit/7dfe2312e4653dd796dc2731668ad65237563e39
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/arm/Kconfig
M hw/arm/stm32l4x5_soc.c
M include/hw/arm/stm32l4x5_soc.h
Log Message:
-----------
hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC
The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO
device will be implemented, its output GPIOs will be connected to the
SYSCFG input GPIOs.
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240109194438.70934-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a96bff6157ca89bbf7fc7aabd670fa4072c922cd
https://github.com/qemu/qemu/commit/a96bff6157ca89bbf7fc7aabd670fa4072c922cd
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_syscfg-test.c
Log Message:
-----------
tests/qtest: Add STM32L4x5 SYSCFG QTest testcase
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240109194438.70934-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d322429a5038f70a82f4e64f0f3a6d728fd04255
https://github.com/qemu/qemu/commit/d322429a5038f70a82f4e64f0f3a6d728fd04255
Author: Hao Wu <wuhaotsh@google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/misc/meson.build
A hw/misc/npcm7xx_pci_mbox.c
M hw/misc/trace-events
A include/hw/misc/npcm7xx_pci_mbox.h
Log Message:
-----------
hw/misc: Add Nuvoton's PCI Mailbox Module
The PCI Mailbox Module is a high-bandwidth communcation module
between a Nuvoton BMC and CPU. It features 16KB RAM that are both
accessible by the BMC and core CPU. and supports interrupt for
both sides.
This patch implements the BMC side of the PCI mailbox module.
Communication with the core CPU is emulated via a chardev and
will be in a follow-up patch.
Change-Id: Iaca22f81c4526927d437aa367079ed038faf43f2
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-2-nabihestefan@google.com
[PMM: Moved some changes that should have been in the following commit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 981b2c6d7f9216337177315f2205fc6474cd786e
https://github.com/qemu/qemu/commit/981b2c6d7f9216337177315f2205fc6474cd786e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M docs/system/arm/nuvoton.rst
M hw/arm/npcm7xx.c
M include/hw/arm/npcm7xx.h
Log Message:
-----------
hw/arm: Add PCI mailbox module to Nuvoton SoC
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-3-nabihestefan@google.com
[PMM: moved some changes incorrectly in previous patch into this one]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 02059169943826d3278db64bbd9a20a50c4415a3
https://github.com/qemu/qemu/commit/02059169943826d3278db64bbd9a20a50c4415a3
Author: Hao Wu <wuhaotsh@google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/npcm7xx_pci_mbox-test.c
Log Message:
-----------
hw/misc: Add qtest for NPCM7xx PCI Mailbox
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-4-nabihestefan@google.com
[PMM: avoid in_port_t type as it is not present on Windows]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 19b661382dfd5522d06e406b4a7e531fcec3fcc3
https://github.com/qemu/qemu/commit/19b661382dfd5522d06e406b4a7e531fcec3fcc3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/net/meson.build
A hw/net/npcm_gmac.c
M hw/net/trace-events
A include/hw/net/npcm_gmac.h
Log Message:
-----------
hw/net: Add NPCMXXX GMAC device
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Change-Id: If71c6d486b95edcccba109ba454870714d7e0940
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-5-nabihestefan@google.com
[PMM: Squashed another patch into this one to avoid compilation failure]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f9eddc7eae3d0683b893e7398ec9c425e229deaa
https://github.com/qemu/qemu/commit/f9eddc7eae3d0683b893e7398ec9c425e229deaa
Author: Hao Wu <wuhaotsh@google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/arm/npcm7xx.c
M include/hw/arm/npcm7xx.h
Log Message:
-----------
hw/arm: Add GMAC devices to NPCM7XX SoC
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-6-nabihestefan@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dbbed853a29cb6de77935881f4c8fa5f64ed295c
https://github.com/qemu/qemu/commit/dbbed853a29cb6de77935881f4c8fa5f64ed295c
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/npcm_gmac-test.c
Log Message:
-----------
tests/qtest: Creating qtest for GMAC Module
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-7-nabihestefan@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 71cce75f1113ddd8586c2b17f5e197866e1c1fa2
https://github.com/qemu/qemu/commit/71cce75f1113ddd8586c2b17f5e197866e1c1fa2
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/net/npcm_gmac.c
M hw/net/trace-events
Log Message:
-----------
hw/net: GMAC Rx Implementation
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP NIC device.
When RX descriptor list is full, it returns a DMA_STATUS for software
to handle it. But there's no way to indicate the software has
handled all RX descriptors and the whole pipeline stalls.
We do something similar to NPCM7XX EMC to handle this case.
1. Return packet size when RX descriptor is full, effectively
dropping these packets in such a case.
2. When software clears RX descriptor full bit, continue receiving
further packets by flushing QEMU packet queue.
Added relevant trace-events
Change-Id: I132aa254a94cda1a586aba2ea33bbfc74ecdb831
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-9-nabihestefan@google.com
[PMM: moved a couple of functions into the following patch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d42cf41dea59f3df92dd442542184edfff14697f
https://github.com/qemu/qemu/commit/d42cf41dea59f3df92dd442542184edfff14697f
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/net/npcm_gmac.c
M hw/net/trace-events
Log Message:
-----------
hw/net: GMAC Tx Implementation
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
Added relevant trace-events
Change-Id: Icf14f9fcc6cc7808a41acd872bca67c9832087e6
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-10-nabihestefan@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 935d5b2d53be03c6d9cbc99d0b70445200d10b0d
https://github.com/qemu/qemu/commit/935d5b2d53be03c6d9cbc99d0b70445200d10b0d
Author: Nabih Estefan Diaz <nabihestefan@google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M tests/qtest/npcm_gmac-test.c
Log Message:
-----------
tests/qtest: Adding PCS Module test to GMAC Qtest
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240110234232.4116804-11-nabihestefan@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 60b2fd1a76475413f9a5a6babf1c8c4bb86891e3
https://github.com/qemu/qemu/commit/60b2fd1a76475413f9a5a6babf1c8c4bb86891e3
Author: Samuel Tardieu <sam@rfc1149.net>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/timer/trace-events
Log Message:
-----------
hw/timer: fix systick trace message
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-id: 20240109184508.3189599-1-sam@rfc1149.net
Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8869bdbb29882edd4fd32baf6b4aa0dd4d927368
https://github.com/qemu/qemu/commit/8869bdbb29882edd4fd32baf6b4aa0dd4d927368
Author: Gavin Shan <gshan@redhat.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Consolidate valid CPU types
It's found that some of the CPU type names in the array of valid
CPU types are invalid because their corresponding classes aren't
registered, as reported by Peter Maydell.
[gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu cortex-a9
qemu-system-arm: Invalid CPU model: cortex-a9
The valid models are: cortex-a7, cortex-a15, (null), (null), (null),
(null), (null), (null), (null), (null), (null), (null), (null), max
Fix it by consolidating the array of valid CPU types. After it's
applied, we have the following output when TCG is enabled.
[gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu cortex-a9
qemu-system-arm: Invalid CPU model: cortex-a9
The valid models are: cortex-a7, cortex-a15, max
[gshan@gshan build]$ ./qemu-system-aarch64 -machine virt -cpu cortex-a9
qemu-system-aarch64: Invalid CPU model: cortex-a9
The valid models are: cortex-a7, cortex-a15, cortex-a35, cortex-a55,
cortex-a72, cortex-a76, cortex-a710, a64fx, neoverse-n1, neoverse-v1,
neoverse-n2, cortex-a53, cortex-a57, max
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2084
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20240111051054.83304-1-gshan@redhat.com
Fixes: fa8c617791 ("hw/arm/virt: Check CPU type in machine_run_board_init()")
Signed-off-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7ec39730a9cc443c752d4cad2bf1c00467551ef5
https://github.com/qemu/qemu/commit/7ec39730a9cc443c752d4cad2bf1c00467551ef5
Author: Anastasia Belova <abelova@astralinux.ru>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M include/hw/elf_ops.h
Log Message:
-----------
load_elf: fix iterator's type for elf file processing
j is used while loading an ELF file to byteswap segments'
data. If data is larger than 2GB an overflow may happen.
So j should be elf_word.
This commit fixes a minor bug: it's unlikely anybody is trying to
load ELF files with 2GB+ segments for wrong-endianness targets,
but if they did, it wouldn't work correctly.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: qemu-stable@nongnu.org
Fixes: 7ef295ea5b ("loader: Add data swap option to load-elf")
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ff7707ae1b73c0526878315f150c049727eabe23
https://github.com/qemu/qemu/commit/ff7707ae1b73c0526878315f150c049727eabe23
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M hw/riscv/boot.c
Log Message:
-----------
hw/riscv: Use misa_mxl instead of misa_mxl_max
The effective MXL value matters when booting.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-23-alex.bennee@linaro.org>
Message-Id: <20231213-riscv-v7-1-a760156a337f@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: bd6d9730355ec7ceacd60697e74c1bd625f3f756
https://github.com/qemu/qemu/commit/bd6d9730355ec7ceacd60697e74c1bd625f3f756
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Remove misa_mxl validation
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20240103173349.398526-24-alex.bennee@linaro.org>
Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 13b5ebd3d76afc0ace5cbb95055bbf86e79c6d06
https://github.com/qemu/qemu/commit/13b5ebd3d76afc0ace5cbb95055bbf86e79c6d06
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Move misa_mxl_max to class
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-25-alex.bennee@linaro.org>
Message-Id: <20231213-riscv-v7-3-a760156a337f@daynix.com>
[AJB: fixed merge conflicts]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 623a92a51810242ca2bd7558be4e46d642053180
https://github.com/qemu/qemu/commit/623a92a51810242ca2bd7558be4e46d642053180
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Validate misa_mxl_max only once
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-26-alex.bennee@linaro.org>
Message-Id: <20231213-riscv-v7-4-a760156a337f@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0fd23101fe987a2599ca6b21316cc9056ece60c4
https://github.com/qemu/qemu/commit/0fd23101fe987a2599ca6b21316cc9056ece60c4
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Use GDBFeature for dynamic XML
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240103173349.398526-27-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-1-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 3ef5eb582d9b5305b793546b3fc056ccf32f3212
https://github.com/qemu/qemu/commit/3ef5eb582d9b5305b793546b3fc056ccf32f3212
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
Log Message:
-----------
target/ppc: Use GDBFeature for dynamic XML
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240103173349.398526-28-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-2-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 788688e0bf24b998a11d3eb61195b7edf9117668
https://github.com/qemu/qemu/commit/788688e0bf24b998a11d3eb61195b7edf9117668
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: Use GDBFeature for dynamic XML
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-29-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-3-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 509a922c2e0214a7641b225904b479aa84b8c7a2
https://github.com/qemu/qemu/commit/509a922c2e0214a7641b225904b479aa84b8c7a2
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
M target/arm/gdbstub.c
M target/hexagon/cpu.c
M target/loongarch/gdbstub.c
M target/m68k/helper.c
M target/microblaze/cpu.c
M target/ppc/gdbstub.c
M target/riscv/gdbstub.c
M target/s390x/gdbstub.c
Log Message:
-----------
gdbstub: Use GDBFeature for gdb_register_coprocessor
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-30-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-4-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 165df5cfc0529ad688a87137134b1afa3410ef45
https://github.com/qemu/qemu/commit/165df5cfc0529ad688a87137134b1afa3410ef45
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M gdbstub/gdbstub.c
Log Message:
-----------
gdbstub: Use GDBFeature for GDBRegisterState
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240103173349.398526-31-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-5-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 93f7969d25fd23842fb469b02545c09bd57c13e5
https://github.com/qemu/qemu/commit/93f7969d25fd23842fb469b02545c09bd57c13e5
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
M target/hexagon/gdbstub.c
M target/hexagon/internal.h
M target/loongarch/gdbstub.c
M target/m68k/helper.c
M target/microblaze/cpu.h
M target/microblaze/gdbstub.c
M target/ppc/gdbstub.c
M target/riscv/gdbstub.c
M target/s390x/gdbstub.c
Log Message:
-----------
gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-32-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-6-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: c6c2e8cfeb617f9bdbf5e88088b8848447a5a5a4
https://github.com/qemu/qemu/commit/c6c2e8cfeb617f9bdbf5e88088b8848447a5a5a4
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M gdbstub/gdbstub.c
M hw/core/cpu-common.c
M include/exec/gdbstub.h
Log Message:
-----------
gdbstub: Simplify XML lookup
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-33-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-7-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 4053bd64ae5b5fe133c57244436203845a6b19f9
https://github.com/qemu/qemu/commit/4053bd64ae5b5fe133c57244436203845a6b19f9
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/hw/core/cpu.h
M target/arm/cpu.c
M target/arm/cpu64.c
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
Log Message:
-----------
gdbstub: Infer number of core registers from XML
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-34-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-8-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 59944d36d84dab6cca15fffe6574af824793076a
https://github.com/qemu/qemu/commit/59944d36d84dab6cca15fffe6574af824793076a
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M include/hw/core/cpu.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
M target/riscv/cpu.c
Log Message:
-----------
hw/core/cpu: Remove gdb_get_dynamic_xml member
This function is no longer used.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240103173349.398526-35-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-9-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: e13a50eff7e5572dffaa49b13461c4ff842016b1
https://github.com/qemu/qemu/commit/e13a50eff7e5572dffaa49b13461c4ff842016b1
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
M scripts/feature_to_c.py
M target/riscv/gdbstub.c
Log Message:
-----------
gdbstub: Add members to identify registers to GDBFeature
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-36-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-10-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: e13b39e7d283de653f28896076059b934bf8d780
https://github.com/qemu/qemu/commit/e13b39e7d283de653f28896076059b934bf8d780
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M accel/tcg/plugin-gen.c
M accel/tcg/plugin-helpers.h
M include/qemu/plugin.h
M plugins/api.c
Log Message:
-----------
plugins: Use different helpers when reading registers
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20240103173349.398526-37-alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-12-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cfae0537049d10e84a01cf9ce3e2d3833fd8e92d
https://github.com/qemu/qemu/commit/cfae0537049d10e84a01cf9ce3e2d3833fd8e92d
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest/meson.build: Bump the boot-serial-test timeout to 4 minutes
When running with TCI, the boot-serial-test can take longer than 3 minutes:
https://gitlab.com/qemu-project/qemu/-/jobs/5890481086#L4774
Bump the timeout to 4 minutes to avoid CI failures here.
Message-ID: <20240115071146.31213-1-thuth@redhat.com>
Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d9e2da0ccc5b636afc632ba9cb95d83885e2d8dc
https://github.com/qemu/qemu/commit/d9e2da0ccc5b636afc632ba9cb95d83885e2d8dc
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M tests/qtest/npcm7xx_watchdog_timer-test.c
Log Message:
-----------
tests/qtest/npcm7xx_watchdog_timer: Only test the corner cases by default
The test_prescaler() part in the npcm7xx_watchdog_timer test is quite
repetitive, testing all possible combinations of the WTCLK and WTIS
bitfields. Since each test spins up a new instance of QEMU, this is
rather an expensive test, especially on loaded host systems.
For the normal quick test mode, it should be sufficient to test the
corner settings of these fields (i.e. 0 and 3), so we can speed up
this test in the default mode quite a bit.
Message-ID: <20240115070223.30178-1-thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2d1f10229adde680234b8c975a4306b697c3b505
https://github.com/qemu/qemu/commit/2d1f10229adde680234b8c975a4306b697c3b505
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M tests/qtest/meson.build
Log Message:
-----------
qtest: Bump npcm7xx_watchdog_timer-test timeout to 2 minutes
The npcm7xx_watchdog_timer-test can take more than 60 seconds in
SPEED=slow mode on a loaded host system.
Bumping to 2 minutes will give more headroom.
Message-ID: <20240112164717.1063954-1-thuth@redhat.com>
Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 043eaa0f0c8618382b2dba2f2e4fe762215b2e29
https://github.com/qemu/qemu/commit/043eaa0f0c8618382b2dba2f2e4fe762215b2e29
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M meson.build
Log Message:
-----------
meson: mitigate against ROP exploits with -fzero-call-used-regs
To quote wikipedia:
"Return-oriented programming (ROP) is a computer security exploit
technique that allows an attacker to execute code in the presence
of security defenses such as executable space protection and code
signing.
In this technique, an attacker gains control of the call stack to
hijack program control flow and then executes carefully chosen
machine instruction sequences that are already present in the
machine's memory, called "gadgets". Each gadget typically ends in
a return instruction and is located in a subroutine within the
existing program and/or shared library code. Chained together,
these gadgets allow an attacker to perform arbitrary operations
on a machine employing defenses that thwart simpler attacks."
QEMU is by no means perfect with an ever growing set of CVEs from
flawed hardware device emulation, which could potentially be
exploited using ROP techniques.
Since GCC 11 there has been a compiler option that can mitigate
against this exploit technique:
-fzero-call-user-regs
To understand it refer to these two resources:
https://www.jerkeby.se/newsletter/posts/rop-reduction-zero-call-user-regs/
https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552262.html
I used two programs to scan qemu-system-x86_64 for ROP gadgets:
https://github.com/0vercl0k/rp
https://github.com/JonathanSalwan/ROPgadget
When asked to find 8 byte gadgets, the 'rp' tool reports:
A total of 440278 gadgets found.
You decided to keep only the unique ones, 156143 unique gadgets found.
While the ROPgadget tool reports:
Unique gadgets found: 353122
With the --ropchain argument, the latter attempts to use the found
gadgets to product a chain that can execute arbitrary syscalls. With
current QEMU it succeeds in this task, which is an undesirable
situation.
With QEMU modified to use -fzero-call-user-regs=used-gpr the 'rp' tool
reports
A total of 528991 gadgets found.
You decided to keep only the unique ones, 121128 unique gadgets found.
This is 22% fewer unique gadgets
While the ROPgadget tool reports:
Unique gadgets found: 328605
This is 7% fewer unique gadgets. Crucially though, despite this more
modest reduction, the ROPgadget tool is no longer able to identify a
chain of gadgets for executing arbitrary syscalls. It fails at the
very first step, unable to find gadgets for populating registers for
a future syscall. Having said that, more advanced tools do still
manage to put together a viable ROP chain.
Also this only takes into account QEMU code. QEMU links to many 3rd
party shared libraries and ideally all of them would be compiled with
this same hardening. That becomes a distro policy question though.
In terms of performance impact, TCG was used as an evaluation test
case. We're not interested in protecting TCG since it isn't designed
to provide a security barrier, but it is performance sensitive code,
so useful as a guide to how other areas of QEMU might be impacted.
With the -fzero-call-user-regs=used-gpr argument present, using the
real world test of booting a linux kernel and having init immediately
poweroff, there is a ~1% slow down in performance under TCG. The QEMU
binary size also grows by approximately 1%.
By comparison, using the more aggressive -fzero-call-user-regs=all,
results in a slowdown of over 25% in TCG, which is clearly not an
acceptable impact, and a binary size increase of 5%.
Considering that 'used-gpr' successfully stopped ROPgadget assembling
a chain, this more targeted protection is a justifiable hardening
/ performance tradeoff.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com>
Message-ID: <20240103123414.2401208-2-berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 7ff9ff039380008952c6fd32011dd2a4d5666906
https://github.com/qemu/qemu/commit/7ff9ff039380008952c6fd32011dd2a4d5666906
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M meson.build
Log Message:
-----------
meson: mitigate against use of uninitialize stack for exploits
When variables are used without being initialized, there is potential
to take advantage of data that was pre-existing on the stack from an
earlier call, to drive an exploit.
It is good practice to always initialize variables, and the compiler
can warn about flaws when -Wuninitialized is present. This warning,
however, is by no means foolproof with its output varying depending
on compiler version and which optimizations are enabled.
The -ftrivial-auto-var-init option can be used to tell the compiler
to always initialize all variables. This increases the security and
predictability of the program, closing off certain attack vectors,
reducing the risk of unsafe memory disclosure.
While the option takes several possible values, using 'zero' is
considered to be the option that is likely to lead to semantically
correct or safe behaviour[1]. eg sizes/indexes are not likely to
lead to out-of-bounds accesses when initialized to zero. Pointers
are less likely to point something useful if initialized to zero.
Even with -ftrivial-auto-var-init=zero set, GCC will still issue
warnings with -Wuninitialized if it discovers a problem, so we are
not loosing diagnostics for developers, just hardening runtime
behaviour and making QEMU behave more predictably in case of hitting
bad codepaths.
[1] https://lists.llvm.org/pipermail/cfe-dev/2020-April/065221.html
Signed-off-by: "Daniel P. Berrangé" <berrange@redhat.com>
Message-ID: <20240103123414.2401208-3-berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2c0ca4b9c9c40670834e134cff188a59dd49b7c7
https://github.com/qemu/qemu/commit/2c0ca4b9c9c40670834e134cff188a59dd49b7c7
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M gdbstub/gdbstub.c
M include/exec/gdbstub.h
Log Message:
-----------
gdbstub: expose api to find registers
Expose an internal API to QEMU to return all the registers for a vCPU.
The list containing the details required to called gdb_read_register().
Based-on: <20231025093128.33116-15-akihiko.odaki@daynix.com>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-38-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 58aaf493496e7e09e4fff5f8da4b647cf663c91b
https://github.com/qemu/qemu/commit/58aaf493496e7e09e4fff5f8da4b647cf663c91b
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M include/qemu/qemu-plugin.h
M plugins/api.c
M plugins/qemu-plugins.symbols
Log Message:
-----------
plugins: add an API to read registers
We can only request a list of registers once the vCPU has been
initialised so the user needs to use either call the get function on
vCPU initialisation or during the translation phase.
We don't expose the reg number to the plugin instead hiding it behind
an opaque handle. This allows for a bit of future proofing should the
internals need to be changed while also being hashed against the
CPUClass so we can handle different register sets per-vCPU in
hetrogenous situations.
Having an internal state within the plugins also allows us to expand
the interface in future (for example providing callbacks on register
change if the translator can track changes).
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org>
Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Commit: 5377db21f7fa53160c1b1a99fd3834a60009253f
https://github.com/qemu/qemu/commit/5377db21f7fa53160c1b1a99fd3834a60009253f
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M contrib/plugins/execlog.c
Log Message:
-----------
contrib/plugins: fix imatch
We can't directly save the ephemeral imatch from argv as that memory
will get recycled.
Message-Id: <20240103173349.398526-40-alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: c004142e80aaef25d903e9f2d7781d1bbcf20c8d
https://github.com/qemu/qemu/commit/c004142e80aaef25d903e9f2d7781d1bbcf20c8d
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M contrib/plugins/execlog.c
M docs/devel/tcg-plugins.rst
Log Message:
-----------
contrib/plugins: extend execlog to track register changes
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions which mention
registers we are interested in tracking.
Example usage:
./qemu-aarch64 -D plugin.log -d plugin \
-cpu max,sve256=on \
-plugin contrib/plugins/libexeclog.so,reg=sp,reg=z\* \
./tests/tcg/aarch64-linux-user/sha512-sve
will display in the execlog any changes to the stack pointer (sp) and
the SVE Z registers.
Message-Id: <20240103173349.398526-41-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Based-On: <20231025093128.33116-19-akihiko.odaki@daynix.com>
Commit: c07e24954478b9c6d265610a10fc5646d8030a8f
https://github.com/qemu/qemu/commit/c07e24954478b9c6d265610a10fc5646d8030a8f
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M contrib/plugins/execlog.c
M docs/devel/tcg-plugins.rst
Log Message:
-----------
contrib/plugins: optimise the register value tracking
This adds an additional flag which attempts to optimise the register
tracking by only instrumenting instructions which are likely to change
its value. This relies on the disassembler showing up the register
names in disassembly so is only enabled when asked for.
Message-Id: <20240103173349.398526-42-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: b0bd631c1045361d4512d490e2daca2956aa94a4
https://github.com/qemu/qemu/commit/b0bd631c1045361d4512d490e2daca2956aa94a4
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M docs/devel/tcg-plugins.rst
Log Message:
-----------
docs/devel: lift example and plugin API sections up
This makes them a bit more visible in the TCG emulation menu rather
than hiding them away bellow the ToC limit.
Message-Id: <20240103173349.398526-43-alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 87bed6910aa0d0942244b5eedee60b4f8b162c05
https://github.com/qemu/qemu/commit/87bed6910aa0d0942244b5eedee60b4f8b162c05
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M docs/devel/tcg-plugins.rst
Log Message:
-----------
docs/devel: document some plugin assumptions
While we attempt to hide implementation details from the plugin we
shouldn't be totally obtuse. Let the user know what they can and can't
expect with the various instrumentation options.
Message-Id: <20240103173349.398526-44-alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 7d9d82f351c4017dce9729fd27dcd1d79602afca
https://github.com/qemu/qemu/commit/7d9d82f351c4017dce9729fd27dcd1d79602afca
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M meson.build
M tests/qtest/meson.build
M tests/qtest/npcm7xx_watchdog_timer-test.c
Log Message:
-----------
Merge tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu into
staging
* Improve the timeouts for some problematic qtests
* Enable some ROP mitigation compiler switches
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# gpg: Signature made Tue 16 Jan 2024 07:45:57 GMT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2024-01-16' of https://gitlab.com/thuth/qemu:
meson: mitigate against use of uninitialize stack for exploits
meson: mitigate against ROP exploits with -fzero-call-used-regs
qtest: Bump npcm7xx_watchdog_timer-test timeout to 2 minutes
tests/qtest/npcm7xx_watchdog_timer: Only test the corner cases by default
tests/qtest/meson.build: Bump the boot-serial-test timeout to 4 minutes
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d1b244225b2ed9cc74b98d5bcfc02ac40143132d
https://github.com/qemu/qemu/commit/d1b244225b2ed9cc74b98d5bcfc02ac40143132d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M accel/tcg/plugin-gen.c
M accel/tcg/plugin-helpers.h
M contrib/plugins/execlog.c
M docs/devel/tcg-plugins.rst
M gdbstub/gdbstub.c
M hw/core/cpu-common.c
M hw/riscv/boot.c
M include/exec/gdbstub.h
M include/hw/core/cpu.h
M include/qemu/plugin.h
M include/qemu/qemu-plugin.h
M plugins/api.c
M plugins/qemu-plugins.symbols
M scripts/feature_to_c.py
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hexagon/gdbstub.c
M target/hexagon/internal.h
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/loongarch/gdbstub.c
M target/m68k/cpu.c
M target/m68k/helper.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/gdbstub.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/gdbstub.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/gdbstub.c
Log Message:
-----------
Merge tag 'pull-registers-for-plugins-160124-2' of
https://gitlab.com/stsquad/qemu into staging
read-only register access for plugins:
- move misa_mxl to CPU class for riscv
- use GDBFeature for arm XML
- use GDBFeature for ppc XML
- use GDBFeature for riscv XML
- unify gdb code to use GDBFeature
- move dynamic XML generation to core GDB code
- provide introspection APIs for rest of QEMU
- expose a plugin API to access registers
- fix memory re-use in execlog
- extend execlog to track registers
- optimise instrumentation based on disassembly
- tweak API docs and expand on assumptions
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# gpg: Signature made Tue 16 Jan 2024 10:35:27 GMT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key)
<alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-registers-for-plugins-160124-2' of https://gitlab.com/stsquad/qemu:
(22 commits)
docs/devel: document some plugin assumptions
docs/devel: lift example and plugin API sections up
contrib/plugins: optimise the register value tracking
contrib/plugins: extend execlog to track register changes
contrib/plugins: fix imatch
plugins: add an API to read registers
gdbstub: expose api to find registers
plugins: Use different helpers when reading registers
gdbstub: Add members to identify registers to GDBFeature
hw/core/cpu: Remove gdb_get_dynamic_xml member
gdbstub: Infer number of core registers from XML
gdbstub: Simplify XML lookup
gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb
gdbstub: Use GDBFeature for GDBRegisterState
gdbstub: Use GDBFeature for gdb_register_coprocessor
target/riscv: Use GDBFeature for dynamic XML
target/ppc: Use GDBFeature for dynamic XML
target/arm: Use GDBFeature for dynamic XML
target/riscv: Validate misa_mxl_max only once
target/riscv: Move misa_mxl_max to class
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9c693df15f24d8a742de204222fca3abb6b4c827
https://github.com/qemu/qemu/commit/9c693df15f24d8a742de204222fca3abb6b4c827
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M MAINTAINERS
A docs/devel/docs.rst
M docs/devel/index-build.rst
M docs/system/arm/b-l475e-iot01a.rst
M docs/system/arm/nuvoton.rst
M docs/system/arm/virt.rst
M hmp-commands-info.hx
M hmp-commands.hx
M hw/arm/Kconfig
M hw/arm/npcm7xx.c
M hw/arm/stm32l4x5_soc.c
M hw/arm/virt.c
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/npcm7xx_pci_mbox.c
A hw/misc/stm32l4x5_exti.c
A hw/misc/stm32l4x5_syscfg.c
M hw/misc/trace-events
M hw/net/meson.build
A hw/net/npcm_gmac.c
M hw/net/trace-events
M hw/timer/trace-events
M include/hw/arm/npcm7xx.h
M include/hw/arm/stm32l4x5_soc.h
M include/hw/elf_ops.h
A include/hw/misc/npcm7xx_pci_mbox.h
A include/hw/misc/stm32l4x5_exti.h
A include/hw/misc/stm32l4x5_syscfg.h
A include/hw/net/npcm_gmac.h
M qemu-img-cmds.hx
M qemu-options.hx
M target/arm/ptw.c
M tests/qtest/meson.build
A tests/qtest/npcm7xx_pci_mbox-test.c
A tests/qtest/npcm_gmac-test.c
A tests/qtest/stm32l4x5_exti-test.c
A tests/qtest/stm32l4x5_syscfg-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240116' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* docs/devel/docs: Document .hx file syntax
* arm_pamax() no longer needs to do feature propagation
* docs/system/arm/virt.rst: Improve 'highmem' option docs
* STM32L4x5 Implement SYSCFG and EXTI devices
* Nuvoton: Implement PCI Mailbox module
* Nuvoton: Implement GMAC module
* hw/timer: fix systick trace message
* hw/arm/virt: Consolidate valid CPU types
* load_elf: fix iterator's type for elf file processing
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# gpg: Signature made Tue 16 Jan 2024 15:09:56 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240116' of
https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
load_elf: fix iterator's type for elf file processing
hw/arm/virt: Consolidate valid CPU types
hw/timer: fix systick trace message
tests/qtest: Adding PCS Module test to GMAC Qtest
hw/net: GMAC Tx Implementation
hw/net: GMAC Rx Implementation
tests/qtest: Creating qtest for GMAC Module
hw/arm: Add GMAC devices to NPCM7XX SoC
hw/net: Add NPCMXXX GMAC device
hw/misc: Add qtest for NPCM7xx PCI Mailbox
hw/arm: Add PCI mailbox module to Nuvoton SoC
hw/misc: Add Nuvoton's PCI Mailbox Module
tests/qtest: Add STM32L4x5 SYSCFG QTest testcase
hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC
hw/misc: Implement STM32L4x5 SYSCFG
tests/qtest: Add STM32L4x5 EXTI QTest testcase
hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC
hw/misc: Implement STM32L4x5 EXTI
docs/system/arm/virt.rst: Improve 'highmem' option docs
target/arm: arm_pamax() no longer needs to do feature propagation
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d0f4aa7d50d4...9c693df15f24
- [Qemu-commits] [qemu/qemu] d95f26: docs/devel/docs: Document .hx file syntax,
Peter Maydell <=