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[Qemu-commits] [qemu/qemu] 853c01: MAINTAINERS: Add the virtio-gpu docum
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 853c01: MAINTAINERS: Add the virtio-gpu documentation to t... |
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Date: |
Wed, 08 Nov 2023 06:18:44 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 853c014bf9565998a245e2b3e70998eef745ac24
https://github.com/qemu/qemu/commit/853c014bf9565998a245e2b3e70998eef745ac24
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add the virtio-gpu documentation to the corresponding section
Add virtio-gpu.rst to the corresponding section in MAINTAINERS, so that
the maintainers gets CC:-ed on corresponding patches.
Message-ID: <20231027060808.242442-1-thuth@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: e93d1e99830481e9a5c758672d2b8ea318f07080
https://github.com/qemu/qemu/commit/e93d1e99830481e9a5c758672d2b8ea318f07080
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M system/vl.c
Log Message:
-----------
vl: Free machine list
Free machine list and make LeakSanitizer happy.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230722062641.18505-1-akihiko.odaki@daynix.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1494a6528044dedc067ab772ec53e51b10b8b00a
https://github.com/qemu/qemu/commit/1494a6528044dedc067ab772ec53e51b10b8b00a
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M system/vl.c
Log Message:
-----------
vl: constify default_list
It's not modified, let's make it const.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231030101529.105266-1-marcandre.lureau@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 57c1a9a7065f52550abbe513b17ec1355d2af576
https://github.com/qemu/qemu/commit/57c1a9a7065f52550abbe513b17ec1355d2af576
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/vm/ubuntu.aarch64
Log Message:
-----------
tests/vm/ubuntu.aarch64: Correct comment about TCG specific delay
Wether we use a software MMU or not to set the SSH timeout
isn't really relevant. What we want to know is if we use
a hardware or software accelerator (TCG).
Replace the 'softmmu' mention by 'TCG'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231002145104.52193-2-philmd@linaro.org>
Commit: 648625e628dde0b57628a2e9992dd4d77744355f
https://github.com/qemu/qemu/commit/648625e628dde0b57628a2e9992dd4d77744355f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/unit/test-seccomp.c
Log Message:
-----------
tests/unit/test-seccomp: Remove mentions of softmmu in test names
Wether we are using a software MMU or not is irrelevant for the
seccomp facility. The facility is restricted to system emulation,
but such detail isn't really helpful, so directly drop the
'softmmu' mention from the test names.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231002145104.52193-3-philmd@linaro.org>
Commit: f4f826c0e0c189869ef55e540a5dcbd90fe392bb
https://github.com/qemu/qemu/commit/f4f826c0e0c189869ef55e540a5dcbd90fe392bb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tcg-accel-ops.c
M hw/core/cpu-common.c
M include/exec/cpu-common.h
M include/exec/tb-flush.h
M plugins/core.c
Log Message:
-----------
accel/tcg: Declare tcg_flush_jmp_cache() in 'exec/tb-flush.h'
"exec/cpu-common.h" is meant to contain the declarations
related to CPU usable with any accelerator / target
combination.
tcg_flush_jmp_cache() is specific to TCG, so restrict its
declaration by moving it to "exec/tb-flush.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230918104153.24433-2-philmd@linaro.org>
Commit: 1b5120d74b1e19c12f8f476f8015a0ac87e11878
https://github.com/qemu/qemu/commit/1b5120d74b1e19c12f8f476f8015a0ac87e11878
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M accel/tcg/user-exec-stub.c
M hw/core/cpu-common.c
M include/hw/core/cpu.h
M include/sysemu/accel-ops.h
M system/cpus.c
Log Message:
-----------
accel: Introduce cpu_exec_reset_hold()
Introduce cpu_exec_reset_hold() which call an accelerator
specific AccelOpsClass::cpu_reset_hold() handler.
Define a stub on TCG user emulation, because CPU reset is
irrelevant there.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230918104153.24433-3-philmd@linaro.org>
Commit: bb6cf6f0168efadb95cf3e41963ec295ad28a941
https://github.com/qemu/qemu/commit/bb6cf6f0168efadb95cf3e41963ec295ad28a941
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M accel/stubs/tcg-stub.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/translate-all.c
M hw/core/cpu-common.c
M include/exec/cpu-common.h
Log Message:
-----------
accel/tcg: Factor tcg_cpu_reset_hold() out
Factor the TCG specific code from cpu_common_reset_hold() to
tcg_cpu_reset_hold() within tcg-accel-ops.c. Since this file
is sysemu specific, we can inline tcg_flush_softmmu_tlb(),
removing its declaration in "exec/cpu-common.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230918104153.24433-4-philmd@linaro.org>
Commit: 6ee45fac56a2e3943214dd0f1568388ee89f16c2
https://github.com/qemu/qemu/commit/6ee45fac56a2e3943214dd0f1568388ee89f16c2
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/alpha/cpu-qom.h
M target/alpha/cpu.h
M target/arm/cpu-qom.h
M target/arm/cpu.h
M target/avr/cpu-qom.h
M target/avr/cpu.h
M target/cris/cpu-qom.h
M target/cris/cpu.h
M target/hexagon/cpu.h
M target/hppa/cpu-qom.h
M target/hppa/cpu.h
M target/i386/cpu-qom.h
M target/i386/cpu.h
M target/loongarch/cpu.h
M target/m68k/cpu-qom.h
M target/m68k/cpu.h
M target/microblaze/cpu-qom.h
M target/microblaze/cpu.h
M target/mips/cpu-qom.h
M target/mips/cpu.h
M target/nios2/cpu.h
M target/openrisc/cpu.h
M target/ppc/cpu.h
M target/riscv/cpu-qom.h
M target/riscv/cpu.h
M target/rx/cpu-qom.h
M target/rx/cpu.h
M target/s390x/cpu-qom.h
M target/s390x/cpu.h
M target/sh4/cpu-qom.h
M target/sh4/cpu.h
M target/sparc/cpu-qom.h
M target/sparc/cpu.h
M target/tricore/cpu-qom.h
M target/tricore/cpu.h
M target/xtensa/cpu-qom.h
M target/xtensa/cpu.h
Log Message:
-----------
target: Unify QOM style
Enforce the style described by commit 067109a11c ("docs/devel:
mention the spacing requirement for QOM"):
The first declaration of a storage or class structure should
always be the parent and leave a visual space between that
declaration and the new code. It is also useful to separate
backing for properties (options driven by the user) and internal
state to make navigation easier.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231013140116.255-2-philmd@linaro.org>
Commit: 336588a29d27d7099155b0e9fa67560f1c454f3d
https://github.com/qemu/qemu/commit/336588a29d27d7099155b0e9fa67560f1c454f3d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/arm/cpu-qom.h
M target/hppa/cpu-qom.h
M target/microblaze/cpu-qom.h
Log Message:
-----------
target: Mention 'cpu-qom.h' is target agnostic
"target/foo/cpu-qom.h" is supposed to be target agnostic
(include-able by any target). Add such mention in the
header.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-3-philmd@linaro.org>
Commit: f6524ddf86bc4af87ddc21b71151399cb47d484a
https://github.com/qemu/qemu/commit/f6524ddf86bc4af87ddc21b71151399cb47d484a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/arm/cpu-qom.h
M target/arm/cpu.h
M target/arm/internals.h
Log Message:
-----------
target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'
These definitions and declarations are only used by
target/arm/, no need to expose them to generic hw/.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-4-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <c48c9829-3dfa-79cf-3042-454fda0d00dc@linaro.org>
Commit: 37b9414b32521dc26e020f16191513c6423ada67
https://github.com/qemu/qemu/commit/37b9414b32521dc26e020f16191513c6423ada67
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
CPU_RESOLVING_TYPE is a per-target definition, and is
irrelevant for other targets. Move it to "cpu.h".
"target/ppc/cpu-qom.h" is supposed to be target agnostic
(include-able by any target). Add such mention in the
header.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-5-philmd@linaro.org>
Commit: 66125f9360f2d698d772d045d1665ff6d380c6c7
https://github.com/qemu/qemu/commit/66125f9360f2d698d772d045d1665ff6d380c6c7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
CPU_RESOLVING_TYPE is a per-target definition, and is
irrelevant for other targets. Move it to "cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-6-philmd@linaro.org>
Commit: 2d56be5a29eb05e33d9fb74bdf55013c5016d5ba
https://github.com/qemu/qemu/commit/2d56be5a29eb05e33d9fb74bdf55013c5016d5ba
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/alpha/cpu-qom.h
M target/alpha/cpu.h
M target/avr/cpu-qom.h
M target/avr/cpu.h
M target/cris/cpu-qom.h
M target/cris/cpu.h
M target/i386/cpu-qom.h
M target/i386/cpu.h
M target/m68k/cpu-qom.h
M target/m68k/cpu.h
M target/mips/cpu-qom.h
M target/mips/cpu.h
M target/rx/cpu-qom.h
M target/rx/cpu.h
M target/s390x/cpu-qom.h
M target/s390x/cpu.h
M target/sh4/cpu-qom.h
M target/sh4/cpu.h
M target/sparc/cpu-qom.h
M target/sparc/cpu.h
M target/tricore/cpu-qom.h
M target/tricore/cpu.h
M target/xtensa/cpu-qom.h
M target/xtensa/cpu.h
Log Message:
-----------
target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
macro to resolve target CPU types. Move the declaration
(along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h".
"target/foo/cpu-qom.h" is supposed to be target agnostic
(include-able by any target). Add such mention in the
header.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-7-philmd@linaro.org>
Commit: 7b6917b9b98287125f139872a0351eb1e7e8350b
https://github.com/qemu/qemu/commit/7b6917b9b98287125f139872a0351eb1e7e8350b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A target/hexagon/cpu-qom.h
M target/hexagon/cpu.h
Log Message:
-----------
target/hexagon: Declare QOM definitions in 'cpu-qom.h'
"target/foo/cpu.h" contains the target specific declarations.
A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).
Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.
Add a comment clarifying that in the header.
Extract QOM definitions from "cpu.h" to "cpu-qom.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20231013140116.255-8-philmd@linaro.org>
Commit: edcea147e342a2ae1cb45a3beb40b428f93b1d1c
https://github.com/qemu/qemu/commit/edcea147e342a2ae1cb45a3beb40b428f93b1d1c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A target/loongarch/cpu-qom.h
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: Declare QOM definitions in 'cpu-qom.h'
"target/foo/cpu.h" contains the target specific declarations.
A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).
Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.
Add a comment clarifying that in the header.
Extract QOM definitions from "cpu.h" to "cpu-qom.h".
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-9-philmd@linaro.org>
Commit: d3680640f18e3f950425e9614c36c154ff43ddb9
https://github.com/qemu/qemu/commit/d3680640f18e3f950425e9614c36c154ff43ddb9
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A target/nios2/cpu-qom.h
M target/nios2/cpu.h
Log Message:
-----------
target/nios2: Declare QOM definitions in 'cpu-qom.h'
"target/foo/cpu.h" contains the target specific declarations.
A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).
Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.
Add a comment clarifying that in the header.
Extract QOM definitions from "cpu.h" to "cpu-qom.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-10-philmd@linaro.org>
Commit: 2d8efe9666dc4297838d9e592d3524285cfb49d6
https://github.com/qemu/qemu/commit/2d8efe9666dc4297838d9e592d3524285cfb49d6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A target/openrisc/cpu-qom.h
M target/openrisc/cpu.h
Log Message:
-----------
target/openrisc: Declare QOM definitions in 'cpu-qom.h'
"target/foo/cpu.h" contains the target specific declarations.
A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).
Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.
Add a comment clarifying that in the header.
Extract QOM definitions from "cpu.h" to "cpu-qom.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-11-philmd@linaro.org>
Commit: 27a6e78ef00c778d0d6d563f90c07deb5176e296
https://github.com/qemu/qemu/commit/27a6e78ef00c778d0d6d563f90c07deb5176e296
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'
TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
definitions which are target specific. Such target specific
definition taints "cpu-qom.h".
Since "cpu-qom.h" must be target agnostic, remove its target
specific definition uses by moving TYPE_RISCV_CPU_BASE to
"target/riscv/cpu.h".
"target/riscv/cpu-qom.h" is now fully target agnostic.
Add a comment clarifying that in the header.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-12-philmd@linaro.org>
Commit: b0a1333331abcf38b6d18a6b97f8f561afc4f48f
https://github.com/qemu/qemu/commit/b0a1333331abcf38b6d18a6b97f8f561afc4f48f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Use env_archcpu() in helper_book3s_msgsndp()
When CPUArchState* is available (here CPUPPCState*), we
can use the fast env_archcpu() macro to get ArchCPU* (here
PowerPCCPU*). The QOM cast POWERPC_CPU() macro will be
slower when building with --enable-qom-cast-debug.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20231009110239.66778-2-philmd@linaro.org>
Commit: edf67fb4c2844a5dad7beb8e1b9634d01f141e72
https://github.com/qemu/qemu/commit/edf67fb4c2844a5dad7beb8e1b9634d01f141e72
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/internals.h
Log Message:
-----------
target/riscv: Use env_archcpu() in [check_]nanbox()
When CPUArchState* is available (here CPURISCVState*), we
can use the fast env_archcpu() macro to get ArchCPU* (here
RISCVCPU*). The QOM cast RISCV_CPU() macro will be slower
when building with --enable-qom-cast-debug.
Inspired-by: Richard W.M. Jones <rjones@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard W.M. Jones <rjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20231009110239.66778-3-philmd@linaro.org>
Commit: 2c6822cd59d5c016bb4e9e36143ad60215f9ff09
https://github.com/qemu/qemu/commit/2c6822cd59d5c016bb4e9e36143ad60215f9ff09
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/s390x/diag.c
Log Message:
-----------
target/s390x: Use env_archcpu() in handle_diag_308()
When CPUArchState* is available (here CPUS390XState*), we
can use the fast env_archcpu() macro to get ArchCPU* (here
S390CPU*). The QOM cast S390_CPU() macro will be slower when
building with --enable-qom-cast-debug.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20231009110239.66778-4-philmd@linaro.org>
Commit: bcb9d2ea77dc83ba2591559fa2052a8ca63e591f
https://github.com/qemu/qemu/commit/bcb9d2ea77dc83ba2591559fa2052a8ca63e591f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/xtensa/op_helper.c
Log Message:
-----------
target/xtensa: Use env_archcpu() in update_c[compare|count]()
When CPUArchState* is available (here CPUXtensaState*), we
can use the fast env_archcpu() macro to get ArchCPU* (here
XtensaCPU*). The QOM cast XTENSA_CPU() macro will be slower
when building with --enable-qom-cast-debug.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20231009110239.66778-5-philmd@linaro.org>
Commit: 82b641d6261a58d9fba5a6ce786e7d58a8876e25
https://github.com/qemu/qemu/commit/82b641d6261a58d9fba5a6ce786e7d58a8876e25
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/hvf/x86_emu.c
Log Message:
-----------
target/i386/hvf: Use x86_cpu in simulate_[rdmsr|wrmsr]()
We already have 'x86_cpu = X86_CPU(cpu)'. Use the variable
instead of doing another QOM cast with X86_CPU().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Roman Bolshakov <roman@roolebo.dev>
Tested-by: Roman Bolshakov <roman@roolebo.dev>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231009110239.66778-6-philmd@linaro.org>
Commit: a9e445df545158e3d6e3239f10c2e88d8119fdd1
https://github.com/qemu/qemu/commit/a9e445df545158e3d6e3239f10c2e88d8119fdd1
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/hvf/hvf.c
M target/i386/hvf/x86_emu.c
M target/i386/hvf/x86_emu.h
Log Message:
-----------
target/i386/hvf: Use env_archcpu() in simulate_[rdmsr/wrmsr]()
When CPUArchState* is available (here CPUX86State*), we can
use the fast env_archcpu() macro to get ArchCPU* (here X86CPU*).
The QOM cast X86_CPU() macro will be slower when building with
--enable-qom-cast-debug.
Pass CPUX86State* as argument to simulate_rdmsr / simulate_wrmsr
instead of a CPUState* to avoid an extra cast.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Roman Bolshakov <roman@roolebo.dev>
Tested-by: Roman Bolshakov <roman@roolebo.dev>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231009110239.66778-7-philmd@linaro.org>
Commit: 89c02195c96641fa2b7a5e767e03eec945c45943
https://github.com/qemu/qemu/commit/89c02195c96641fa2b7a5e767e03eec945c45943
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/hvf/x86_emu.c
Log Message:
-----------
target/i386/hvf: Use CPUState typedef
Follow C style guidelines and use CPUState forward
declaration from "qemu/typedefs.h".
No functional changes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231020111136.44401-2-philmd@linaro.org>
Commit: 5366a0644f7fc68334a7ac6e0f131c90cdb5bcc4
https://github.com/qemu/qemu/commit/5366a0644f7fc68334a7ac6e0f131c90cdb5bcc4
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/hvf/x86_emu.c
Log Message:
-----------
target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs'
Follow the naming used by other files in target/i386/.
No functional changes.
Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231020111136.44401-3-philmd@linaro.org>
Commit: 3152e954135a40b07fefd11738616c66a2d30e1b
https://github.com/qemu/qemu/commit/3152e954135a40b07fefd11738616c66a2d30e1b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/hvf/x86_emu.c
Log Message:
-----------
target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu'
Follow the naming used by other files in target/i386/.
No functional changes.
Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231020111136.44401-4-philmd@linaro.org>
Commit: de910c496a62db24388b9ef7da49f06b12745274
https://github.com/qemu/qemu/commit/de910c496a62db24388b9ef7da49f06b12745274
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/kvm/kvm-cpu.c
Log Message:
-----------
target/i386/kvm: Correct comment in kvm_cpu_realize()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230918160257.30127-4-philmd@linaro.org>
Commit: 2b34d7382b669b154f44d616f7e5b78f459ffd61
https://github.com/qemu/qemu/commit/2b34d7382b669b154f44d616f7e5b78f459ffd61
Author: Dongli Zhang <dongli.zhang@oracle.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/monitor.c
Log Message:
-----------
target/i386/monitor: synchronize cpu state for lapic info
While the default "info lapic" always synchronizes cpu state ...
mon_get_cpu()
-> mon_get_cpu_sync(mon, true)
-> cpu_synchronize_state(cpu)
-> ioctl KVM_GET_LAPIC (taking KVM as example)
... the cpu state is not synchronized when the apic-id is available as
argument.
The cpu state should be synchronized when apic-id is available. Otherwise
the "info lapic <apic-id>" always returns stale data.
Reference:
https://lore.kernel.org/all/20211028155457.967291-19-berrange@redhat.com/
Cc: Joe Jin <joe.jin@oracle.com>
Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Message-ID: <20231030085336.2681386-1-armbru@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231026211938.162815-1-dongli.zhang@oracle.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 04591b3ddd9a96b9298a1dd437a6464ab55e62ee
https://github.com/qemu/qemu/commit/04591b3ddd9a96b9298a1dd437a6464ab55e62ee
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/mips/tcg/msa.decode
Log Message:
-----------
target/mips: Fix MSA BZ/BNZ opcodes displacement
The PC offset is *signed*.
Cc: qemu-stable@nongnu.org
Reported-by: Sergey Evlashev <vectorchiefrocks@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624
Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914085807.12241-1-philmd@linaro.org>
Commit: 18f86aecd6a1bea0f78af14587a684ad966d8d3a
https://github.com/qemu/qemu/commit/18f86aecd6a1bea0f78af14587a684ad966d8d3a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/mips/tcg/tx79.decode
Log Message:
-----------
target/mips: Fix TX79 LQ/SQ opcodes
The base register address offset is *signed*.
Cc: qemu-stable@nongnu.org
Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914090447.12557-1-philmd@linaro.org>
Commit: aa6edf97ce9783bf831ffaca5eda243210290292
https://github.com/qemu/qemu/commit/aa6edf97ce9783bf831ffaca5eda243210290292
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/sysemu/kvm.h
M target/ppc/kvm.c
Log Message:
-----------
sysemu/kvm: Restrict kvmppc_get_radix_page_info() to ppc targets
kvm_get_radix_page_info() is only defined for ppc targets (in
target/ppc/kvm.c). The declaration is not useful in other targets,
reduce its scope.
Rename using the 'kvmppc_' prefix following other declarations
from target/ppc/kvm_ppc.h.
Suggested-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20231003070427.69621-2-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 86d9ff288a9f978840982c6d663b78d64021a6da
https://github.com/qemu/qemu/commit/86d9ff288a9f978840982c6d663b78d64021a6da
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ppc/e500.c
R target/ppc/kvm-stub.c
M target/ppc/meson.build
Log Message:
-----------
hw/ppc/e500: Restrict ppce500_init_mpic_kvm() to KVM
Inline and guard the single call to kvm_openpic_connect_vcpu()
allows to remove kvm-stub.c.
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231003070427.69621-3-philmd@linaro.org>
Commit: a523b6761c32d62304037366717e0c2ede8bbf3b
https://github.com/qemu/qemu/commit/a523b6761c32d62304037366717e0c2ede8bbf3b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/meson.build
Log Message:
-----------
target/ppc: Restrict KVM objects to system emulation
CONFIG_KVM is always FALSE on user emulation, so 'kvm.c'
won't be added to ppc_ss[] source set; direcly use the system
specific ppc_system_ss[] source set.
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231003070427.69621-4-philmd@linaro.org>
Commit: c6b8252c6d55a4db19a67c295f88b66158c6d94e
https://github.com/qemu/qemu/commit/c6b8252c6d55a4db19a67c295f88b66158c6d94e
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Prohibit target specific KVM prototypes on user emulation
None of these target-specific prototypes should be used
by user emulation. Remove their declaration there, so we
get a compile failure if ever used (instead of having to
deal with linker and its possible optimizations, such
dead code removal).
Suggested-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20231003070427.69621-5-philmd@linaro.org>
Commit: 1978a41bcf4112ca95dac96ecf5b79613ae9a4ba
https://github.com/qemu/qemu/commit/1978a41bcf4112ca95dac96ecf5b79613ae9a4ba
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/internal.h
Log Message:
-----------
target/ppc: Define powerpc_pm_insn_t in 'internal.h'
PM instructions are only used by TCG helpers. No need to
expose to other hardware.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-3-philmd@linaro.org>
Commit: 866c8cf91879ac9a079fb3d676af3b4f47fc57cf
https://github.com/qemu/qemu/commit/866c8cf91879ac9a079fb3d676af3b4f47fc57cf
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h'
ppc_cpu_class_by_name() is only called in target/ppc/,
no need to expose outside (in particular to hw/).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-4-philmd@linaro.org>
Commit: f3cb33255c6baa0362012349b58bf49bc8f9f704
https://github.com/qemu/qemu/commit/f3cb33255c6baa0362012349b58bf49bc8f9f704
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/hw/ppc/ppc.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Move PowerPCCPUClass definition to 'cpu.h'
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares the
PowerPCCPUClass type. This forward declaration is sufficient
for code in hw/ to use the QOM definitions. No need to expose
the structure definition. Keep it local to target/ppc/ by
moving it to target/ppc/cpu.h.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013125630.95116-5-philmd@linaro.org>
Commit: d66d3d4ab9a3774406343ad67ae4b4b77bedec7b
https://github.com/qemu/qemu/commit/d66d3d4ab9a3774406343ad67ae4b4b77bedec7b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Move powerpc_excp_t definition to 'cpu.h'
The powerpc_excp_t definition is only used by target/ppc/, no need
to expose it. Restrict it by moving it to "target/ppc/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-6-philmd@linaro.org>
Commit: 6fb8b16a711596fdaa40b4c2fec90a997e4e8d94
https://github.com/qemu/qemu/commit/6fb8b16a711596fdaa40b4c2fec90a997e4e8d94
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Move powerpc_mmu_t definition to 'cpu.h'
The powerpc_mmu_t definition is only used by target/ppc/, no need
to expose it. Restrict it by moving it to "target/ppc/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-7-philmd@linaro.org>
Commit: 2bb53fa2f36c03ed73b643592d9f6d2c3898d9d1
https://github.com/qemu/qemu/commit/2bb53fa2f36c03ed73b643592d9f6d2c3898d9d1
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Move powerpc_input_t definition to 'cpu.h'
The powerpc_input_t definition is only used by target/ppc/, no need
to expose it. Restrict it by moving it to "target/ppc/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-8-philmd@linaro.org>
Commit: 6233759ae15302e0ea60b8cda849fcd2c01d8098
https://github.com/qemu/qemu/commit/6233759ae15302e0ea60b8cda849fcd2c01d8098
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/s390x/css.c
M include/hw/s390x/css.h
M target/s390x/kvm/kvm.c
M target/s390x/tcg/misc_helper.c
Log Message:
-----------
hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState
"hw/s390x/css.h" is a header used by target-agnostic objects
(such hw/s390x/virtio-ccw-gpu.c), thus can not use target-specific
types, such CPUS390XState.
Have css_do_sic() take S390CPU a pointer, which is target-agnostic.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-2-philmd@linaro.org>
Commit: 6d3910c9dbad5ff47c43214397f7afef9645ceb7
https://github.com/qemu/qemu/commit/6d3910c9dbad5ff47c43214397f7afef9645ceb7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/s390x/sclp.c
M include/hw/s390x/sclp.h
M target/s390x/kvm/kvm.c
M target/s390x/tcg/misc_helper.c
Log Message:
-----------
hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU*
"hw/s390x/sclp.h" is a header used by target-agnostic objects
(such hw/char/sclpconsole[-lm].c), thus can not use target-specific
types, such CPUS390XState.
Have sclp_service_call[_protected]() take a S390CPU pointer, which
is target-agnostic.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-3-philmd@linaro.org>
Commit: 1663e886cb3b609aed05b92c97d24bc6e66110f9
https://github.com/qemu/qemu/commit/1663e886cb3b609aed05b92c97d24bc6e66110f9
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/s390x/cpu.h
Log Message:
-----------
target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG
cpu_get_tb_cpu_state() is TCG specific. Another accelerator
calling it would be a bug, so restrict the definition to TCG,
along with "tcg_s390x.h" header inclusion.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-4-philmd@linaro.org>
Commit: 571568a173dfae14c27ef0db9fd2f7b77f0e4bad
https://github.com/qemu/qemu/commit/571568a173dfae14c27ef0db9fd2f7b77f0e4bad
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/s390x/cpu-qom.h
M target/s390x/cpu.h
Log Message:
-----------
target/s390x/cpu: Restrict CPUS390XState declaration to 'cpu.h'
"target/s390x/cpu-qom.h" has to be target-agnostic. However, it
currently declares CPUS390XState, which is target-specific.
Move that declaration to "cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231106114500.5269-5-philmd@linaro.org>
Commit: c61b18a5d0562851b933cd2fdc61cf21ea1be270
https://github.com/qemu/qemu/commit/c61b18a5d0562851b933cd2fdc61cf21ea1be270
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/nios2/cpu.c
Log Message:
-----------
target/nios2: Create IRQs *after* accelerator vCPU is realized
Architecture specific hardware doesn't have a particular dependency
on the accelerator vCPU (created with cpu_exec_realizefn), and can
be initialized *after* the vCPU is realized. Doing so allows further
generic API simplification (in few commits).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230918160257.30127-12-philmd@linaro.org>
Commit: 9348028e7ed089a1e9ed45091668c4c199e76fcd
https://github.com/qemu/qemu/commit/9348028e7ed089a1e9ed45091668c4c199e76fcd
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/alpha/cpu-qom.h
M target/alpha/cpu.h
M target/arm/cpu-qom.h
M target/arm/cpu.h
M target/avr/cpu-qom.h
M target/avr/cpu.h
M target/cris/cpu-qom.h
M target/cris/cpu.h
M target/hexagon/cpu-qom.h
M target/hppa/cpu-qom.h
M target/hppa/cpu.h
M target/i386/cpu-qom.h
M target/i386/cpu.h
M target/loongarch/cpu-qom.h
M target/m68k/cpu-qom.h
M target/m68k/cpu.h
M target/microblaze/cpu-qom.h
M target/microblaze/cpu.h
M target/mips/cpu-qom.h
M target/mips/cpu.h
M target/nios2/cpu-qom.h
M target/openrisc/cpu-qom.h
M target/riscv/cpu-qom.h
M target/riscv/cpu.h
M target/rx/cpu-qom.h
M target/rx/cpu.h
M target/s390x/cpu-qom.h
M target/s390x/cpu.h
M target/s390x/cpu_models.h
M target/sh4/cpu-qom.h
M target/sh4/cpu.h
M target/sparc/cpu-qom.h
M target/sparc/cpu.h
M target/tricore/cpu-qom.h
M target/tricore/cpu.h
M target/xtensa/cpu-qom.h
M target/xtensa/cpu.h
Log Message:
-----------
target: Move ArchCPUClass definition to 'cpu.h'
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each
ArchCPUClass type. These forward declarations are sufficient
for code in hw/ to use the QOM definitions. No need to expose
these structure definitions. Keep each local to their target/
by moving them to the corresponding "cpu.h" header.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231013140116.255-13-philmd@linaro.org>
Commit: 55f2cd77376c6f2187ff386ab3b330ef260eedb2
https://github.com/qemu/qemu/commit/55f2cd77376c6f2187ff386ab3b330ef260eedb2
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/alpha/cpu.c
Log Message:
-----------
target/alpha: Tidy up alpha_cpu_class_by_name()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-Id: <20230908112235.75914-2-philmd@linaro.org>
Commit: 3a9d0d7b64b72144369f48ef12ef0ed69d633fd6
https://github.com/qemu/qemu/commit/3a9d0d7b64b72144369f48ef12ef0ed69d633fd6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/core/cpu-common.c
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hexagon/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/openrisc/cpu.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()
Let CPUClass::class_by_name() handlers to return abstract classes,
and filter them once in the public cpu_class_by_name() method.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230908112235.75914-3-philmd@linaro.org>
Commit: 79a99091c1af7783a13c21ab5e4049265fcbb1d1
https://github.com/qemu/qemu/commit/79a99091c1af7783a13c21ab5e4049265fcbb1d1
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M cpu-target.c
M include/hw/core/cpu.h
Log Message:
-----------
exec/cpu: Have cpu_exec_realize() return a boolean
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have cpu_exec_realizefn()
return a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230918160257.30127-22-philmd@linaro.org>
Commit: 3c55dd5896d687b5d5e61e8eec07b8bb2931713a
https://github.com/qemu/qemu/commit/3c55dd5896d687b5d5e61e8eec07b8bb2931713a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M bsd-user/main.c
M cpu-common.c
M include/hw/core/cpu.h
M linux-user/main.c
M target/s390x/cpu_models.c
Log Message:
-----------
hw/cpu: Clean up global variable shadowing
Fix:
hw/core/machine.c:1302:22: error: declaration shadows a variable in the
global scope [-Werror,-Wshadow]
const CPUArchId *cpus = possible_cpus->cpus;
^
hw/core/numa.c:69:17: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
uint16List *cpus = NULL;
^
hw/acpi/aml-build.c:2005:20: error: declaration shadows a variable in the
global scope [-Werror,-Wshadow]
CPUArchIdList *cpus = ms->possible_cpus;
^
hw/core/machine-smp.c:77:14: error: declaration shadows a variable in the
global scope [-Werror,-Wshadow]
unsigned cpus = config->has_cpus ? config->cpus : 0;
^
include/hw/core/cpu.h:589:17: note: previous declaration is here
extern CPUTailQ cpus;
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231010115048.11856-2-philmd@linaro.org>
Commit: e265ee4379a62949133ce3b5d1b4b4b12a884944
https://github.com/qemu/qemu/commit/e265ee4379a62949133ce3b5d1b4b4b12a884944
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/core/loader.c
M include/hw/loader.h
Log Message:
-----------
hw/loader: Clean up global variable shadowing in rom_add_file()
Fix:
hw/core/loader.c:1073:27: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
bool option_rom, MemoryRegion *mr,
^
include/sysemu/sysemu.h:57:22: note: previous declaration is here
extern QEMUOptionRom option_rom[MAX_OPTION_ROMS];
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231010115048.11856-3-philmd@linaro.org>
Commit: 2798ee63b03a8a67017c4fa5ef21fc85bfef67d5
https://github.com/qemu/qemu/commit/2798ee63b03a8a67017c4fa5ef21fc85bfef67d5
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/isa/i82378.c
Log Message:
-----------
hw/isa/i82378: Propagate error if PC_SPEAKER device creation failed
In commit 40f8214fcd ("hw/audio/pcspk: Inline pcspk_init()")
we neglected to give a change to the caller to handle failed
device creation cleanly. Respect the caller API contract and
propagate the error if creating the PC_SPEAKER device ever
failed. This avoid yet another bad API use to be taken as
example and copy / pasted all over the code base.
Reported-by: Bernhard Beschow <shentey@gmail.com>
Suggested-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231020171509.87839-5-philmd@linaro.org>
Commit: 5f0d69b5a69f56d63a1afd5f927919b1584e5e9b
https://github.com/qemu/qemu/commit/5f0d69b5a69f56d63a1afd5f927919b1584e5e9b
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/hw/i386/topology.h
Log Message:
-----------
hw/i386: Fix comment style in topology.h
For function comments in this file, keep the comment style consistent
with other files in the directory.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@Intel.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231024090323.1859210-2-zhao1.liu@linux.intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: af4c26e618368cbb474d3fb142b2a18b7a54c2e0
https://github.com/qemu/qemu/commit/af4c26e618368cbb474d3fb142b2a18b7a54c2e0
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M tests/unit/meson.build
R tests/unit/test-x86-cpuid.c
A tests/unit/test-x86-topo.c
Log Message:
-----------
tests/unit: Rename test-x86-cpuid.c to test-x86-topo.c
The tests in this file actually test the APIC ID combinations.
Rename to test-x86-topo.c to make its name more in line with its
actual content.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231024090323.1859210-3-zhao1.liu@linux.intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 958ac3c42b683ceee9660fecb707b8d4468348ab
https://github.com/qemu/qemu/commit/958ac3c42b683ceee9660fecb707b8d4468348ab
Author: Zhuocheng Ding <zhuocheng.ding@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M system/cpus.c
M target/i386/cpu.c
Log Message:
-----------
system/cpus: Fix CPUState.nr_cores' calculation
>From CPUState.nr_cores' comment, it represents "number of cores within
this CPU package".
After 003f230e37d7 ("machine: Tweak the order of topology members in
struct CpuTopology"), the meaning of smp.cores changed to "the number of
cores in one die", but this commit missed to change CPUState.nr_cores'
calculation, so that CPUState.nr_cores became wrong and now it
misses to consider numbers of clusters and dies.
At present, only i386 is using CPUState.nr_cores.
But as for i386, which supports die level, the uses of CPUState.nr_cores
are very confusing:
Early uses are based on the meaning of "cores per package" (before die
is introduced into i386), and later uses are based on "cores per die"
(after die's introduction).
This difference is due to that commit a94e1428991f ("target/i386: Add
CPUID.1F generation support for multi-dies PCMachine") misunderstood
that CPUState.nr_cores means "cores per die" when calculated
CPUID.1FH.01H:EBX. After that, the changes in i386 all followed this
wrong understanding.
With the influence of 003f230e37d7 and a94e1428991f, for i386 currently
the result of CPUState.nr_cores is "cores per die", thus the original
uses of CPUState.cores based on the meaning of "cores per package" are
wrong when multiple dies exist:
1. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.01H:EBX[bits 23:16] is
incorrect because it expects "cpus per package" but now the
result is "cpus per die".
2. In cpu_x86_cpuid() of target/i386/cpu.c, for all leaves of CPUID.04H:
EAX[bits 31:26] is incorrect because they expect "cpus per package"
but now the result is "cpus per die". The error not only impacts the
EAX calculation in cache_info_passthrough case, but also impacts other
cases of setting cache topology for Intel CPU according to cpu
topology (specifically, the incoming parameter "num_cores" expects
"cores per package" in encode_cache_cpuid4()).
3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.0BH.01H:EBX[bits
15:00] is incorrect because the EBX of 0BH.01H (core level) expects
"cpus per package", which may be different with 1FH.01H (The reason
is 1FH can support more levels. For QEMU, 1FH also supports die,
1FH.01H:EBX[bits 15:00] expects "cpus per die").
4. In cpu_x86_cpuid() of target/i386/cpu.c, when CPUID.80000001H is
calculated, here "cpus per package" is expected to be checked, but in
fact, now it checks "cpus per die". Though "cpus per die" also works
for this code logic, this isn't consistent with AMD's APM.
5. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.80000008H:ECX expects
"cpus per package" but it obtains "cpus per die".
6. In simulate_rdmsr() of target/i386/hvf/x86_emu.c, in
kvm_rdmsr_core_thread_count() of target/i386/kvm/kvm.c, and in
helper_rdmsr() of target/i386/tcg/sysemu/misc_helper.c,
MSR_CORE_THREAD_COUNT expects "cpus per package" and "cores per
package", but in these functions, it obtains "cpus per die" and
"cores per die".
On the other hand, these uses are correct now (they are added in/after
a94e1428991f):
1. In cpu_x86_cpuid() of target/i386/cpu.c, topo_info.cores_per_die
meets the actual meaning of CPUState.nr_cores ("cores per die").
2. In cpu_x86_cpuid() of target/i386/cpu.c, vcpus_per_socket (in CPUID.
04H's calculation) considers number of dies, so it's correct.
3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.1FH.01H:EBX[bits
15:00] needs "cpus per die" and it gets the correct result, and
CPUID.1FH.02H:EBX[bits 15:00] gets correct "cpus per package".
When CPUState.nr_cores is correctly changed to "cores per package" again
, the above errors will be fixed without extra work, but the "currently"
correct cases will go wrong and need special handling to pass correct
"cpus/cores per die" they want.
Fix CPUState.nr_cores' calculation to fit the original meaning "cores
per package", as well as changing calculation of topo_info.cores_per_die,
vcpus_per_socket and CPUID.1FH.
Fixes: a94e1428991f ("target/i386: Add CPUID.1F generation support for
multi-dies PCMachine")
Fixes: 003f230e37d7 ("machine: Tweak the order of topology members in struct
CpuTopology")
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231024090323.1859210-4-zhao1.liu@linux.intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: aa1878fbc96aea70ba2a3a471111bec5352946fe
https://github.com/qemu/qemu/commit/aa1878fbc96aea70ba2a3a471111bec5352946fe
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/hw/core/cpu.h
M target/i386/cpu.h
Log Message:
-----------
hw/cpu: Update the comments of nr_cores and nr_dies
In the nr_threads' comment, specify it represents the
number of threads in the "core" to avoid confusion.
Also add comment for nr_dies in CPUX86State.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231024090323.1859210-5-zhao1.liu@linux.intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7d7512019fc40c577e2bdd61f114f31a9eb84a8e
https://github.com/qemu/qemu/commit/7d7512019fc40c577e2bdd61f114f31a9eb84a8e
Author: Fiona Ebner <f.ebner@proxmox.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ide/core.c
Log Message:
-----------
hw/ide: reset: cancel async DMA operation before resetting state
If there is a pending DMA operation during ide_bus_reset(), the fact
that the IDEState is already reset before the operation is canceled
can be problematic. In particular, ide_dma_cb() might be called and
then use the reset IDEState which contains the signature after the
reset. When used to construct the IO operation this leads to
ide_get_sector() returning 0 and nsector being 1. This is particularly
bad, because a write command will thus destroy the first sector which
often contains a partition table or similar.
Traces showing the unsolicited write happening with IDEState
0x5595af6949d0 being used after reset:
> ahci_port_write ahci(0x5595af6923f0)[0]: port write [reg:PxSCTL] @ 0x2c:
> 0x00000300
> ahci_reset_port ahci(0x5595af6923f0)[0]: reset port
> ide_reset IDEstate 0x5595af6949d0
> ide_reset IDEstate 0x5595af694da8
> ide_bus_reset_aio aio_cancel
> dma_aio_cancel dbs=0x7f64600089a0
> dma_blk_cb dbs=0x7f64600089a0 ret=0
> dma_complete dbs=0x7f64600089a0 ret=0 cb=0x5595acd40b30
> ahci_populate_sglist ahci(0x5595af6923f0)[0]
> ahci_dma_prepare_buf ahci(0x5595af6923f0)[0]: prepare buf limit=512
> prepared=512
> ide_dma_cb IDEState 0x5595af6949d0; sector_num=0 n=1 cmd=DMA WRITE
> dma_blk_io dbs=0x7f6420802010 bs=0x5595ae2c6c30 offset=0 to_dev=1
> dma_blk_cb dbs=0x7f6420802010 ret=0
> (gdb) p *qiov
> $11 = {iov = 0x7f647c76d840, niov = 1, {{nalloc = 1, local_iov = {iov_base =
> 0x0,
> iov_len = 512}}, {__pad =
> "\001\000\000\000\000\000\000\000\000\000\000",
> size = 512}}}
> (gdb) bt
> #0 blk_aio_pwritev (blk=0x5595ae2c6c30, offset=0, qiov=0x7f6420802070,
> flags=0,
> cb=0x5595ace6f0b0 <dma_blk_cb>, opaque=0x7f6420802010)
> at ../block/block-backend.c:1682
> #1 0x00005595ace6f185 in dma_blk_cb (opaque=0x7f6420802010, ret=<optimized
> out>)
> at ../softmmu/dma-helpers.c:179
> #2 0x00005595ace6f778 in dma_blk_io (ctx=0x5595ae0609f0,
> sg=sg@entry=0x5595af694d00, offset=offset@entry=0, align=align@entry=512,
> io_func=io_func@entry=0x5595ace6ee30 <dma_blk_write_io_func>,
> io_func_opaque=io_func_opaque@entry=0x5595ae2c6c30,
> cb=0x5595acd40b30 <ide_dma_cb>, opaque=0x5595af6949d0,
> dir=DMA_DIRECTION_TO_DEVICE) at ../softmmu/dma-helpers.c:244
> #3 0x00005595ace6f90a in dma_blk_write (blk=0x5595ae2c6c30,
> sg=sg@entry=0x5595af694d00, offset=offset@entry=0, align=align@entry=512,
> cb=cb@entry=0x5595acd40b30 <ide_dma_cb>,
> opaque=opaque@entry=0x5595af6949d0)
> at ../softmmu/dma-helpers.c:280
> #4 0x00005595acd40e18 in ide_dma_cb (opaque=0x5595af6949d0, ret=<optimized
> out>)
> at ../hw/ide/core.c:953
> #5 0x00005595ace6f319 in dma_complete (ret=0, dbs=0x7f64600089a0)
> at ../softmmu/dma-helpers.c:107
> #6 dma_blk_cb (opaque=0x7f64600089a0, ret=0) at ../softmmu/dma-helpers.c:127
> #7 0x00005595ad12227d in blk_aio_complete (acb=0x7f6460005b10)
> at ../block/block-backend.c:1527
> #8 blk_aio_complete (acb=0x7f6460005b10) at ../block/block-backend.c:1524
> #9 blk_aio_write_entry (opaque=0x7f6460005b10) at
> ../block/block-backend.c:1594
> #10 0x00005595ad258cfb in coroutine_trampoline (i0=<optimized out>,
> i1=<optimized out>) at ../util/coroutine-ucontext.c:177
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: simon.rowe@nutanix.com
Message-ID: <20230906130922.142845-1-f.ebner@proxmox.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: cc610857bbd3551f4b86ae2299336b5d9aa0db2b
https://github.com/qemu/qemu/commit/cc610857bbd3551f4b86ae2299336b5d9aa0db2b
Author: Fiona Ebner <f.ebner@proxmox.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/qtest/ahci-test.c
Log Message:
-----------
tests/qtest: ahci-test: add test exposing reset issue with pending callback
Before commit "hw/ide: reset: cancel async DMA operation before
resetting state", this test would fail, because a reset with a
pending write operation would lead to an unsolicited write to the
first sector of the disk.
The test writes a pattern to the beginning of the disk and verifies
that it is still intact after a reset with a pending operation. It
also checks that the pending operation actually completes correctly.
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Message-ID: <20230906130922.142845-2-f.ebner@proxmox.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: cfb0884c6f941977db1e0ce53ac659a8428e4e48
https://github.com/qemu/qemu/commit/cfb0884c6f941977db1e0ce53ac659a8428e4e48
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i2c/pmbus_device.c
M include/hw/i2c/pmbus_device.h
Log Message:
-----------
hw/i2c: pmbus add support for block receive
PMBus devices can send and receive variable length data using the
block read and write format, with the first byte in the payload
denoting the length.
This is mostly used for strings and on-device logs. Devices can
respond to a block read with an empty string.
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
Message-ID: <20231023-staging-pmbus-v3-v4-1-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 144729b9f1156174d41df54f05f4b57ce80e30de
https://github.com/qemu/qemu/commit/144729b9f1156174d41df54f05f4b57ce80e30de
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/hw/i2c/pmbus_device.h
Log Message:
-----------
hw/i2c: pmbus: add vout mode bitfields
The VOUT_MODE command is described in the PMBus Specification,
Part II, Ver 1.3 Section 8.3
VOUT_MODE has a three bit mode and 4 bit parameter, the three bit
mode determines whether voltages are formatted as uint16, uint16,
VID, and Direct modes. VID and Direct modes use the remaining 5 bits
to scale the voltage readings.
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
Message-ID: <20231023-staging-pmbus-v3-v4-2-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b7fba25ef1f32bfe92d9fcc73f297b2ce58fee9e
https://github.com/qemu/qemu/commit/b7fba25ef1f32bfe92d9fcc73f297b2ce58fee9e
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i2c/pmbus_device.c
M include/hw/i2c/pmbus_device.h
Log Message:
-----------
hw/i2c: pmbus: add fan support
PMBus devices may integrate fans whose operation is configurable
over PMBus. This commit allows the driver to read and write the
fan control registers but does not model the operation of fans.
Reviewed-by: Stephen Longfield <slongfield@google.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
Message-ID: <20231023-staging-pmbus-v3-v4-3-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 3401b1dd1a947256dcfa5494642dfb46c16c47c2
https://github.com/qemu/qemu/commit/3401b1dd1a947256dcfa5494642dfb46c16c47c2
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i2c/pmbus_device.c
M include/hw/i2c/pmbus_device.h
Log Message:
-----------
hw/i2c: pmbus: add VCAP register
VCAP is a register for devices with energy storage capacitors.
Reviewed-by: Benjamin Streb <bstreb@google.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
Message-ID: <20231023-staging-pmbus-v3-v4-4-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 6f351a7a707f5d4257b6c55b28e9d99012730acc
https://github.com/qemu/qemu/commit/6f351a7a707f5d4257b6c55b28e9d99012730acc
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M hw/arm/Kconfig
M hw/sensor/Kconfig
A hw/sensor/adm1266.c
M hw/sensor/meson.build
Log Message:
-----------
hw/sensor: add ADM1266 device model
The ADM1266 is a cascadable super sequencer with margin control and
fault recording.
This commit adds basic support for its PMBus commands and models
the identification registers that can be modified in a firmware
update.
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
[PMD: Cover file in MAINTAINERS]
Message-ID: <20231023-staging-pmbus-v3-v4-5-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 5861f5abf408a4d9c03a827869bc42d2aae8976b
https://github.com/qemu/qemu/commit/5861f5abf408a4d9c03a827869bc42d2aae8976b
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
A tests/qtest/adm1266-test.c
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: add tests for ADM1266
The ADM1266 can have string fields written by the driver, so
it's worth specifically testing.
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
[PMD: Cover file in MAINTAINERS]
Message-ID: <20231023-staging-pmbus-v3-v4-6-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 84db503e7c260ace0cf7267379955bbae77e85a4
https://github.com/qemu/qemu/commit/84db503e7c260ace0cf7267379955bbae77e85a4
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i2c/pmbus_device.c
Log Message:
-----------
hw/i2c: pmbus: immediately clear faults on request
The probing process of the generic pmbus driver generates
faults to determine if functions are available. These faults
were not always cleared resulting in probe failures.
Reviewed-by: Patrick Venture <venture@google.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
Message-ID: <20231023-staging-pmbus-v3-v4-7-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: ff0511282d406150984de1aaaaad451da8ad3a1c
https://github.com/qemu/qemu/commit/ff0511282d406150984de1aaaaad451da8ad3a1c
Author: Titus Rwantare <titusr@google.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i2c/pmbus_device.c
M tests/qtest/max34451-test.c
Log Message:
-----------
hw/i2c: pmbus: reset page register for out of range reads
The linux pmbus driver scans all possible pages and does not reset the
current page after the scan, making all future page reads fail as out of range
on devices with a single page.
This change resets out of range pages immediately on write.
Also added a qtest for simultaneous writes to all pages.
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Titus Rwantare <titusr@google.com>
Message-ID: <20231023-staging-pmbus-v3-v4-8-07a8cb7cd20a@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 88d2198c0836871e5902da1e1340e3ba3cb5a71d
https://github.com/qemu/qemu/commit/88d2198c0836871e5902da1e1340e3ba3cb5a71d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/sd/aspeed_sdhci.c
M hw/sd/bcm2835_sdhost.c
M hw/sd/cadence_sdhci.c
M hw/sd/core.c
M hw/sd/npcm7xx_sdhci.c
M hw/sd/pl181.c
M hw/sd/pxa2xx_mmci.c
M hw/sd/sd.c
M hw/sd/sdhci-pci.c
M hw/sd/ssi-sd.c
Log Message:
-----------
hw/sd: Declare QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Mechanical transformation using the following comby script:
[pattern-x1]
match='''
static const TypeInfo :[i1~.*_info] = {
:[body]
};
static void :[rt1~.*_register_type.](void)
{
type_register_static(&:[i2~.*_info]);
}
type_init(:[rt2~.*_register_type.])
'''
rewrite='''
static const TypeInfo :[i1][] = {
{
:[body]
},
};
DEFINE_TYPES(:[i1])
'''
rule='where :[i1] == :[i2], :[rt1] == :[rt2]'
[pattern-x2]
match='''
static const TypeInfo :[i1a~.*_info] = {
:[body1]
};
...
static const TypeInfo :[i2a~.*_info] = {
:[body2]
};
static void :[rt1~.*_register_type.](void)
{
type_register_static(&:[i1b~.*_info]);
type_register_static(&:[i2b~.*_info]);
}
type_init(:[rt2~.*_register_type.])
'''
rewrite='''
static const TypeInfo :[i1a][] = {
{
:[body1]
},
{
:[body2]
},
};
DEFINE_TYPES(:[i1a])
'''
rule='''
where
:[i1a] == :[i1b],
:[i2a] == :[i2b],
:[rt1] == :[rt2]
'''
and re-indented manually.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231031080603.86889-2-philmd@linaro.org>
Commit: 670185cad5f1eaaef8c1949d55ccc10e9c4810dc
https://github.com/qemu/qemu/commit/670185cad5f1eaaef8c1949d55ccc10e9c4810dc
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section
tmu012.h is the header that belongs to hw/timer/sh_timer.c, so we
should list it in the same section as sh_timer.c.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-ID: <20231026080011.156325-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 8995f1feeb6aaa001bcfbc61e868d8cb16e6a179
https://github.com/qemu/qemu/commit/8995f1feeb6aaa001bcfbc61e868d8cb16e6a179
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add the CAN documentation file to the CAN section
Add can.rst to the corresponding section in MAINTAINERS, so that
the maintainers get CC:-ed on corresponding patches.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Message-ID: <20231027060931.242491-1-thuth@redhat.com>
[PMD: Fixed typo in subject]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f5c5e7d9dba372df3ef02ee828c5041c95ddff29
https://github.com/qemu/qemu/commit/f5c5e7d9dba372df3ef02ee828c5041c95ddff29
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: update libvirt devel mailing list address
Effective immediately, the libvirt project has moved its list off
libvir-list@redhat.com, to devel@lists.libvirt.org
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20231027095643.2842382-1-berrange@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2b531600381595214519e0598aa9ebac80e6a7e5
https://github.com/qemu/qemu/commit/2b531600381595214519e0598aa9ebac80e6a7e5
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section
These machines are the only user of the mx_pic code, so the
header (which is currently "unmaintained" according to the
MAINTAINERS file) should be added to this section.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231107102104.14342-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 51145a0d872f58a7fed32f999af39f9b10ebd38c
https://github.com/qemu/qemu/commit/51145a0d872f58a7fed32f999af39f9b10ebd38c
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add more guest-agent related files to the corresponding section
contrib/systemd/qemu-guest-agent.service, tests/data/test-qga-config
and tests/data/test-qga-os-release belong to the guest agent, so make
sure that these files are covered here, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-ID: <20231107101811.14189-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 547ec5a0a4f697323e313062fabdebefc964eb97
https://github.com/qemu/qemu/commit/547ec5a0a4f697323e313062fabdebefc964eb97
Author: Adrian Wowk <dev@adrianwowk.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/sdl2.c
Log Message:
-----------
ui/sdl2: use correct key names in win title on mac
Previously, when using the SDL2 UI on MacOS, the title bar uses incorrect
key names (such as Ctrl and Alt instead of the standard MacOS key symbols
like ⌃ and ⌥). This commit changes sdl_update_caption in ui/sdl2.c to
use the correct symbols when compiling for MacOS (CONFIG_DARWIN is
defined).
Unfortunately, standard Mac keyboards do not include a "Right-Ctrl" key,
so in the case that the SDL grab mode is set to HOT_KEY_MOD_RCTRL, the
default text is still used.
Signed-off-by: Adrian Wowk <dev@adrianwowk.com>
Acked-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231030024119.28342-1-dev@adrianwowk.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 95a40c44501b5e3b8d1922ea37f30142981b2b34
https://github.com/qemu/qemu/commit/95a40c44501b5e3b8d1922ea37f30142981b2b34
Author: Zongmin Zhou <min_halo@163.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M dump/dump.c
Log Message:
-----------
dump: Add close fd on error return to avoid resource leak
Reported-by: Coverity CID 1523842 (RESOURCE_LEAK)
Fixes: e6549197f7 ("dump: Add command interface for kdump-raw formats")
Signed-off-by: Zongmin Zhou <zhouzongmin@kylinos.cn>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231107024417.585475-1-min_halo@163.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e158f8e92df5782f41b61adb6fa43bed70879f7f
https://github.com/qemu/qemu/commit/e158f8e92df5782f41b61adb6fa43bed70879f7f
Author: Markus Armbruster <armbru@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M crypto/rsakey-builtin.c.inc
Log Message:
-----------
crypto/rsakey-builtin.c.inc: Clean up two error paths
When qcrypto_builtin_rsa_public_key_parse() is about to fail, but no
error has been set, it makes one up. Actually, there's just one way
to fail without setting an error. Set it there instead.
Same for qcrypto_builtin_rsa_private_key_parse().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 9c636e0f9644d0778c16f460e0645e2352f42a7a
https://github.com/qemu/qemu/commit/9c636e0f9644d0778c16f460e0645e2352f42a7a
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M io/net-listener.c
Log Message:
-----------
io: Stop appending -listen to net listeners
All callers of qio_net_listener_set_name() already add some sort of
"listen" or "listener" suffix.
For intance, we currently have "migration-socket-listener-listen" and
"vnc-listen-listen" as ioc names.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 5b4edd7230cd3010a05c6bc34c5465215275b12a
https://github.com/qemu/qemu/commit/5b4edd7230cd3010a05c6bc34c5465215275b12a
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M audio/wavaudio.c
Log Message:
-----------
audio: don't abort on f32 audio format in wav backend
Print a debug message as is done for other unsupported audio formats
to give the user the chance to understand their mistake.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: cc9118f240e125d33d9d0d31dcd0fa017683b042
https://github.com/qemu/qemu/commit/cc9118f240e125d33d9d0d31dcd0fa017683b042
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: update libvirt devel mailing list address
Effective immediately, the libvirt project has moved its list off
libvir-list@redhat.com, to devel@lists.libvirt.org
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: 97d3b2cd36d46b033a5f4219084ab929a5bac9d3
https://github.com/qemu/qemu/commit/97d3b2cd36d46b033a5f4219084ab929a5bac9d3
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/pci-host/Kconfig
A hw/pci-host/articia.c
M hw/pci-host/meson.build
A include/hw/pci-host/articia.h
Log Message:
-----------
hw/pci-host: Add emulation of Mai Logic Articia S
The Articia S is a generic chipset supporting several different CPUs
that were among others used on some PPC boards. This is a minimal
emulation of the parts needed for emulating the AmigaOne board.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID:
<83822787431701cf4d460298d3e3845f362e5da1.1698406922.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3e7ebf58e808afb422e5000bbf77dc4aa88dd6e6
https://github.com/qemu/qemu/commit/3e7ebf58e808afb422e5000bbf77dc4aa88dd6e6
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M scripts/cpu-x86-uarch-abi.py
Log Message:
-----------
scripts/cpu-x86-uarch-abi.py: Fix parameter error of cmd
When run this script, there's the error:
python3 scripts/cpu-x86-uarch-abi.py /tmp/qmp
Traceback (most recent call last):
File "/path-to-qemu/qemu/scripts/cpu-x86-uarch-abi.py", line 96, in <module>
cpu = shell.cmd("query-cpu-model-expansion",
TypeError: QEMUMonitorProtocol.cmd() takes 2 positional arguments but 3 were
given
Commit 7f521b023bc28 ("scripts/cpu-x86-uarch-abi.py: use .command()
instead of .cmd()") converts the the original .cmd() to .command()
(which was later renamed to "cmd" to replace the original one).
But the new .cmd() only accepts typing.Mapping as the parameter instead
of typing.Dict (see _qmp.execute()).
Change the paremeters of "query-cpu-model-expansion" to typing.Mapping
format to fix this error.
Fixes: 7f521b023bc28 ("scripts/cpu-x86-uarch-abi.py: use .command() instead of
.cmd()")
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: e416fd79d5d12889266259e6df6ff0d22f6f6d6b
https://github.com/qemu/qemu/commit/e416fd79d5d12889266259e6df6ff0d22f6f6d6b
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add artist.c to the hppa machine section
The artist graphics adapter is only used by the hppa machine, so
let's add this file to the corresponding section.
Message-ID: <20231107103044.15089-1-thuth@redhat.com>
Acked-by: Helge Deller <deller@gmx.de>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 645198d58b6e1236373f5375fdaa8e3b15519108
https://github.com/qemu/qemu/commit/645198d58b6e1236373f5375fdaa8e3b15519108
Author: Thomas Huth <huth@tuxfamily.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/avocado/machine_m68k_nextcube.py
M tests/avocado/tesseract_utils.py
Log Message:
-----------
tests/avocado: Allow newer versions of tesseract in the nextcube test
Current Linux distros ship version 5 of the tesseract OCR software,
so the nextcube screen test is ignored there. Let's make the check
more flexible to allow newer versions, too, and remove the old v3
test since most Linux distros don't ship this version anymore.
Message-ID: <20231101204323.35533-1-huth@tuxfamily.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Commit: 81f993828bce9a9afd72da17b7672cb8bd121e63
https://github.com/qemu/qemu/commit/81f993828bce9a9afd72da17b7672cb8bd121e63
Author: Heiko Carstens <hca@linux.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/hw/s390x/sclp.h
Log Message:
-----------
s390/sclp: fix SCLP facility map
Qemu's SCLP implementation incorrectly reports that it supports CPU
reconfiguration. If a guest issues a CPU reconfiguration request it
is rejected as invalid command.
Fix the SCLP_HAS_CPU_INFO mask, and remove the unused
SCLP_CMDW_CONFIGURE_CPU and SCLP_CMDW_DECONFIGURE_CPU defines.
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Halil Pasic <pasic@linux.ibm.com>
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
Message-ID: <20231024100703.929679-1-hca@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: ad63e6d69326a2db0ed5ab8c9277b5b504a919a8
https://github.com/qemu/qemu/commit/ad63e6d69326a2db0ed5ab8c9277b5b504a919a8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/s390x/cpu_models.c
Log Message:
-----------
target/s390x/cpu_models: Use 'first_cpu' in s390_get_feat_block()
We already have a global 'first_cpu' variable storing a pointer
to the first CPU, no need to use a static one.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231030093150.65297-1-philmd@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: aba2ec341c6d20c8dc3e6ecf87fa7c1a71e30c1e
https://github.com/qemu/qemu/commit/aba2ec341c6d20c8dc3e6ecf87fa7c1a71e30c1e
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Fix CLC corrupting cc_src
CLC updates cc_src before accessing the second operand; if the latter
is inaccessible, the former ends up containing a bogus value.
Fix by reading cc_src into a temporary first.
Fixes: 4f7403d52b1c ("target-s390: Convert CLC")
Closes: https://gitlab.com/qemu-project/qemu/-/issues/1865
Cc: qemu-stable@nongnu.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-ID: <20231106093605.1349201-2-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 43fecbe7a53fe8e5a6aff0d6471b1cc624e26b51
https://github.com/qemu/qemu/commit/43fecbe7a53fe8e5a6aff0d6471b1cc624e26b51
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/clc.c
Log Message:
-----------
tests/tcg/s390x: Test CLC with inaccessible second operand
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231106093605.1349201-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: bea402482a8c94389638cbd3d7fe3963fb317f4c
https://github.com/qemu/qemu/commit/bea402482a8c94389638cbd3d7fe3963fb317f4c
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/s390x/tcg/insn-data.h.inc
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Fix LAALG not updating cc_src
LAALG uses op_laa() and wout_addu64(). The latter expects cc_src to be
set, but the former does not do it. This can lead to assertion failures
if something sets cc_src to neither 0 nor 1 before.
Fix by introducing op_laa_addu64(), which sets cc_src, and using it for
LAALG.
Fixes: 4dba4d6fef61 ("target/s390x: Use atomic operations for LOAD AND OP")
Cc: qemu-stable@nongnu.org
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231106093605.1349201-4-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: ebc14107f1f3ac1db13132cd28cf94adcd38e5d7
https://github.com/qemu/qemu/commit/ebc14107f1f3ac1db13132cd28cf94adcd38e5d7
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/laalg.c
Log Message:
-----------
tests/tcg/s390x: Test LAALG with negative cc_src
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231106093605.1349201-5-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d7e61d6b39cd3d644bc33bcb517d24fca479704c
https://github.com/qemu/qemu/commit/d7e61d6b39cd3d644bc33bcb517d24fca479704c
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/add-logical-with-carry.c
Log Message:
-----------
tests/tcg/s390x: Test ADD LOGICAL WITH CARRY
Add a test that tries different combinations of ADD LOGICAL WITH
CARRY instructions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20231106093605.1349201-6-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 3e19fbc0c51a62d0c021e1ae768da0df64855927
https://github.com/qemu/qemu/commit/3e19fbc0c51a62d0c021e1ae768da0df64855927
Author: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/s390x/kvm/stsi-topology.c
Log Message:
-----------
target/s390x/cpu topology: Fix ordering and creation of TLEs
In case of horizontal polarization entitlement has no effect on
ordering.
Moreover, since the comparison is used to insert CPUs at the correct
position in the TLE list, this affects the creation of TLEs and now
correctly collapses horizontally polarized CPUs into one TLE.
Fixes: f4f54b582f ("target/s390x/cpu topology: handle STSI(15) and build the
SYSIB")
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231027163637.3060537-1-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d9656f860a38f83efc9710c515eab6a5b015134c
https://github.com/qemu/qemu/commit/d9656f860a38f83efc9710c515eab6a5b015134c
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M configs/devices/ppc-softmmu/default.mak
M hw/ppc/Kconfig
A hw/ppc/amigaone.c
M hw/ppc/meson.build
Log Message:
-----------
hw/ppc: Add emulation of AmigaOne XE board
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware
with patches to support AmigaOS and is very similar to pegasos2 so can
be easily emulated sharing most code with pegasos2. The reason to
emulate it is that AmigaOS comes in different versions for AmigaOne
and PegasosII which only have drivers for one machine and firmware so
these only run on the specific machine. Adding this board allows
another AmigaOS version to be used reusing already existing peagasos2
emulation. (The AmigaOne was the first of these boards so likely most
widespread which then inspired Pegasos that was later replaced with
PegasosII due to problems with Articia S, so these have a lot of
similarity. Pegasos mainly ran MorphOS while the PegasosII version of
AmigaOS was added later and therefore less common than the AmigaOne
version.)
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID:
<804935e7a5921548d630576159ae2c758fe6e275.1699382232.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f46f8e0f37e0ecf68c7ef516bcd74640223a192e
https://github.com/qemu/qemu/commit/f46f8e0f37e0ecf68c7ef516bcd74640223a192e
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A tests/avocado/ppc_amiga.py
Log Message:
-----------
tests/avocado: Add test for amigaone board
Add an avocado test for the amigaone board that tests it with the
firmware.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID:
<b1a0246840fcff1fe6bbd8685e2474a9231b34c5.1698406922.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 263b81ee15af05cbb2ad284aadabb0981a19c941
https://github.com/qemu/qemu/commit/263b81ee15af05cbb2ad284aadabb0981a19c941
Author: Cédric Le Goater <clg@kaod.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ppc/meson.build
A hw/ppc/pnv_i2c.c
A include/hw/ppc/pnv_i2c.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Add an I2C controller model
The more recent IBM power processors have an embedded I2C
controller that is accessible by software via the XSCOM
address space.
Each instance of the I2C controller is capable of controlling
multiple I2C buses (one at a time). Prior to beginning a
transaction on an I2C bus, the bus must be selected by writing
the port number associated with the bus into the PORT_NUM
field of the MODE register. Once an I2C bus is selected,
the status of the bus can be determined by reading the
Status and Extended Status registers.
I2C bus transactions can be started by writing a command to
the Command register and reading/writing data from/to the
FIFO register.
Not supported :
. 10 bit I2C addresses
. Multimaster
. Slave
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[milesg: Split wiring to powernv9 into its own commit]
[milesg: Added more detail to commit message]
[milesg: Added SPDX Licensed Identifier to new files]
[milesg: updated copyright dates]
[milesg: Added use of g_autofree]
[milesg: Added NULL check after pnv_i2c_get_bus]
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <20231016222013.3739530-2-milesg@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5f0661215454959e98f69e7d3933e793d884282d
https://github.com/qemu/qemu/commit/5f0661215454959e98f69e7d3933e793d884282d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
ppc/pnv: Connect I2C controller model to powernv9 chip
Wires up three I2C controller instances to the powernv9 chip
XSCOM address space.
Each controller instance is wired up to a single I2C bus of
its own. No other I2C devices are connected to the buses
at this time.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[milesg: Split wiring from addition of model itself]
[milesg: Added new commit message]
[milesg: Moved hardcoded attributes into PnvChipClass]
[milesg: Removed TODO comment for I2C]
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <20231016222013.3739530-3-milesg@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1ceda19c28a11cf51ca5f670c50934c66b7785bd
https://github.com/qemu/qemu/commit/1ceda19c28a11cf51ca5f670c50934c66b7785bd
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv_chip.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Connect PNV I2C controller to powernv10
Wires up four I2C controller instances to the powernv10 chip
XSCOM address space.
Each controller instance is wired up to two I2C buses of
its own. No other I2C devices are connected to the buses
at this time.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20231017221434.810363-1-milesg@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0d1dcb0bb168ee876445a7c94d753aee8d8a2e15
https://github.com/qemu/qemu/commit/0d1dcb0bb168ee876445a7c94d753aee8d8a2e15
Author: Glenn Miles <milesg@linux.vnet.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
ppc/pnv: Fix number of I2C engines and ports for power9/10
Power9 is supposed to have 4 PIB-connected I2C engines with the
following number of ports on each engine:
0: 2
1: 13
2: 2
3: 2
Power10 also has 4 engines but has the following number of ports
on each engine:
0: 14
1: 14
2: 2
3: 16
Current code assumes that they all have the same (maximum) number.
This can be a problem if software expects to see a certain number
of ports present (Power Hypervisor seems to care).
Fixed this by adding separate tables for power9 and power10 that
map the I2C controller number to the number of I2C buses that should
be attached for that engine.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Message-ID: <20231025152714.956664-1-milesg@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fcc63904b5e3622e6495b923a9e0e7d10cc78c5c
https://github.com/qemu/qemu/commit/fcc63904b5e3622e6495b923a9e0e7d10cc78c5c
Author: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M include/hw/pci-host/pnv_phb4.h
M include/hw/pci-host/pnv_phb4_regs.h
Log Message:
-----------
hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-ID: <20231016175948.10869-1-saif.abrar@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5bf4ceec109289356f50f69bf277c99b045182e7
https://github.com/qemu/qemu/commit/5bf4ceec109289356f50f69bf277c99b045182e7
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ppc/spapr_rtas.c
R include/hw/ppc/spapr_rtas.h
Log Message:
-----------
ppc: qtest already exports qtest_rtas_call()
Having two functions with the same name is a bad idea. As spapr only
uses the function locally, made it static.
When you compile with clang, you get this compilation error:
/usr/bin/ld: tests/qtest/libqos/libqos.fa.p/.._libqtest.c.o: in function
`qtest_rtas_call':
/scratch/qemu/clang/full/all/../../../../../mnt/code/qemu/full/tests/qtest/libqtest.c:1195:
multiple definition of `qtest_rtas_call';
libqemu-ppc64-softmmu.fa.p/hw_ppc_spapr_rtas.c.o:/scratch/qemu/clang/full/all/../../../../../mnt/code/qemu/full/hw/ppc/spapr_rtas.c:536:
first defined here
clang-16: error: linker command failed with exit code 1 (use -v to see
invocation)
ninja: build stopped: subcommand failed.
make: *** [Makefile:162: run-ninja] Error 1
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20231030163834.4638-1-quintela@redhat.com>
[dhb: remove 'spapr_rtas.h' include from spapr_rtas.c]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ed1d873caa93fde443b14369309cdd4366d4ca08
https://github.com/qemu/qemu/commit/ed1d873caa93fde443b14369309cdd4366d4ca08
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-08 (Wed, 08 Nov 2023)
Changed paths:
M MAINTAINERS
M accel/stubs/tcg-stub.c
M accel/tcg/cputlb.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/translate-all.c
M accel/tcg/user-exec-stub.c
M bsd-user/main.c
M cpu-common.c
M cpu-target.c
M dump/dump.c
M hw/arm/Kconfig
M hw/core/cpu-common.c
M hw/core/loader.c
M hw/i2c/pmbus_device.c
M hw/ide/core.c
M hw/isa/i82378.c
M hw/ppc/e500.c
M hw/s390x/css.c
M hw/s390x/sclp.c
M hw/sd/aspeed_sdhci.c
M hw/sd/bcm2835_sdhost.c
M hw/sd/cadence_sdhci.c
M hw/sd/core.c
M hw/sd/npcm7xx_sdhci.c
M hw/sd/pl181.c
M hw/sd/pxa2xx_mmci.c
M hw/sd/sd.c
M hw/sd/sdhci-pci.c
M hw/sd/ssi-sd.c
M hw/sensor/Kconfig
A hw/sensor/adm1266.c
M hw/sensor/meson.build
M include/exec/cpu-common.h
M include/exec/tb-flush.h
M include/hw/core/cpu.h
M include/hw/i2c/pmbus_device.h
M include/hw/i386/topology.h
M include/hw/loader.h
M include/hw/ppc/ppc.h
M include/hw/s390x/css.h
M include/hw/s390x/sclp.h
M include/sysemu/accel-ops.h
M include/sysemu/kvm.h
M linux-user/main.c
M plugins/core.c
M system/cpus.c
M system/vl.c
M target/alpha/cpu-qom.h
M target/alpha/cpu.c
M target/alpha/cpu.h
M target/arm/cpu-qom.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/internals.h
M target/avr/cpu-qom.h
M target/avr/cpu.c
M target/avr/cpu.h
M target/cris/cpu-qom.h
M target/cris/cpu.c
M target/cris/cpu.h
A target/hexagon/cpu-qom.h
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hppa/cpu-qom.h
M target/hppa/cpu.h
M target/i386/cpu-qom.h
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/hvf/hvf.c
M target/i386/hvf/x86_emu.c
M target/i386/hvf/x86_emu.h
M target/i386/kvm/kvm-cpu.c
M target/i386/monitor.c
A target/loongarch/cpu-qom.h
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/m68k/cpu-qom.h
M target/m68k/cpu.c
M target/m68k/cpu.h
M target/microblaze/cpu-qom.h
M target/microblaze/cpu.h
M target/mips/cpu-qom.h
M target/mips/cpu.h
M target/mips/tcg/msa.decode
M target/mips/tcg/tx79.decode
A target/nios2/cpu-qom.h
M target/nios2/cpu.c
M target/nios2/cpu.h
A target/openrisc/cpu-qom.h
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/internal.h
R target/ppc/kvm-stub.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/meson.build
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/internals.h
M target/rx/cpu-qom.h
M target/rx/cpu.c
M target/rx/cpu.h
M target/s390x/cpu-qom.h
M target/s390x/cpu.h
M target/s390x/cpu_models.c
M target/s390x/cpu_models.h
M target/s390x/diag.c
M target/s390x/kvm/kvm.c
M target/s390x/tcg/misc_helper.c
M target/sh4/cpu-qom.h
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sparc/cpu-qom.h
M target/sparc/cpu.h
M target/tricore/cpu-qom.h
M target/tricore/cpu.c
M target/tricore/cpu.h
M target/xtensa/cpu-qom.h
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/op_helper.c
A tests/qtest/adm1266-test.c
M tests/qtest/ahci-test.c
M tests/qtest/max34451-test.c
M tests/qtest/meson.build
M tests/unit/meson.build
M tests/unit/test-seccomp.c
R tests/unit/test-x86-cpuid.c
A tests/unit/test-x86-topo.c
M tests/vm/ubuntu.aarch64
M ui/sdl2.c
Log Message:
-----------
Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging
Misc hardware patch queue
HW emulation:
- PMBus fixes and tests (Titus)
- IDE fixes and tests (Fiona)
- New ADM1266 sensor (Titus)
- Better error propagation in PCI-ISA i82378 (Philippe)
- Declare SD model QOM types using DEFINE_TYPES macro (Philippe)
Topology:
- Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)
Monitor:
- Synchronize CPU state in 'info lapic' (Dongli Zhang)
QOM:
- Have 'cpu-qom.h' target-agnostic (Philippe)
- Move ArchCPUClass definition to each target's cpu.h (Philippe)
- Call object_class_is_abstract once in cpu_class_by_name (Philippe)
UI:
- Use correct key names in titles on MacOS / SDL2 (Adrian)
MIPS:
- Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)
Nios2:
- Create IRQs *after* vCPU is realized (Philippe)
PPC:
- Restrict KVM objects to system emulation (Philippe)
- Move target-specific definitions out of 'cpu-qom.h' (Philippe)
S390X:
- Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)
X86:
- HVF & KVM cleanups (Philippe)
Various targets:
- Use env_archcpu() to optimize (Philippe)
Misc:
- Few global variable shadowing removed (Philippe)
- Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe)
- Remove few more 'softmmu' mentions (Philippe)
- Fix and cleanup in vl.c (Akihiko & Marc-André)
- Resource leak fix in dump (Zongmin Zhou)
- MAINTAINERS updates (Thomas, Daniel)
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits)
dump: Add close fd on error return to avoid resource leak
ui/sdl2: use correct key names in win title on mac
MAINTAINERS: Add more guest-agent related files to the corresponding section
MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section
MAINTAINERS: update libvirt devel mailing list address
MAINTAINERS: Add the CAN documentation file to the CAN section
MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section
hw/sd: Declare QOM types using DEFINE_TYPES() macro
hw/i2c: pmbus: reset page register for out of range reads
hw/i2c: pmbus: immediately clear faults on request
tests/qtest: add tests for ADM1266
hw/sensor: add ADM1266 device model
hw/i2c: pmbus: add VCAP register
hw/i2c: pmbus: add fan support
hw/i2c: pmbus: add vout mode bitfields
hw/i2c: pmbus add support for block receive
tests/qtest: ahci-test: add test exposing reset issue with pending callback
hw/ide: reset: cancel async DMA operation before resetting state
hw/cpu: Update the comments of nr_cores and nr_dies
system/cpus: Fix CPUState.nr_cores' calculation
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 44ad47b75877e10a750adb17174539ddfeae3963
https://github.com/qemu/qemu/commit/44ad47b75877e10a750adb17174539ddfeae3963
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-08 (Wed, 08 Nov 2023)
Changed paths:
M MAINTAINERS
M include/hw/s390x/sclp.h
M target/s390x/cpu_models.c
M target/s390x/kvm/stsi-topology.c
M target/s390x/tcg/insn-data.h.inc
M target/s390x/tcg/translate.c
M tests/avocado/machine_m68k_nextcube.py
M tests/avocado/tesseract_utils.py
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/add-logical-with-carry.c
A tests/tcg/s390x/clc.c
A tests/tcg/s390x/laalg.c
Log Message:
-----------
Merge tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu into
staging
* Fix s390x CPU reconfiguration information in the SCLP facility map
* Fix condition code problem in the CLC and LAALG instruction
* Fix ordering of the new s390x topology list entries
* Add some more files to the MAINTAINERS file
* Allow newer versions of Tesseract in the m68k nextcube test
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 08 Nov 2023 02:30:35 HKT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu:
target/s390x/cpu topology: Fix ordering and creation of TLEs
tests/tcg/s390x: Test ADD LOGICAL WITH CARRY
tests/tcg/s390x: Test LAALG with negative cc_src
target/s390x: Fix LAALG not updating cc_src
tests/tcg/s390x: Test CLC with inaccessible second operand
target/s390x: Fix CLC corrupting cc_src
target/s390x/cpu_models: Use 'first_cpu' in s390_get_feat_block()
s390/sclp: fix SCLP facility map
tests/avocado: Allow newer versions of tesseract in the nextcube test
MAINTAINERS: Add artist.c to the hppa machine section
MAINTAINERS: Add the virtio-gpu documentation to the corresponding section
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: f09744ddc2424bc6a76702e1951a8d24917062d6
https://github.com/qemu/qemu/commit/f09744ddc2424bc6a76702e1951a8d24917062d6
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-08 (Wed, 08 Nov 2023)
Changed paths:
M audio/wavaudio.c
M crypto/rsakey-builtin.c.inc
M io/net-listener.c
M scripts/cpu-x86-uarch-abi.py
Log Message:
-----------
Merge tag 'misc-fixes-pull-request' of https://gitlab.com/berrange/qemu into
staging
* Print error with f32 audio format in wav backend instead of abort
* Drop redundant listener name suffix
* Update libvirt mailing list address
* Cleanup RSA key error paths
* Fix CPU uarch ABI script QMP command calling
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# gpg: Signature made Wed 08 Nov 2023 03:07:54 HKT
# gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full]
# gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full]
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
* tag 'misc-fixes-pull-request' of https://gitlab.com/berrange/qemu:
scripts/cpu-x86-uarch-abi.py: Fix parameter error of cmd
MAINTAINERS: update libvirt devel mailing list address
audio: don't abort on f32 audio format in wav backend
io: Stop appending -listen to net listeners
crypto/rsakey-builtin.c.inc: Clean up two error paths
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: a3c3aaa846ad61b801e7196482dcf4afb8ba34e4
https://github.com/qemu/qemu/commit/a3c3aaa846ad61b801e7196482dcf4afb8ba34e4
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-08 (Wed, 08 Nov 2023)
Changed paths:
M MAINTAINERS
M configs/devices/ppc-softmmu/default.mak
M hw/pci-host/Kconfig
A hw/pci-host/articia.c
M hw/pci-host/meson.build
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/Kconfig
A hw/ppc/amigaone.c
M hw/ppc/meson.build
M hw/ppc/pnv.c
A hw/ppc/pnv_i2c.c
M hw/ppc/spapr_rtas.c
A include/hw/pci-host/articia.h
M include/hw/pci-host/pnv_phb4.h
M include/hw/pci-host/pnv_phb4_regs.h
M include/hw/ppc/pnv_chip.h
A include/hw/ppc/pnv_i2c.h
M include/hw/ppc/pnv_xscom.h
R include/hw/ppc/spapr_rtas.h
A tests/avocado/ppc_amiga.py
Log Message:
-----------
Merge tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2023-11-07:
This queue, the last one before the 8.2 feature freeze, has miscellanous
changes that includes new PowerNV features and the new AmigaONE XE
board.
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 08 Nov 2023 04:46:49 HKT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu:
ppc: qtest already exports qtest_rtas_call()
hw/pci-host: Update PHB5 XSCOM registers
ppc/pnv: Fix number of I2C engines and ports for power9/10
ppc/pnv: Connect PNV I2C controller to powernv10
ppc/pnv: Connect I2C controller model to powernv9 chip
ppc/pnv: Add an I2C controller model
tests/avocado: Add test for amigaone board
hw/ppc: Add emulation of AmigaOne XE board
hw/pci-host: Add emulation of Mai Logic Articia S
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/462ad017ed76...a3c3aaa846ad