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[Qemu-commits] [qemu/qemu] ce32a9: target/hppa: Update to SeaBIOS-hppa v
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] ce32a9: target/hppa: Update to SeaBIOS-hppa version 10 |
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Date: |
Fri, 20 Oct 2023 05:24:57 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: ce32a9e9912fd091d5ca7d604ae367b9d705eb87
https://github.com/qemu/qemu/commit/ce32a9e9912fd091d5ca7d604ae367b9d705eb87
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-14 (Sat, 14 Oct 2023)
Changed paths:
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
Log Message:
-----------
target/hppa: Update to SeaBIOS-hppa version 10
Enhancements:
- Initial support for 64-bit CPUs with Astro/Elroy (e.g. C3700
workstation)
- USB support (OHCI)
- better PCI support
- esp-scsi fixes from Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: a536f564d3281014478ef100a0cd1204a47eb9e1
https://github.com/qemu/qemu/commit/a536f564d3281014478ef100a0cd1204a47eb9e1
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Require at least SeaBIOS-hppa version 10
The new SeaBIOS-hppa version 10 includes initial support
for PA2.0 CPUs.
Additionally update copyright and drop commented-out code.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 2e90154eea04c25bd30042ba4d6a9056e781437f
https://github.com/qemu/qemu/commit/2e90154eea04c25bd30042ba4d6a9056e781437f
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/net/tulip.c
M include/hw/pci/pci_ids.h
Log Message:
-----------
pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: a1e6a5c46219bada2c7b932748527553b36559ae
https://github.com/qemu/qemu/commit/a1e6a5c46219bada2c7b932748527553b36559ae
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/input/lasips2.c
Log Message:
-----------
lasips2: LASI PS/2 devices are not user-createable
Those PS/2 ports are created with the LASI controller when
a 32-bit PA-RISC machine is created.
Mark them not user-createable to avoid showing them in
the qemu device list.
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: qemu-stable@nongnu.org
Commit: 0e6bff0d43bf04c6e7a16c2775879816ca056b3d
https://github.com/qemu/qemu/commit/0e6bff0d43bf04c6e7a16c2775879816ca056b3d
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Use iovec for vhost_vdpa_net_cvq_add()
Next patches in this series will no longer perform an
immediate poll and check of the device's used buffers
for each CVQ state load command. Consequently, there
will be multiple pending buffers in the shadow VirtQueue,
making it a must for every control command to have its
own buffer.
To achieve this, this patch refactor vhost_vdpa_net_cvq_add()
to accept `struct iovec`, which eliminates the coupling of
control commands to `s->cvq_cmd_out_buffer` and `s->status`,
allowing them to use their own buffer.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<8a328f146fb043f34edb75ba6d043d2d6de88f99.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 327dedb8df91f57ef917ab5b5db519146ee6f08b
https://github.com/qemu/qemu/commit/327dedb8df91f57ef917ab5b5db519146ee6f08b
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load()
Next patches in this series will refactor vhost_vdpa_net_load_cmd()
to iterate through the control commands shadow buffers, allowing QEMU
to send CVQ state load commands in parallel at device startup.
Considering that QEMU always forwards the CVQ command serialized
outside of vhost_vdpa_net_load(), it is more elegant to send the
CVQ commands directly without invoking vhost_vdpa_net_load_*() helpers.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<254f0618efde7af7229ba4fdada667bb9d318991.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 24e59cfe0cb53416b06c2c117bc22ff22dc54df3
https://github.com/qemu/qemu/commit/24e59cfe0cb53416b06c2c117bc22ff22dc54df3
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Check device ack in vhost_vdpa_net_load_rx_mode()
Considering that vhost_vdpa_net_load_rx_mode() is only called
within vhost_vdpa_net_load_rx() now, this patch refactors
vhost_vdpa_net_load_rx_mode() to include a check for the
device's ack, simplifying the code and improving its maintainability.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<68811d52f96ae12d68f0d67d996ac1642a623943.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a864a3219d7e63569583d204c12bff2a0f90463e
https://github.com/qemu/qemu/commit/a864a3219d7e63569583d204c12bff2a0f90463e
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add()
This patch moves vhost_svq_poll() to the caller of
vhost_vdpa_net_cvq_add() and introduces a helper funtion.
By making this change, next patches in this series is
able to refactor vhost_vdpa_net_load_x() only to delay
the polling and checking process until either the SVQ
is full or control commands shadow buffers are full.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<196cadb55175a75275660c6634a538289f027ae3.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1d7e2a8fd4996fdb20d74fce41fe897311f3b06a
https://github.com/qemu/qemu/commit/1d7e2a8fd4996fdb20d74fce41fe897311f3b06a
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Introduce cursors to vhost_vdpa_net_loadx()
This patch introduces two new arugments, `out_cursor`
and `in_cursor`, to vhost_vdpa_net_loadx(). Addtionally,
it includes a helper function
vhost_vdpa_net_load_cursor_reset() for resetting these
cursors.
Furthermore, this patch refactors vhost_vdpa_net_load_cmd()
so that vhost_vdpa_net_load_cmd() prepares buffers
for the device using the cursors arguments, instead
of directly accesses `s->cvq_cmd_out_buffer` and
`s->status` fields.
By making these change, next patches in this series
can refactor vhost_vdpa_net_load_cmd() directly to
iterate through the control commands shadow buffers,
allowing QEMU to send CVQ state load commands in parallel
at device startup.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<1c6516e233a14cc222f0884e148e4e1adceda78d.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 99d6a32469debf1a48921125879b614d15acfb7a
https://github.com/qemu/qemu/commit/99d6a32469debf1a48921125879b614d15acfb7a
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
M hw/virtio/vhost-shadow-virtqueue.h
Log Message:
-----------
vhost: Expose vhost_svq_available_slots()
Next patches in this series will delay the polling
and checking of buffers until either the SVQ is
full or control commands shadow buffers are full,
no longer perform an immediate poll and check of
the device's used buffers for each CVQ state load command.
To achieve this, this patch exposes
vhost_svq_available_slots(), allowing QEMU to know
whether the SVQ is full.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<25938079f0bd8185fd664c64e205e629f7a966be.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: acec5f685c7ad6bd3c9bb9a57d4e509160480376
https://github.com/qemu/qemu/commit/acec5f685c7ad6bd3c9bb9a57d4e509160480376
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Send cvq state load commands in parallel
This patch enables sending CVQ state load commands
in parallel at device startup by following steps:
* Refactor vhost_vdpa_net_load_cmd() to iterate through
the control commands shadow buffers. This allows different
CVQ state load commands to use their own unique buffers.
* Delay the polling and checking of buffers until either
the SVQ is full or control commands shadow buffers are full.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1578
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<9350f32278e39f7bce297b8f2d82dac27c6f8c9a.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a6c5d159ce8e2f8e4cf5a0cd58de12167dd72311
https://github.com/qemu/qemu/commit/a6c5d159ce8e2f8e4cf5a0cd58de12167dd72311
Author: John Snow <jsnow@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M scripts/qapi/gen.py
M scripts/qapi/parser.py
Log Message:
-----------
qapi: re-establish linting baseline
Some very minor housekeeping to make the linters happy once more.
Signed-off-by: John Snow <jsnow@redhat.com>
Message-ID: <20231004230532.3002201-4-jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: 0a59c02b0c4fd4591b010410bdfd423b9e259b03
https://github.com/qemu/qemu/commit/0a59c02b0c4fd4591b010410bdfd423b9e259b03
Author: Markus Armbruster <armbru@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M qapi/compat.json
Log Message:
-----------
qapi: Belatedly update CompatPolicy documentation for unstable
Commit 57df0dff1a1 (qapi: Extend -compat to set policy for unstable
interfaces) neglected to update the "Limitation" paragraph to mention
feature 'unstable' in addition to feature 'deprecated'. Do that now.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20231009110449.4015601-1-armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e307a8174bb876ba0ac91cf1c2ced01ec4374af9
https://github.com/qemu/qemu/commit/e307a8174bb876ba0ac91cf1c2ced01ec4374af9
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M scripts/qapi/schema.py
Log Message:
-----------
qapi: provide a friendly string representation of QAPI classes
If printing a QAPI schema object for debugging we get the classname and
a hex value for the instance:
<qapi.schema.QAPISchemaEnumType object at 0x7f0ab4c2dad0>
<qapi.schema.QAPISchemaObjectType object at 0x7f0ab4c2dd90>
<qapi.schema.QAPISchemaArrayType object at 0x7f0ab4c2df90>
With this change we instead get the classname and the human friendly
name of the QAPI type instance:
<QAPISchemaEnumType:CpuS390State at 0x7f0ab4c2dad0>
<QAPISchemaObjectType:CpuInfoS390 at 0x7f0ab4c2dd90>
<QAPISchemaArrayType:CpuInfoFastList at 0x7f0ab4c2df90>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20231018120500.2028642-1-berrange@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Conditional swapped to avoid negation]
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[Tweaked to mollify pylint]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Commit: 29ecf2de024b386acc72b53b9eb0c3559883d1b6
https://github.com/qemu/qemu/commit/29ecf2de024b386acc72b53b9eb0c3559883d1b6
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/misc/bcm2835_property.c
A include/hw/arm/raspberrypi-fw-defs.h
R include/hw/misc/raspberrypi-fw-defs.h
Log Message:
-----------
hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
The file is obviously related to the raspberrypi machine, so
it should reside in hw/arm/ instead of hw/misc/. And while we're
at it, also adjust the wildcard in MAINTAINERS so that it covers
this file, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231012073458.860187-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 85c90d45f6bd0d931af5ff7cc37a8a34ab285489
https://github.com/qemu/qemu/commit/85c90d45f6bd0d931af5ff7cc37a8a34ab285489
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M include/hw/arm/exynos4210.h
M target/arm/cpu-qom.h
Log Message:
-----------
hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'
struct arm_boot_info is declared in "hw/arm/boot.h".
By including the correct header we don't need to declare
it again in "target/arm/cpu-qom.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231013130214.95742-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 213bf5c1613e924f905f2cf9499dcf909db54e3e
https://github.com/qemu/qemu/commit/213bf5c1613e924f905f2cf9499dcf909db54e3e
Author: Tong Ho <tong.ho@amd.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/nvram/xlnx-bbram.c
Log Message:
-----------
xlnx-bbram: hw/nvram: Remove deprecated device reset
This change implements the ResettableClass interface for the device.
Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231003052345.199725-1-tong.ho@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7667b51524c58c73f4fa3ed891bfdfeb870d05be
https://github.com/qemu/qemu/commit/7667b51524c58c73f4fa3ed891bfdfeb870d05be
Author: Tong Ho <tong.ho@amd.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/nvram/xlnx-zynqmp-efuse.c
Log Message:
-----------
xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
This change implements the ResettableClass interface for the device.
Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20231004055713.324009-1-tong.ho@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 51244b5911483d12a4cde26b1facd19c8600751d
https://github.com/qemu/qemu/commit/51244b5911483d12a4cde26b1facd19c8600751d
Author: Tong Ho <tong.ho@amd.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/nvram/xlnx-versal-efuse-ctrl.c
Log Message:
-----------
xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
This change implements the ResettableClass interface for the device.
Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20231004055339.323833-1-tong.ho@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b65b4b7ae3c873dc2f8f4ce65ea5cedc45be3938
https://github.com/qemu/qemu/commit/b65b4b7ae3c873dc2f8f4ce65ea5cedc45be3938
Author: Tong Ho <tong.ho@amd.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M include/hw/nvram/xlnx-bbram.h
Log Message:
-----------
xlnx-bbram: hw/nvram: Use dot in device type name
This replaces the comma (,) to dot (.) in the device type name
so the name can be used with the 'driver=' command line option.
Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20231003052139.199665-1-tong.ho@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8b01683e857a80425ea67dc44505b4983fc11a8e
https://github.com/qemu/qemu/commit/8b01683e857a80425ea67dc44505b4983fc11a8e
Author: Viktor Prutyanov <viktor@daynix.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M contrib/elf2dmp/main.c
Log Message:
-----------
elf2dmp: limit print length for sign_rsds
String sign_rsds isn't terminated, so the print length must be limited.
Fixes: Coverity CID 1521598
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230930235317.11469-2-viktor@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9d9c06b144da340b9a937ed01d45a936810715be
https://github.com/qemu/qemu/commit/9d9c06b144da340b9a937ed01d45a936810715be
Author: Viktor Prutyanov <viktor@daynix.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M contrib/elf2dmp/pdb.c
Log Message:
-----------
elf2dmp: check array bounds in pdb_get_file_size
Index in file_size array must be checked against num_files, because the
entries we are looking for may be absent in the PDB.
Fixes: Coverity CID 1521597
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230930235317.11469-3-viktor@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d01448c79d89cfdc86228081b1dd1dfaf85fb4c3
https://github.com/qemu/qemu/commit/d01448c79d89cfdc86228081b1dd1dfaf85fb4c3
Author: Michal Orzel <michal.orzel@amd.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
On an attempt to access CNTPCT_EL0 from EL0 using a guest running on top
of Xen, a trap from EL2 was observed which is something not reproducible
on HW (also, Xen does not trap accesses to physical counter).
This is because gt_counter_access() checks for an incorrect bit (1
instead of 0) of CNTHCTL_EL2 if HCR_EL2.E2H is 0 and access is made to
physical counter. Refer ARM ARM DDI 0487J.a, D19.12.2:
When HCR_EL2.E2H is 0:
- EL1PCTEN, bit [0]: refers to physical counter
- EL1PCEN, bit [1]: refers to physical timer registers
Drop entire block "if (hcr & HCR_E2H) {...} else {...}" from EL0 case
and fall through to EL1 case, given that after fixing checking for the
correct bit, the handling is the same.
Fixes: 5bc8437136fb ("target/arm: Update timer access for VHE")
Signed-off-by: Michal Orzel <michal.orzel@amd.com>
Tested-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Message-id: 20230928094404.20802-1-michal.orzel@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9036e917f8357f4e5965ebfecdab5964d40e6a40
https://github.com/qemu/qemu/commit/9036e917f8357f4e5965ebfecdab5964d40e6a40
Author: Leif Lindholm <quic_llindhol@quicinc.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
{include/}hw/arm: refactor virt PPI logic
GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
As in, PPI0 is INTID16 .. PPI15 is INTID31.
Arm's Base System Architecture specification (BSA) lists the mandated and
recommended private interrupt IDs by INTID, not by PPI index. But current
definitions in virt define them by PPI index, complicating cross
referencing.
Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,
converting a PPI index to an INTID.
Resolve this by redefining the BSA-allocated PPIs by their INTIDs,
and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2419ce83fce2300e61b5e6df256caddaa07a2ae0
https://github.com/qemu/qemu/commit/2419ce83fce2300e61b5e6df256caddaa07a2ae0
Author: Leif Lindholm <quic_llindhol@quicinc.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
A include/hw/arm/bsa.h
M include/hw/arm/virt.h
Log Message:
-----------
include/hw/arm: move BSA definitions to bsa.h
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
While we're moving the definitions, sort them into numerical order,
and add the ARCH_TIMER_NS_EL2_VIRT_IRQ definition used by sbsa-ref
and which will eventually be needed by virt also.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230919090229.188092-3-quic_llindhol@quicinc.com
[PMM: Remove unused PPI_TO_INTID macro; sort numerically;
add ARCH_TIMER_NS_EL2_VIRT_IRQ]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d40ab068c07d924af5001ba4670651696ec9664e
https://github.com/qemu/qemu/commit/d40ab068c07d924af5001ba4670651696ec9664e
Author: Leif Lindholm <quic_llindhol@quicinc.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: use bsa.h for PPI definitions
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use the INTIDs defined there instead
of the PPI# used previously.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6c8b9a74bf76f4fc98246671de9acfdfa2c227c4
https://github.com/qemu/qemu/commit/6c8b9a74bf76f4fc98246671de9acfdfa2c227c4
Author: Cornelia Huck <cohuck@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M target/arm/kvm.c
M target/arm/kvm64.c
Log Message:
-----------
arm/kvm: convert to kvm_set_one_reg
We can neaten the code by switching to the kvm_set_one_reg function.
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231010142453.224369-2-cohuck@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 40d45b85e045501a3d3d3301f8554ff30adef3ee
https://github.com/qemu/qemu/commit/40d45b85e045501a3d3d3301f8554ff30adef3ee
Author: Cornelia Huck <cohuck@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M target/arm/kvm.c
M target/arm/kvm64.c
Log Message:
-----------
arm/kvm: convert to kvm_get_one_reg
We can neaten the code by switching the callers that work on a
CPUstate to the kvm_get_one_reg function.
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231010142453.224369-3-cohuck@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a530e470ea4f70d1207ef62273e43a7d178f53ac
https://github.com/qemu/qemu/commit/a530e470ea4f70d1207ef62273e43a7d178f53ac
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Permit T32 LDM with single register
For the Thumb T32 encoding of LDM, if only a single register is
specified in the register list this instruction is UNPREDICTABLE,
with the following choices:
* instruction UNDEFs
* instruction is a NOP
* instruction loads a single register
* instruction loads an unspecified set of registers
Currently we choose to UNDEF (a behaviour chosen in commit
4b222545dbf30 in 2019; previously we treated it as "load the
specified single register").
Unfortunately there is real world code out there (which shipped in at
least Android 11, 12 and 13) which incorrectly uses this
UNPREDICTABLE insn on the assumption that it does a single register
load, which is (presumably) what it happens to do on real hardware,
and is also what it does on the equivalent A32 encoding.
Revert to the pre-4b222545dbf30 behaviour of not UNDEFing
for this T32 encoding.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1799
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230927101853.39288-1-peter.maydell@linaro.org
Commit: cbaf9404f031a39342dee4d3183488a763f149e4
https://github.com/qemu/qemu/commit/cbaf9404f031a39342dee4d3183488a763f149e4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/smmuv3-internal.h
Log Message:
-----------
hw/arm/smmuv3: Update ID register bit field definitions
Update the SMMUv3 ID register bit field definitions to the
set in the most recent specification (IHI0700 F.a).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org
Commit: 27fd85d35b7bb05a7b939bf36de33b6aa68005f6
https://github.com/qemu/qemu/commit/27fd85d35b7bb05a7b939bf36de33b6aa68005f6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Sort ID register setting into field order
In smmuv3_init_regs() when we set the various bits in the ID
registers, we do this almost in order of the fields in the
registers, but not quite. Move the initialization of
SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org
Commit: 4cdd146d8bb72117b10ff22afe3a730dc4df4913
https://github.com/qemu/qemu/commit/4cdd146d8bb72117b10ff22afe3a730dc4df4913
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is
supported, so we should theoretically have implemented it as part of
the recent S2P work. Fortunately, for us the implementation is a
no-op.
This feature is about interpretation of the stage 2 page table
descriptor XN bits, which control execute permissions.
For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and
IOMMUAccessFlags) only indicate read and write; we do not distinguish
data reads from instruction reads outside the CPU proper. In the
SMMU architecture's terms, our interconnect between the client device
and the SMMU doesn't have the ability to convey the INST attribute,
and we therefore use the default value of "data" for this attribute.
We also do not support the bits in the Stream Table Entry that can
override the on-the-bus transaction attribute permissions (we do not
set SMMU_IDR1.ATTR_PERMS_OVR=1).
These two things together mean that for our implementation, it never
has to deal with transactions with the INST attribute, and so it can
correctly ignore the XN bits entirely. So we already implement
FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent
that we need to.
Advertise the presence of the feature in SMMU_IDR3.XNX.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org
Commit: 3d80bbf1f619ad1a0db85bb385ce4f5f74e4b0a3
https://github.com/qemu/qemu/commit/3d80bbf1f619ad1a0db85bb385ce4f5f74e4b0a3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/helper.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Implement FEAT_HPMN0
FEAT_HPMN0 is a small feature which defines that it is valid for
MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided
to an EL1 guest" (previously this setting was reserved). QEMU's
implementation almost gets HPMN == 0 right, but we need to fix
one check in pmevcntr_is_64_bit(). That is enough for us to
advertise the feature in the 'max' CPU.
(We don't need to make the behaviour conditional on feature
presence, because the FEAT_HPMN0 behaviour is within the range
of permitted UNPREDICTABLE behaviour for a non-FEAT_HPMN0
implementation.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230921185445.3339214-1-peter.maydell@linaro.org
Commit: 4fd79a96ea9149a7ea8fba5c0ea74ff5f9f02139
https://github.com/qemu/qemu/commit/4fd79a96ea9149a7ea8fba5c0ea74ff5f9f02139
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M target/arm/kvm64.c
Log Message:
-----------
target/arm/kvm64.c: Remove unused include
The include of hw/arm/virt.h in kvm64.c is unnecessary and also a
layering violation since the generic KVM code shouldn't need to know
anything about board-specifics. The include line is an accidental
leftover from commit 15613357ba53a4763, where we cleaned up the code
to not depend on virt board internals but forgot to also remove the
now-redundant include line.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230925110429.3917202-1-peter.maydell@linaro.org
Commit: 30722e0445908d3cf2d366d7bee69d0ae57401be
https://github.com/qemu/qemu/commit/30722e0445908d3cf2d366d7bee69d0ae57401be
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M target/arm/common-semi-target.h
Log Message:
-----------
target/arm/common-semi-target.h: Remove unnecessary boot.h include
The hw/arm/boot.h include in common-semi-target.h is not actually
needed, and it's a bit odd because it pulls a hw/arm header into a
target/arm file.
This include was originally needed because the semihosting code used
the arm_boot_info struct to get the base address of the RAM in system
emulation, to use in a (bad) heuristic for the return values for the
SYS_HEAPINFO semihosting call. We've since overhauled how we
calculate the HEAPINFO values in system emulation, and the code no
longer uses the arm_boot_info struct.
Remove the now-redundant include line, and instead directly include
the cpu-qom.h header that we were previously getting via boot.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230925112219.3919261-1-peter.maydell@linaro.org
Commit: 3a45f4f5376cad9489e1608f2e4960fd34805546
https://github.com/qemu/qemu/commit/3a45f4f5376cad9489e1608f2e4960fd34805546
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/boot.c
M target/arm/arm-powerctl.c
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
The code for powering on a CPU in arm-powerctl.c has two separate
use cases:
* emulation of a real hardware power controller
* emulation of firmware interfaces (primarily PSCI) with
CPU on/off APIs
For the first case, we only need to reset the CPU and set its
starting PC and X0. For the second case, because we're emulating the
firmware we need to ensure that it's in the state that the firmware
provides. In particular, when we reset to a lower EL than the
highest one we are emulating, we need to put the CPU into a state
that permits correct running at that lower EL. We already do a
little of this in arm-powerctl.c (for instance we set SCR_HCE to
enable the HVC insn) but we don't do enough of it. This means that
in the case where we are emulating EL3 but also providing emulated
PSCI the guest will crash when a secondary core tries to use a
feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth.
The hw/arm/boot.c code also has to support this "start guest code in
an EL that's lower than the highest emulated EL" case in order to do
direct guest kernel booting; it has all the necessary initialization
code to set the SCR_EL3 bits. Pull the relevant boot.c code out into
a separate function so we can share it between there and
arm-powerctl.c.
This refactoring has a few code changes that look like they
might be behaviour changes but aren't:
* if info->secure_boot is false and info->secure_board_setup is
true, then the old code would start the first CPU in Hyp
mode but without changing SCR.NS and NSACR.{CP11,CP10}.
This was wrong behaviour because there's no such thing
as Secure Hyp mode. The new code will leave the CPU in SVC.
(There is no board which sets secure_boot to false and
secure_board_setup to true, so this isn't a behaviour
change for any of our boards.)
* we don't explicitly clear SCR.NS when arm-powerctl.c
does a CPU-on to EL3. This was a no-op because CPU reset
will reset to NS == 0.
And some real behaviour changes:
* we no longer set HCR_EL2.RW when booting into EL2: the guest
can and should do that themselves before dropping into their
EL1 code. (arm-powerctl and boot did this differently; I
opted to use the logic from arm-powerctl, which only sets
HCR_EL2.RW when it's directly starting the guest in EL1,
because it's more correct, and I don't expect guests to be
accidentally depending on our having set the RW bit for them.)
* if we are booting a CPU into AArch32 Secure SVC then we won't
set SCR.HCE any more. This affects only the vexpress-a15 and
raspi2b machine types. Guests booting in this case will either:
- be able to set SCR.HCE themselves as part of moving from
Secure SVC into NS Hyp mode
- will move from Secure SVC to NS SVC, and won't care about
behaviour of the HVC insn
- will stay in Secure SVC, and won't care about HVC
* on an arm-powerctl CPU-on we will now set the SCR bits for
pauth/mte/sve/sme/hcx/fgt features
The first two of these are very minor and I don't expect guest
code to trip over them, so I didn't judge it worth convoluting
the code in an attempt to keep exactly the same boot.c behaviour.
The third change fixes issue 1899.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org
Commit: 9ef2629712680e70cbf39d8b6cb1ec0e0e2e72fa
https://github.com/qemu/qemu/commit/9ef2629712680e70cbf39d8b6cb1ec0e0e2e72fa
Author: Chris Rauer <crauer@google.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/timer/npcm7xx_timer.c
Log Message:
-----------
hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
The counter register is only 24-bits and counts down. If the timer is
running but the qtimer to reset it hasn't fired off yet, there is a chance
the regster read can return an invalid result.
Signed-off-by: Chris Rauer <crauer@google.com>
Message-id: 20230922181411.2697135-1-crauer@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2a052b4ee01b3c413cef2ef49cb780cde17d4ba1
https://github.com/qemu/qemu/commit/2a052b4ee01b3c413cef2ef49cb780cde17d4ba1
Author: Suraj Shirvankar <surajshirvankar@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M contrib/elf2dmp/addrspace.c
M contrib/elf2dmp/main.c
M contrib/elf2dmp/pdb.c
M contrib/elf2dmp/qemu_elf.c
Log Message:
-----------
contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
QEMU coding style uses the glib memory allocation APIs, not
the raw libc malloc/free. Switch the allocation and free
calls in elf2dmp to use these functions (dropping the now-unneeded
checks for failure).
Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>
Message-id: 169753938460.23804.11418813007617535750-1@git.sr.ht
[PMM: also remove NULL checks from g_malloc() calls;
beef up commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 364c7520a62bc16ba62360a8b05cd367368f1b20
https://github.com/qemu/qemu/commit/364c7520a62bc16ba62360a8b05cd367368f1b20
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/unit/test-smp-parse.c
Log Message:
-----------
tests: test-smp-parse: Add the test for cores/threads per socket helpers
Use the different ways to calculate cores/threads per socket, so that
the new CPU topology levels won't be missed in these 2 helpes:
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
threads per socket").
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-2-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9717aa04085e6c5f69e05a426b73386cd8bd9570
https://github.com/qemu/qemu/commit/9717aa04085e6c5f69e05a426b73386cd8bd9570
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.type4-count
A tests/data/acpi/q35/DSDT.type4-count
A tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count
test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 count.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-3-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a0380d46fe0119dc0d88ae1e1366f0d31d4b7c01
https://github.com/qemu/qemu/commit/a0380d46fe0119dc0d88ae1e1366f0d31d4b7c01
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 count
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
calculation").
In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built
for each socket, so the count of type4 tables should be equal to the
number of sockets.
Thus for the topology in this case, there're the following considerations:
1. The topology should include multiple sockets to ensure smbios could
create type4 tables for each socket.
2. In addition to sockets, for the more general topology, we should also
configure as many topology levels as possible (multiple dies, no
module since x86 hasn't supported it), to ensure that smbios is able
to exclude the effect of other topology levels to create the type4
tables only for sockets.
3. The original miscalculation bug also misused "smp.cpus", so it's
necessary to configure "cpus" (presented threads for machine) and
"maxcpus" (total threads for machine) as well to make sure that
configuring unpluged CPUs in smp (cpus < maxcpus) does not affect
the correctness of the count of type4 tables.
Based on these considerations, select the topology as the follow:
-smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3
The expected count of type4 tables = sockets (5).
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-4-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 488be118822f42f3d8ab64f7b4ff45aa1987b2d0
https://github.com/qemu/qemu/commit/488be118822f42f3d8ab64f7b4ff45aa1987b2d0
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.type4-count
M tests/data/acpi/q35/DSDT.type4-count
M tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000430
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : C5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
+[3E5h 0997 1] Length : 08
+[3E6h 0998 1] Processor ID : 77
+[3E7h 0999 1] Local Apic ID : 9E
+[3E8h 1000 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
+[3EDh 1005 1] Length : 0C
+[3EEh 1006 1] I/O Apic ID : 00
+[3EFh 1007 1] Reserved : 00
+[3F0h 1008 4] Address : FEC00000
+[3F4h 1012 4] Interrupt : 00000000
+
+[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
+[3F9h 1017 1] Length : 0A
+[3FAh 1018 1] Bus : 00
+[3FBh 1019 1] Source : 00
+[3FCh 1020 4] Interrupt : 00000002
+[400h 1024 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
+[403h 1027 1] Length : 0A
+[404h 1028 1] Bus : 00
+[405h 1029 1] Source : 05
+[406h 1030 4] Interrupt : 00000005
+[40Ah 1034 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
+[40Dh 1037 1] Length : 0A
+[40Eh 1038 1] Bus : 00
+[40Fh 1039 1] Source : 09
+[410h 1040 4] Interrupt : 00000009
+[414h 1044 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
+[417h 1047 1] Length : 0A
+[418h 1048 1] Bus : 00
+[419h 1049 1] Source : 0A
+[41Ah 1050 4] Interrupt : 0000000A
+[41Eh 1054 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
+[421h 1057 1] Length : 0A
+[422h 1058 1] Bus : 00
+[423h 1059 1] Source : 0B
+[424h 1060 4] Interrupt : 0000000B
+[428h 1064 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
+[42Bh 1067 1] Length : 06
+[42Ch 1068 1] Processor ID : FF
+[42Dh 1069 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[42Fh 1071 1] Interrupt Input LINT : 01
+
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000489D (18589)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDB
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
[snip]
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C077, 0x77, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x77))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 //
..w.....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x77)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x77, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-5-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c1ead6f56664f4b054600b866b3b5717c1b583c0
https://github.com/qemu/qemu/commit/c1ead6f56664f4b054600b866b3b5717c1b583c0
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.core-count
A tests/data/acpi/q35/DSDT.core-count
A tests/data/acpi/q35/FACP.core-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core
count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 core count
field.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-6-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 216cee8e19d7df4b98146affba41e9a8cd2420b8
https://github.com/qemu/qemu/commit/216cee8e19d7df4b98146affba41e9a8cd2420b8
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 core count
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
cores in the socket is not more than 255, then smbios type4 table
encodes cores per socket into the core count field.
So for the topology in this case, there're the following considerations:
1. cores per socket should be not more than 255 to ensure we could cover
the core count field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count field is correct.
Based on these considerations, select the topology with multiple sockets
and dies:
-smp 54,sockets=2,dies=3,cores=3,threads=3
The expected core count = cores per socket = cores (3) * dies (3) = 9.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-7-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0fb2bcba2146951453f9f4f2a2e26b27b3c3c4f2
https://github.com/qemu/qemu/commit/0fb2bcba2146951453f9f4f2a2e26b27b3c3c4f2
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.core-count
M tests/data/acpi/q35/DSDT.core-count
M tests/data/acpi/q35/FACP.core-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count
test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 3C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID:
Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) //
_CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
[snip]
+ If ((Arg0 == 0x35))
+ {
+ Notify (C035, Arg1)
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 //
..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-8-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cdfb71f1aea337087effd1abe088fa3e366eff49
https://github.com/qemu/qemu/commit/cdfb71f1aea337087effd1abe088fa3e366eff49
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core
count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be changed about the type 4 core count2
test case.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-9-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9b6eed0a425c164e69043631695fe49923ba3aa3
https://github.com/qemu/qemu/commit/9b6eed0a425c164e69043631695fe49923ba3aa3
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Extend smbios core count2 test to cover general
topology
The commit 196ea60a734c3 ("hw/smbios: Fix core count in type4") fixed
the miscalculation of cores per socket.
The original core count2 test (with the topology configured by
"-smp 275") didn't recognize that topology-related but because it just
created a special topology with only one socket and one die by default,
ignoring the effect of more topology levels (between socket and core) on
the cores per socket calculation.
So for the topology in this case, there're the following considerations:
1. cores per socket should be more than 255 to ensure we could cover
the core count2 field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (mutiple
sockets or dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count2 field is correct.
Based on these considerations, select the topology with multiple dies:
-smp 260,dies=2,cores=130,threads=1
Note, here we doesn't configure multiple sockets to avoid the error
("kvm_init_vcpu: kvm_get_vcpu failed (*): Too many open files") if user
uses the default ulimit seeting on his machine.
And the cores per socket calculation for multiple sockets has already
been covered by the core count test case, so that only multiple dies
configuration is enough.
The expected core count2 = cores per socket = cores (130) * dies (2) =
260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-10-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a2608f483691982630959c67a0c0f04565aeeb05
https://github.com/qemu/qemu/commit/a2608f483691982630959c67a0c0f04565aeeb05
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.core-count2
M tests/data/acpi/q35/DSDT.core-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Update ACPI table binaries for smbios core count2
test
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51
2023
+ * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
-[004h 0004 4] Table Length : 000009AE
+[004h 0004 4] Table Length : 00000CA6
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : CE
+[009h 0009 1] Checksum : FA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
@@ -1051,1256 +1051,1136 @@
[42Ch 1068 1] Subtable Type : 00 [Processor Local APIC]
[42Dh 1069 1] Length : 08
[42Eh 1070 1] Processor ID : 80
[42Fh 1071 1] Local Apic ID : 80
[430h 1072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
[435h 1077 1] Length : 08
[436h 1078 1] Processor ID : 81
[437h 1079 1] Local Apic ID : 81
[438h 1080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
-[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC]
-[43Dh 1085 1] Length : 08
-[43Eh 1086 1] Processor ID : 82
-[43Fh 1087 1] Local Apic ID : 82
-[440h 1088 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
-
-[444h 1092 1] Subtable Type : 00 [Processor Local APIC]
-[445h 1093 1] Length : 08
-[446h 1094 1] Processor ID : 83
-[447h 1095 1] Local Apic ID : 83
-[448h 1096 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
[snip]
-
-[964h 2404 1] Subtable Type : 01 [I/O APIC]
-[965h 2405 1] Length : 0C
-[966h 2406 1] I/O Apic ID : 00
-[967h 2407 1] Reserved : 00
-[968h 2408 4] Address : FEC00000
-[96Ch 2412 4] Interrupt : 00000000
-
-[970h 2416 1] Subtable Type : 02 [Interrupt Source Override]
-[971h 2417 1] Length : 0A
-[972h 2418 1] Bus : 00
-[973h 2419 1] Source : 00
-[974h 2420 4] Interrupt : 00000002
-[978h 2424 2] Flags (decoded below) : 0000
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
+
+[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC]
+[44Dh 1101 1] Length : 10
+[44Eh 1102 2] Reserved : 0000
+[450h 1104 4] Processor x2Apic ID : 00000101
+[454h 1108 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[458h 1112 4] Processor UID : 00000083
+
[snip]
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override]
-[97Bh 2427 1] Length : 0A
-[97Ch 2428 1] Bus : 00
-[97Dh 2429 1] Source : 05
-[97Eh 2430 4] Interrupt : 00000005
-[982h 2434 2] Flags (decoded below) : 000D
+[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override]
+[C73h 3187 1] Length : 0A
+[C74h 3188 1] Bus : 00
+[C75h 3189 1] Source : 05
+[C76h 3190 4] Interrupt : 00000005
+[C7Ah 3194 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[984h 2436 1] Subtable Type : 02 [Interrupt Source Override]
-[985h 2437 1] Length : 0A
-[986h 2438 1] Bus : 00
-[987h 2439 1] Source : 09
-[988h 2440 4] Interrupt : 00000009
-[98Ch 2444 2] Flags (decoded below) : 000D
+[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override]
+[C7Dh 3197 1] Length : 0A
+[C7Eh 3198 1] Bus : 00
+[C7Fh 3199 1] Source : 09
+[C80h 3200 4] Interrupt : 00000009
+[C84h 3204 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override]
-[98Fh 2447 1] Length : 0A
-[990h 2448 1] Bus : 00
-[991h 2449 1] Source : 0A
-[992h 2450 4] Interrupt : 0000000A
-[996h 2454 2] Flags (decoded below) : 000D
+[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override]
+[C87h 3207 1] Length : 0A
+[C88h 3208 1] Bus : 00
+[C89h 3209 1] Source : 0A
+[C8Ah 3210 4] Interrupt : 0000000A
+[C8Eh 3214 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[998h 2456 1] Subtable Type : 02 [Interrupt Source Override]
-[999h 2457 1] Length : 0A
-[99Ah 2458 1] Bus : 00
-[99Bh 2459 1] Source : 0B
-[99Ch 2460 4] Interrupt : 0000000B
-[9A0h 2464 2] Flags (decoded below) : 000D
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI]
-[9A3h 2467 1] Length : 0C
-[9A4h 2468 2] Flags (decoded below) : 0000
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[9A6h 2470 4] Processor UID : FFFFFFFF
-[9AAh 2474 1] Interrupt Input LINT : 01
-[9ABh 2475 3] Reserved : 000000
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51
2023
+ * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00007EEF (32495)
+ * Length 0x000083EA (33770)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x52
+ * Checksum 0x01
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\)
{
OperationRegion (DBG, SystemIO, 0x0402, One)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DBGB, 8
}
@@ -4196,107 +4196,32 @@
}
If ((Arg0 == 0x0101))
{
Notify (C101, Arg1)
}
If ((Arg0 == 0x0102))
{
Notify (C102, Arg1)
}
If ((Arg0 == 0x0103))
{
Notify (C103, Arg1)
}
-
- If ((Arg0 == 0x0104))
- {
- Notify (C104, Arg1)
- }
-
- If ((Arg0 == 0x0105))
- {
- Notify (C105, Arg1)
- }
-
- If ((Arg0 == 0x0106))
- {
- Notify (C106, Arg1)
- }
-
[snip]
- If ((Arg0 == 0x0112))
- {
- Notify (C112, Arg1)
- }
}
Method (CSTA, 1, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
If ((\_SB.PCI0.PRES.CPEN == One))
{
Local0 = 0x0F
}
Release (\_SB.PCI0.PRES.CPLK)
Return (Local0)
}
@@ -4306,33 +4231,33 @@
\_SB.PCI0.PRES.CSEL = Arg0
\_SB.PCI0.PRES.CEJ0 = One
Release (\_SB.PCI0.PRES.CPLK)
}
Method (CSCN, 0, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
{
Local4 = Zero
Local0 = One
Local1 = Zero
- While (((Local0 == One) && (Local3 < 0x0113)))
+ While (((Local0 == One) && (Local3 < 0x0104)))
{
Local0 = Zero
\_SB.PCI0.PRES.CSEL = Local3
\_SB.PCI0.PRES.CCMD = Zero
If ((\_SB.PCI0.PRES.CDAT < Local3))
{
Break
}
If ((Local1 == 0xFF))
{
Local4 = One
Break
}
Local3 = \_SB.PCI0.PRES.CDAT
@@ -7220,3281 +7145,3281 @@
Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
{
0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 //
........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x81)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x81, Arg0, Arg1, Arg2)
}
}
- Processor (C082, 0x82, 0x00000000, 0x00)
+ Device (C082)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x82) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x82))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x82)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x82, Arg0, Arg1, Arg2)
}
}
- Processor (C083, 0x83, 0x00000000, 0x00)
+ Device (C083)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x83) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x83))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x83)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x83, Arg0, Arg1, Arg2)
}
}
- Processor (C084, 0x84, 0x00000000, 0x00)
+ Device (C084)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x84) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x84))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x84)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x84, Arg0, Arg1, Arg2)
}
}
[snip]
- Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ Device (C0FE)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0xFE) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0xFE))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00,
0x00, // ....|...
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0xFE)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0xFE, Arg0, Arg1, Arg2)
}
}
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-11-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ec535cbbcabafc55d851a5684a58d74375b5fe03
https://github.com/qemu/qemu/commit/ec535cbbcabafc55d851a5684a58d74375b5fe03
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.thread-count
A tests/data/acpi/q35/DSDT.thread-count
A tests/data/acpi/q35/FACP.thread-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4
thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-12-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 353a6a8e25f01a2c876780662c43a107f94db76e
https://github.com/qemu/qemu/commit/353a6a8e25f01a2c876780662c43a107f94db76e
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 thread count
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is not more than 255, then smbios type4 table
encodes threads per socket into the thread count field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be not more than 255 to ensure we could
cover the thread count field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count field.
Based on these considerations, select the topology as the follow:
-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3
The expected thread count = threads per socket = threads (3) * cores (3)
* dies (3) = 27.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-13-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c738d7cf7e6c429127cbea0b7e8a850677af0227
https://github.com/qemu/qemu/commit/c738d7cf7e6c429127cbea0b7e8a850677af0227
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.thread-count
M tests/data/acpi/q35/DSDT.thread-count
M tests/data/acpi/q35/FACP.thread-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread
count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 63
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 //
..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-14-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: edefabefa082a693434ed07a34fcc2b7580dbb3d
https://github.com/qemu/qemu/commit/edefabefa082a693434ed07a34fcc2b7580dbb3d
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.thread-count2
A tests/data/acpi/q35/DSDT.thread-count2
A tests/data/acpi/q35/FACP.thread-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4
thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count2 field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-15-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 449d7c8441db2faa8596e393bba84130219d4551
https://github.com/qemu/qemu/commit/449d7c8441db2faa8596e393bba84130219d4551
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 thread count2
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is more than 255, then smbios type4 table encodes
threads per socket into the thread count2 field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be more than 255 to ensure we could cover
the thread count2 field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count2 field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count2 field.
Based on these considerations, select the topology as the follow:
-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2
The expected thread count2 = threads per socket = threads (2)
* cores (65) * dies (2) = 260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-16-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a270b3d88f9aa95b1648d0204c5a9312ba25a15c
https://github.com/qemu/qemu/commit/a270b3d88f9aa95b1648d0204c5a9312ba25a15c
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.thread-count2
M tests/data/acpi/q35/DSDT.thread-count2
M tests/data/acpi/q35/FACP.thread-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread
count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-WOA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-UMA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00001CE6
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : CA
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
+[435h 1077 1] Length : 08
+[436h 1078 1] Processor ID : 81
+[437h 1079 1] Local Apic ID : 81
+[438h 1080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
[snip]
+[1C8Ch 7308 1] Subtable Type : 09 [Processor Local x2APIC]
+[1C8Dh 7309 1] Length : 10
+[1C8Eh 7310 2] Reserved : 0000
+[1C90h 7312 4] Processor x2Apic ID : 00000381
+[1C94h 7316 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[1C98h 7320 4] Processor UID : 00000207
+
+[1C9Ch 7324 1] Subtable Type : 01 [I/O APIC]
+[1C9Dh 7325 1] Length : 0C
+[1C9Eh 7326 1] I/O Apic ID : 00
+[1C9Fh 7327 1] Reserved : 00
+[1CA0h 7328 4] Address : FEC00000
+[1CA4h 7332 4] Interrupt : 00000000
+
+[1CA8h 7336 1] Subtable Type : 02 [Interrupt Source Override]
+[1CA9h 7337 1] Length : 0A
+[1CAAh 7338 1] Bus : 00
+[1CABh 7339 1] Source : 00
+[1CACh 7340 4] Interrupt : 00000002
+[1CB0h 7344 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1CB2h 7346 1] Subtable Type : 02 [Interrupt Source Override]
+[1CB3h 7347 1] Length : 0A
+[1CB4h 7348 1] Bus : 00
+[1CB5h 7349 1] Source : 05
+[1CB6h 7350 4] Interrupt : 00000005
+[1CBAh 7354 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CBCh 7356 1] Subtable Type : 02 [Interrupt Source Override]
+[1CBDh 7357 1] Length : 0A
+[1CBEh 7358 1] Bus : 00
+[1CBFh 7359 1] Source : 09
+[1CC0h 7360 4] Interrupt : 00000009
+[1CC4h 7364 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CC6h 7366 1] Subtable Type : 02 [Interrupt Source Override]
+[1CC7h 7367 1] Length : 0A
+[1CC8h 7368 1] Bus : 00
+[1CC9h 7369 1] Source : 0A
+[1CCAh 7370 4] Interrupt : 0000000A
+[1CCEh 7374 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CD0h 7376 1] Subtable Type : 02 [Interrupt Source Override]
+[1CD1h 7377 1] Length : 0A
+[1CD2h 7378 1] Bus : 00
+[1CD3h 7379 1] Source : 0B
+[1CD4h 7380 4] Interrupt : 0000000B
+[1CD8h 7384 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CDAh 7386 1] Subtable Type : 0A [Local x2APIC NMI]
+[1CDBh 7387 1] Length : 0C
+[1CDCh 7388 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[1CDEh 7390 4] Processor UID : FFFFFFFF
+[1CE2h 7394 1] Interrupt Input LINT : 01
+[1CE3h 7395 3] Reserved : 000000
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-LWJ191, Wed Aug 23 22:29:53 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000F8B7 (63671)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xB7
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x81))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x81)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x81, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-17-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4620730c9787898f30b59ba5b84c05f52a79db2d
https://github.com/qemu/qemu/commit/4620730c9787898f30b59ba5b84c05f52a79db2d
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: strip superfluous whitespace
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-2-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c0c12102686aa08962667555b1cce9295bc86f25
https://github.com/qemu/qemu/commit/c0c12102686aa08962667555b1cce9295bc86f25
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: tighten "reply_supported" scope in "set_vring_addr"
In the vhost_user_set_vring_addr() function, we calculate
"reply_supported" unconditionally, even though we'll only need it if
"wait_for_reply" is also true.
Restrict the scope of "reply_supported" to the minimum.
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-3-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7c8be448c483f01c32021ccee4ba09ef0a69ff3e
https://github.com/qemu/qemu/commit/7c8be448c483f01c32021ccee4ba09ef0a69ff3e
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: factor out "vhost_user_write_sync"
The tails of the "vhost_user_set_vring_addr" and "vhost_user_set_u64"
functions are now byte-for-byte identical. Factor the common tail out to a
new function called "vhost_user_write_sync".
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-4-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f055379dae841a6db216864d7010d21f64a659a1
https://github.com/qemu/qemu/commit/f055379dae841a6db216864d7010d21f64a659a1
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: flatten "enforce_reply" into "vhost_user_write_sync"
At this point, only "vhost_user_write_sync" calls "enforce_reply"; embed
the latter into the former.
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-5-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c932ddb7f2f61ea27b3114d5adc3f06002cf119c
https://github.com/qemu/qemu/commit/c932ddb7f2f61ea27b3114d5adc3f06002cf119c
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: hoist "write_sync", "get_features", "get_u64"
In order to avoid a forward-declaration for "vhost_user_write_sync" in a
subsequent patch, hoist "vhost_user_write_sync" ->
"vhost_user_get_features" -> "vhost_user_get_u64" just above
"vhost_set_vring".
This is purely code movement -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-6-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 25e7564f205b1f0c7ccb81ca241014764e634f63
https://github.com/qemu/qemu/commit/25e7564f205b1f0c7ccb81ca241014764e634f63
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: allow "vhost_set_vring" to wait for a reply
The "vhost_set_vring" function already centralizes the common parts of
"vhost_user_set_vring_num", "vhost_user_set_vring_base" and
"vhost_user_set_vring_enable". We'll want to allow some of those callers
to wait for a reply.
Therefore, rebase "vhost_set_vring" from just "vhost_user_write" to
"vhost_user_write_sync", exposing the "wait_for_reply" parameter.
This is purely refactoring -- there is no observable change. That's
because:
- all three callers pass in "false" for "wait_for_reply", which disables
all logic in "vhost_user_write_sync" except the call to
"vhost_user_write";
- the fds=NULL and fd_num=0 arguments of the original "vhost_user_write"
call inside "vhost_set_vring" are hard-coded within
"vhost_user_write_sync".
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-7-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6c478515242e3dab419de4080f57010dec5694ba
https://github.com/qemu/qemu/commit/6c478515242e3dab419de4080f57010dec5694ba
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously
(1) The virtio-1.2 specification
<http://docs.oasis-open.org/virtio/virtio/v1.2/virtio-v1.2.html> writes:
> 3 General Initialization And Device Operation
> 3.1 Device Initialization
> 3.1.1 Driver Requirements: Device Initialization
>
> [...]
>
> 7. Perform device-specific setup, including discovery of virtqueues for
> the device, optional per-bus setup, reading and possibly writing the
> device’s virtio configuration space, and population of virtqueues.
>
> 8. Set the DRIVER_OK status bit. At this point the device is “live”.
and
> 4 Virtio Transport Options
> 4.1 Virtio Over PCI Bus
> 4.1.4 Virtio Structure PCI Capabilities
> 4.1.4.3 Common configuration structure layout
> 4.1.4.3.2 Driver Requirements: Common configuration structure layout
>
> [...]
>
> The driver MUST configure the other virtqueue fields before enabling the
> virtqueue with queue_enable.
>
> [...]
(The same statements are present in virtio-1.0 identically, at
<http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.html>.)
These together mean that the following sub-sequence of steps is valid for
a virtio-1.0 guest driver:
(1.1) set "queue_enable" for the needed queues as the final part of device
initialization step (7),
(1.2) set DRIVER_OK in step (8),
(1.3) immediately start sending virtio requests to the device.
(2) When vhost-user is enabled, and the VHOST_USER_F_PROTOCOL_FEATURES
special virtio feature is negotiated, then virtio rings start in disabled
state, according to
<https://qemu-project.gitlab.io/qemu/interop/vhost-user.html#ring-states>.
In this case, explicit VHOST_USER_SET_VRING_ENABLE messages are needed for
enabling vrings.
Therefore setting "queue_enable" from the guest (1.1) -- which is
technically "buffered" on the QEMU side until the guest sets DRIVER_OK
(1.2) -- is a *control plane* operation, which -- after (1.2) -- travels
from the guest through QEMU to the vhost-user backend, using a unix domain
socket.
Whereas sending a virtio request (1.3) is a *data plane* operation, which
evades QEMU -- it travels from guest to the vhost-user backend via
eventfd.
This means that operations ((1.1) + (1.2)) and (1.3) travel through
different channels, and their relative order can be reversed, as perceived
by the vhost-user backend.
That's exactly what happens when OVMF's virtiofs driver (VirtioFsDxe) runs
against the Rust-language virtiofsd version 1.7.2. (Which uses version
0.10.1 of the vhost-user-backend crate, and version 0.8.1 of the vhost
crate.)
Namely, when VirtioFsDxe binds a virtiofs device, it goes through the
device initialization steps (i.e., control plane operations), and
immediately sends a FUSE_INIT request too (i.e., performs a data plane
operation). In the Rust-language virtiofsd, this creates a race between
two components that run *concurrently*, i.e., in different threads or
processes:
- Control plane, handling vhost-user protocol messages:
The "VhostUserSlaveReqHandlerMut::set_vring_enable" method
[crates/vhost-user-backend/src/handler.rs] handles
VHOST_USER_SET_VRING_ENABLE messages, and updates each vring's "enabled"
flag according to the message processed.
- Data plane, handling virtio / FUSE requests:
The "VringEpollHandler::handle_event" method
[crates/vhost-user-backend/src/event_loop.rs] handles the incoming
virtio / FUSE request, consuming the virtio kick at the same time. If
the vring's "enabled" flag is set, the virtio / FUSE request is
processed genuinely. If the vring's "enabled" flag is clear, then the
virtio / FUSE request is discarded.
Note that OVMF enables the queue *first*, and sends FUSE_INIT *second*.
However, if the data plane processor in virtiofsd wins the race, then it
sees the FUSE_INIT *before* the control plane processor took notice of
VHOST_USER_SET_VRING_ENABLE and green-lit the queue for the data plane
processor. Therefore the latter drops FUSE_INIT on the floor, and goes
back to waiting for further virtio / FUSE requests with epoll_wait.
Meanwhile OVMF is stuck waiting for the FUSET_INIT response -- a deadlock.
The deadlock is not deterministic. OVMF hangs infrequently during first
boot. However, OVMF hangs almost certainly during reboots from the UEFI
shell.
The race can be "reliably masked" by inserting a very small delay -- a
single debug message -- at the top of "VringEpollHandler::handle_event",
i.e., just before the data plane processor checks the "enabled" field of
the vring. That delay suffices for the control plane processor to act upon
VHOST_USER_SET_VRING_ENABLE.
We can deterministically prevent the race in QEMU, by blocking OVMF inside
step (1.2) -- i.e., in the write to the device status register that
"unleashes" queue enablement -- until VHOST_USER_SET_VRING_ENABLE actually
*completes*. That way OVMF's VCPU cannot advance to the FUSE_INIT
submission before virtiofsd's control plane processor takes notice of the
queue being enabled.
Wait for VHOST_USER_SET_VRING_ENABLE completion by:
- setting the NEED_REPLY flag on VHOST_USER_SET_VRING_ENABLE, and waiting
for the reply, if the VHOST_USER_PROTOCOL_F_REPLY_ACK vhost-user feature
has been negotiated, or
- performing a separate VHOST_USER_GET_FEATURES *exchange*, which requires
a backend response regardless of VHOST_USER_PROTOCOL_F_REPLY_ACK.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
[lersek@redhat.com: work Eugenio's explanation into the commit message,
about QEMU containing step (1.1) until step (1.2)]
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-8-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1653545368d4849af5e1ed3e7c1815900c004b12
https://github.com/qemu/qemu/commit/1653545368d4849af5e1ed3e7c1815900c004b12
Author: Ilya Maximets <i.maximets@ovn.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M include/exec/memory.h
Log Message:
-----------
memory: initialize 'fv' in MemoryRegionCache to make Coverity happy
Coverity scan reports multiple false-positive "defects" for the
following series of actions in virtio.c:
MemoryRegionCache indirect_desc_cache;
address_space_cache_init_empty(&indirect_desc_cache);
address_space_cache_destroy(&indirect_desc_cache);
For some reason it's unable to recognize the dependency between 'mrs.mr'
and 'fv' and insists that '!mrs.mr' check in address_space_cache_destroy
may take a 'false' branch, even though it is explicitly initialized to
NULL in the address_space_cache_init_empty():
*** CID 1522371: Memory - illegal accesses (UNINIT)
/qemu/hw/virtio/virtio.c: 1627 in virtqueue_split_pop()
1621 }
1622
1623 vq->inuse++;
1624
1625 trace_virtqueue_pop(vq, elem, elem->in_num, elem->out_num);
1626 done:
>>> CID 1522371: Memory - illegal accesses (UNINIT)
>>> Using uninitialized value "indirect_desc_cache.fv" when
>>> calling "address_space_cache_destroy".
1627 address_space_cache_destroy(&indirect_desc_cache);
1628
1629 return elem;
1630
1631 err_undo_map:
1632 virtqueue_undo_map_desc(out_num, in_num, iov);
** CID 1522370: Memory - illegal accesses (UNINIT)
Instead of trying to silence these false positive reports in 4
different places, initializing 'fv' as well, as this doesn't result
in any noticeable performance impact.
Signed-off-by: Ilya Maximets <i.maximets@ovn.org>
Message-Id: <20231009104322.3085887-1-i.maximets@ovn.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 36d91da4a0e163a16fe2bb56855b11a48882efe9
https://github.com/qemu/qemu/commit/36d91da4a0e163a16fe2bb56855b11a48882efe9
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: do not send RESET_OWNER on device reset
The VHOST_USER_RESET_OWNER message is deprecated in the spec:
This is no longer used. Used to be sent to request disabling all
rings, but some back-ends interpreted it to also discard connection
state (this interpretation would lead to bugs). It is recommended
that back-ends either ignore this message, or use it to disable all
rings.
The only caller of vhost_user_reset_device() is vhost_user_scsi_reset().
It checks that F_RESET_DEVICE was negotiated before calling it:
static void vhost_user_scsi_reset(VirtIODevice *vdev)
{
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(vdev);
struct vhost_dev *dev = &vsc->dev;
/*
* Historically, reset was not implemented so only reset devices
* that are expecting it.
*/
if (!virtio_has_feature(dev->protocol_features,
VHOST_USER_PROTOCOL_F_RESET_DEVICE)) {
return;
}
if (dev->vhost_ops->vhost_reset_device) {
dev->vhost_ops->vhost_reset_device(dev);
}
}
Therefore VHOST_USER_RESET_OWNER is actually never sent by
vhost_user_reset_device(). Remove the dead code. This effectively moves
the vhost-user protocol specific code from vhost-user-scsi.c into
vhost-user.c where it belongs.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-2-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Commit: c4c8c5616c6d2b7c139a08c31adee7195721a9dc
https://github.com/qemu/qemu/commit/c4c8c5616c6d2b7c139a08c31adee7195721a9dc
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/vhost-backend.c
Log Message:
-----------
vhost-backend: remove vhost_kernel_reset_device()
vhost_kernel_reset_device() invokes RESET_OWNER, which disassociates the
owner process from the device. The device is left non-operational since
SET_OWNER is only called once during startup in vhost_dev_init().
vhost_kernel_reset_device() is never called so this latent bug never
appears. Get rid of vhost_kernel_reset_device() for now. If someone
needs it in the future they'll need to implement it correctly.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-3-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Hanna Czenczek <hreitz@redhat.com>
Commit: b7e9e78ade053308ef52b8dadeba15bd55623d20
https://github.com/qemu/qemu/commit/b7e9e78ade053308ef52b8dadeba15bd55623d20
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost.c
M hw/virtio/virtio.c
M include/hw/virtio/vhost.h
M meson.build
Log Message:
-----------
virtio: call ->vhost_reset_device() during reset
vhost-user-scsi has a VirtioDeviceClass->reset() function that calls
->vhost_reset_device(). The other vhost devices don't notify the vhost
device upon reset.
Stateful vhost devices may need to handle device reset in order to free
resources or prevent stale device state from interfering after reset.
Call ->vhost_device_reset() from virtio_reset() so that that vhost
devices are notified of device reset.
This patch affects behavior as follows:
- vhost-kernel: No change in behavior since ->vhost_reset_device() is
not implemented.
- vhost-user: back-ends that negotiate
VHOST_USER_PROTOCOL_F_RESET_DEVICE now receive a
VHOST_USER_DEVICE_RESET message upon device reset. Otherwise there is
no change in behavior. DPDK, SPDK, libvhost-user, and the
vhost-user-backend crate do not negotiate
VHOST_USER_PROTOCOL_F_RESET_DEVICE automatically.
- vhost-vdpa: an extra SET_STATUS 0 call is made during device reset.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-4-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Hanna Czenczek <hreitz@redhat.com>
Commit: 59cce3602fc40aebf265ec74378d8be998d4d0cd
https://github.com/qemu/qemu/commit/59cce3602fc40aebf265ec74378d8be998d4d0cd
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers
being identical
Commit 6103451aeb74 ("hw/i386: Build-time assertion on pc/q35 reset register
being identical.") introduced a build-time check where the addresses of the
reset registers are expected to be equal. Back then rev3 of the FADT was used
which required the reset register to be populated and there was common code.
In commit 3a3fcc75f92a ("pc: acpi: force FADT rev1 for 440fx based machine
types") the FADT was downgraded to rev1 for PIIX where the reset register isn't
available. Thus, there is no need for the assertion any longer, so remove it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231004092355.12929-1-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 70f86ee9f13bb182d4c4c51d464a4a1c011b3789
https://github.com/qemu/qemu/commit/70f86ee9f13bb182d4c4c51d464a4a1c011b3789
Author: Damien Zammit <damien@zamaudio.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/timer/i8254_common.c
Log Message:
-----------
timer/i8254: Fix one shot PIT mode
Currently, the one-shot (mode 1) PIT expires far too quickly,
due to the output being set under the wrong logic.
This change fixes the one-shot PIT mode to behave similarly to mode 0.
TESTED: using the one-shot PIT mode to calibrate a local apic timer.
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Message-Id: <20230226015755.52624-1-damien@zamaudio.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8d87983478a6db3679b15af601bb3df0d18ee09a
https://github.com/qemu/qemu/commit/8d87983478a6db3679b15af601bb3df0d18ee09a
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/display/virtio-dmabuf.c
Log Message:
-----------
hw/display: fix memleak from virtio_add_resource
When the given uuid is already present in the hash table,
virtio_add_resource() does not add the passed VirtioSharedObject. In
this case, free it in the callers to avoid leaking memory. This fixed
the following `make check` error, when built with --enable-sanitizers:
4/166 qemu:unit / test-virtio-dmabuf ERROR 1.51s exit status 1
==7716==ERROR: LeakSanitizer: detected memory leaks
Direct leak of 320 byte(s) in 20 object(s) allocated from:
#0 0x7f6fc16e3808 in __interceptor_malloc
../../../../src/libsanitizer/asan/asan_malloc_linux.cc:144
#1 0x7f6fc1503e98 in g_malloc
(/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57e98)
#2 0x564d63cafb6b in test_add_invalid_resource
../tests/unit/test-virtio-dmabuf.c:100
#3 0x7f6fc152659d (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7a59d)
SUMMARY: AddressSanitizer: 320 byte(s) leaked in 20 allocation(s).
The changes at virtio_add_resource() itself are not strictly necessary
for the memleak fix, but they make it more obvious that, on an error
return, the passed object is not added to the hash.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Message-Id:
<c61c13f9a0c67dec473bdbfc8789c29ef26c900b.1696624734.git.quic_mathbern@quicinc.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Albert Esteve <aesteve@redhat.com>
Signed-off-by: Matheus Tavares Bernardino <<a
href="mailto:quic_mathbern@quicinc.com";
target="_blank">quic_mathbern@quicinc.com</a>><br>
Commit: 068f463a6bbdfc0715a996b5d93db3a07d8b8942
https://github.com/qemu/qemu/commit/068f463a6bbdfc0715a996b5d93db3a07d8b8942
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
hw/i386/pc: Merge two if statements into one
By being the only entity assigning a non-NULL value to "rtc_irq", the first if
statement determines whether the second if statement is executed. So merge the
two statements into one.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-2-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 07779d2a500af6a47d8638da6f404f9f70b917e2
https://github.com/qemu/qemu/commit/07779d2a500af6a47d8638da6f404f9f70b917e2
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south
bridge
The next patches will need to take advantage of it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-3-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 171ded8387d45813c90fe564daeaaab57080985b
https://github.com/qemu/qemu/commit/171ded8387d45813c90fe564daeaaab57080985b
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize()
Unlike its PIIX4 counterpart, TYPE_PIIX3_DEVICE doesn't instantiate a PIC
itself. Instead, it relies on the board to do so. This means that the board
needs to wire the ISA IRQs to the PIIX3 device model. As long as the board
assigns the ISA IRQs after PIIX3's realize(), internal devices can't be wired in
pci_piix3_realize() since the qemu_irqs are still NULL. Fix that by assigning
the ISA interrupts before realize(). This will allow for embedding child devices
into the host device as already done for PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-4-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b2dafe19edd0658f179b3d8cf8869d5391e8d64c
https://github.com/qemu/qemu/commit/b2dafe19edd0658f179b3d8cf8869d5391e8d64c
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-5-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e6d1ee24a79a4e298a12e89f4518a8b855d97d81
https://github.com/qemu/qemu/commit/e6d1ee24a79a4e298a12e89f4518a8b855d97d81
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property
Avoid assigning the private member of struct PIIX3State from outside which goes
against best QOM practices. Instead, implement best QOM practice by adding an
"isa-irqs" array property to TYPE_PIIX3_DEVICE and assign it in board code, i.e.
from outside.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-6-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 17f19f20f7fd0f061a6fe2a5717e12044afd03cd
https://github.com/qemu/qemu/commit/17f19f20f7fd0f061a6fe2a5717e12044afd03cd
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix: Remove redundant "piix3" variable
The variable is never used by its declared type. Eliminate it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-7-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9fe11ba144a6301ed4c37f2d5d376f81d91570f9
https://github.com/qemu/qemu/commit/9fe11ba144a6301ed4c37f2d5d376f81d91570f9
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in"
TYPE_PIIX3_DEVICE doesn't instantiate a PIC since it relies on the board to do
so. The "pic" attribute, however, suggests that there is one. Rename the
attribute to reflect that it represents ISA interrupt lines. Use the same naming
convention as in the VIA south bridges as well as in TYPE_I82378.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-8-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 594be5780459fc713e9dc2fd91ee45e164097cd7
https://github.com/qemu/qemu/commit/594be5780459fc713e9dc2fd91ee45e164097cd7
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_q35.c
M hw/isa/lpc_ich9.c
Log Message:
-----------
hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize()
When the board assigns the ISA IRQs after the device's realize(), internal
devices such as the RTC can't be wired in ich9_lpc_realize() since the qemu_irqs
are still NULL. Fix that by assigning the ISA interrupts before realize().
This change is necessary for PIIX consolidation because PIIX4 wires the RTC
interrupts in its realize() method, so PIIX3 needs to do so as well. Since the
PC and Q35 boards share RTC code, and since PIIX3 needs the change, ICH9 needs
to be adapted as well.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-9-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 952fe2040017ba2f7712b56a9bd8f788c7a2bb67
https://github.com/qemu/qemu/commit/952fe2040017ba2f7712b56a9bd8f788c7a2bb67
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Wire PIC IRQs to ISA bus in host device
Thie PIIX3 south bridge implements both the PIC and the ISA bus, so wiring the
interrupts there makes the device model more self-contained. Furthermore, this
allows the ISA interrupts to be wired to internal child devices in
pci_piix3_realize() which will be performed in subsequent patches.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-10-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fac7dff67c2916740361c478509a62778c6ab35f
https://github.com/qemu/qemu/commit/fac7dff67c2916740361c478509a62778c6ab35f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc.c
M hw/isa/lpc_ich9.c
M hw/isa/piix3.c
Log Message:
-----------
hw/i386/pc: Wire RTC ISA IRQs in south bridges
Makes the south bridges a bit more self-contained and aligns PIIX3 more with
PIIX4. The latter is needed for consolidating the PIIX south bridges.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-11-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 89e8173cef14961f548d3ec93754782bf3966e74
https://github.com/qemu/qemu/commit/89e8173cef14961f548d3ec93754782bf3966e74
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/Kconfig
M hw/i386/pc_piix.c
M hw/isa/Kconfig
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Create IDE controller in host device
The IDE controller is an integral part of PIIX3 (function 1). So create it as
part of the south bridge.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-12-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 155b8d360cf3a12494536147e569c34660f0439e
https://github.com/qemu/qemu/commit/155b8d360cf3a12494536147e569c34660f0439e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/Kconfig
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Create USB controller in host device
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-13-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cd035303afe8127a4317a634de6e0b724d653444
https://github.com/qemu/qemu/commit/cd035303afe8127a4317a634de6e0b724d653444
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/Kconfig
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Create power management controller in host device
The power management controller is an integral part of PIIX3 (function 3). So
create it as part of the south bridge.
Note that the ACPI function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-14-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 15dc7b0bf565d953f578e487f7fe499247cfb91a
https://github.com/qemu/qemu/commit/15dc7b0bf565d953f578e487f7fe499247cfb91a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Drop the "3" from PIIX base class name
TYPE_PIIX3_PCI_DEVICE was the former base class of the Xen and non-Xen variants
of the PIIX3 ISA device models. It will become the base class for the PIIX3 and
PIIX4 device models, so drop the "3" from the type names.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-15-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b65ca9f8a3e8df22b3f94a8bf3d2f7ad73fc5733
https://github.com/qemu/qemu/commit/b65ca9f8a3e8df22b3f94a8bf3d2f7ad73fc5733
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Remove unused inbound ISA interrupt lines
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines. PIIX3 doesn't expose such interrupt lines
either, so remove them for PIIX4 for simplicity and consistency.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-16-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 03a4bf0885c29cc240fbef0598c4e248d01ffd04
https://github.com/qemu/qemu/commit/03a4bf0885c29cc240fbef0598c4e248d01ffd04
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in"
Rename the "isa" attribute to align it with PIIX3 for consolidation.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-17-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 24f1eae318ffc5d971f5756e13f2a86232a29106
https://github.com/qemu/qemu/commit/24f1eae318ffc5d971f5756e13f2a86232a29106
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Rename reset control operations to match PIIX3
Both implementations are the same and will be shared upon merging.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-18-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e219e47e5748be63bfc51c8f672dd812b8bb2a6d
https://github.com/qemu/qemu/commit/e219e47e5748be63bfc51c8f672dd812b8bb2a6d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix4.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix4: Reuse struct PIIXState from PIIX3
PIIX4 has its own, private PIIX4State structure. PIIX3 has almost the
same structure, provided in a public header. So reuse it and add a
cpu_intr attribute to it which is only used by PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-19-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 975bd3009c67d97dad8d8be81492915cdeee6255
https://github.com/qemu/qemu/commit/975bd3009c67d97dad8d8be81492915cdeee6255
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/i386/Kconfig
M hw/isa/Kconfig
M hw/isa/meson.build
A hw/isa/piix.c
R hw/isa/piix3.c
R hw/isa/piix4.c
M hw/mips/Kconfig
Log Message:
-----------
hw/isa/piix3: Merge hw/isa/piix4.c
Now that the PIIX3 and PIIX4 device models are sufficiently prepared, their
implementations can be merged into one file for further consolidation.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-20-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f6ca9c147dd66cef7da2f18a3af36314f2374275
https://github.com/qemu/qemu/commit/f6ca9c147dd66cef7da2f18a3af36314f2374275
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix: Allow for optional PIC creation in PIIX3
In the PC machine, the PIC is created in board code to allow it to be
virtualized with various virtualization techniques. So explicitly disable its
creation in the PC machine via a property which defaults to enabled. Once the
PIIX implementations are consolidated this default will keep Malta working
without further ado.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-21-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4a0ca61d89f3171ad4855c21052ce8f036f44df4
https://github.com/qemu/qemu/commit/4a0ca61d89f3171ad4855c21052ce8f036f44df4
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix: Allow for optional PIT creation in PIIX3
In the PC machine, the PIT is created in board code to allow it to be
virtualized with various virtualization techniques. So explicitly disable its
creation in the PC machine via a property which defaults to enabled. Once the
PIIX implementations are consolidated this default will keep Malta working
without further ado.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-22-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2f88ed357542dae7a40b3253a9021e783d1be795
https://github.com/qemu/qemu/commit/2f88ed357542dae7a40b3253a9021e783d1be795
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Harmonize names of reset control memory regions
There is no need for having different names here. Having the same name
further allows code to be shared between PIIX3 and PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-23-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3ee54f65f4bbcd566ff2e564cfa88080e0461cc2
https://github.com/qemu/qemu/commit/3ee54f65f4bbcd566ff2e564cfa88080e0461cc2
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Share PIIX3's base class with PIIX4
Having a common base class will allow for futher code sharing between PIIX3 and
PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-24-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d0d90c91e5227652bc6b2d0085d499769be268ac
https://github.com/qemu/qemu/commit/d0d90c91e5227652bc6b2d0085d499769be268ac
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix.c
M hw/mips/malta.c
Log Message:
-----------
hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
Resolves duplicate code. Also makes PIIX4 respect the PIIX3 properties which get
added, too. This allows for using PIIX4 in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-25-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 12103341c1802cc2ba2f265f44a65e26fd37b918
https://github.com/qemu/qemu/commit/12103341c1802cc2ba2f265f44a65e26fd37b918
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
PIIX4 will get the same optimizations which are already implemented for
PIIX3.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-26-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8894116db45dd4f3b4d97a19fe7ad85998d770dc
https://github.com/qemu/qemu/commit/8894116db45dd4f3b4d97a19fe7ad85998d770dc
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen
which relies on pci_bus_fire_intx_routing_notifier() to be fired.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-27-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 852a2968b658d709d5fa20785b3e0975bbe5e740
https://github.com/qemu/qemu/commit/852a2968b658d709d5fa20785b3e0975bbe5e740
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
Now that both PIIX3 and PIIX4 use piix_set_irq() to trigger PCI IRQs the wiring
in the respective realize methods can be shared, too.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-28-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f2bc8eba2a6e2f3b24713e84687766f7fc504917
https://github.com/qemu/qemu/commit/f2bc8eba2a6e2f3b24713e84687766f7fc504917
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Implement multi-process QEMU support also for PIIX4
So far multi-process QEMU was only implemented for PIIX3. Move the support into
the base class to achieve feature parity between both device models.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-29-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 99b70606c925aeab7cb446ec432dae3e90224124
https://github.com/qemu/qemu/commit/99b70606c925aeab7cb446ec432dae3e90224124
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M docs/system/target-i386-desc.rst.inc
M hw/i386/pc.c
M hw/i386/pc_piix.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
QEMU's PIIX3 implementation actually models the real PIIX4, but with different
PCI IDs. Usually, guests deal just fine with it. Still, in order to provide a
more consistent illusion to guests, allow QEMU's PIIX4 implementation to be used
in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-30-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 63a5c46a151c0d281d456de0474b7a27e87cd7ce
https://github.com/qemu/qemu/commit/63a5c46a151c0d281d456de0474b7a27e87cd7ce
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/scsi/vhost-scsi-common.c
Log Message:
-----------
vhost-user-common: send get_inflight_fd once
Currently the get_inflight_fd will be sent every time the device is started, and
the backend will allocate shared memory to save the inflight state. If the
backend finds that it receives the second get_inflight_fd, it will release the
previous shared memory, which breaks inflight working logic.
This patch is a preparation for the following patches.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-2-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0c4f0681bc8e9d18d6d247bbf53754bb09c114e0
https://github.com/qemu/qemu/commit/0c4f0681bc8e9d18d6d247bbf53754bb09c114e0
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/virtio/vhost-user-gpio.c
M include/hw/virtio/vhost.h
Log Message:
-----------
vhost: move and rename the conn retry times
Multiple devices need this macro, move it to a common header.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-3-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9dd0ffb1b904619ccc5e6b176c75877ed82be42f
https://github.com/qemu/qemu/commit/9dd0ffb1b904619ccc5e6b176c75877ed82be42f
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/scsi/vhost-scsi-common.c
M hw/scsi/vhost-scsi.c
M hw/scsi/vhost-user-scsi.c
M include/hw/virtio/vhost-scsi-common.h
M include/hw/virtio/vhost-user-scsi.h
Log Message:
-----------
vhost-user-scsi: support reconnect to backend
If the backend crashes and restarts, the device is broken.
This patch adds reconnect for vhost-user-scsi.
This patch also improves the error messages, and reports some silent errors.
Tested with spdk backend.
Signed-off-by: Li Feng <fengli@smartx.com>
Message-Id: <20231009044735.941655-4-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Commit: b52f98549a2ec1627a601d8debd87129d42b38af
https://github.com/qemu/qemu/commit/b52f98549a2ec1627a601d8debd87129d42b38af
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/scsi/vhost-user-scsi.c
Log Message:
-----------
vhost-user-scsi: start vhost when guest kicks
Let's keep the same behavior as vhost-user-blk.
Some old guests kick virtqueue before setting VIRTIO_CONFIG_S_DRIVER_OK.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-5-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f5af444510a79a32888ccb821abcba990ce296d0
https://github.com/qemu/qemu/commit/f5af444510a79a32888ccb821abcba990ce296d0
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost-user-gpio.c
M hw/virtio/vhost-user.c
M include/hw/virtio/vhost-user.h
Log Message:
-----------
vhost-user: fix lost reconnect
When the vhost-user is reconnecting to the backend, and if the vhost-user fails
at the get_features in vhost_dev_init(), then the reconnect will fail
and it will not be retriggered forever.
The reason is:
When the vhost-user fails at get_features, the vhost_dev_cleanup will be called
immediately.
vhost_dev_cleanup calls 'memset(hdev, 0, sizeof(struct vhost_dev))'.
The reconnect path is:
vhost_user_blk_event
vhost_user_async_close(.. vhost_user_blk_disconnect ..)
qemu_chr_fe_set_handlers <----- clear the notifier callback
schedule vhost_user_async_close_bh
The vhost->vdev is null, so the vhost_user_blk_disconnect will not be
called, then the event fd callback will not be reinstalled.
All vhost-user devices have this issue, including vhost-user-blk/scsi.
With this patch, if the vdev->vdev is null, the fd callback will still
be reinstalled.
Fixes: 71e076a07d ("hw/virtio: generalise CHR_EVENT_CLOSED handling")
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-6-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e9a5ce6265c31a11f8da17c3b09f0a65ec96ac66
https://github.com/qemu/qemu/commit/e9a5ce6265c31a11f8da17c3b09f0a65ec96ac66
Author: Ani Sinha <anisinha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range
pc_get_device_memory_range() finds the device memory size by calculating the
difference between maxram and ram sizes. This calculation makes sense only when
maxram is greater than the ram size. Make sure we check for that before calling
pc_get_device_memory_range().
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231011105335.42296-1-anisinha@redhat.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ca5140c48f9ad7c2dd2ddd7b0c01535decc72706
https://github.com/qemu/qemu/commit/ca5140c48f9ad7c2dd2ddd7b0c01535decc72706
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Allow update of DSDT.cxl
Addition of QTG in following patch requires an update to the test
data.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20231012125623.21101-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5485c304d89dcfba243c0d6b94bee91c1eed2c0f
https://github.com/qemu/qemu/commit/5485c304d89dcfba243c0d6b94bee91c1eed2c0f
Author: Dave Jiang <dave.jiang@intel.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/acpi/cxl.c
M hw/i386/acpi-build.c
M include/hw/acpi/cxl.h
Log Message:
-----------
hw/cxl: Add QTG _DSM support for ACPI0017 device
Add a simple _DSM call support for the ACPI0017 device to return fake QTG
ID values of 0 and 1 in all cases. This for _DSM plumbing testing from the OS.
Following edited for readability
Device (CXLM)
{
Name (_HID, "ACPI0017") // _HID: Hardware ID
...
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("f365f9a6-a7de-4071-a66a-b40c0b4f8e52")))
{
If ((Arg2 == Zero))
{
Return (Buffer (One) { 0x01 })
}
If ((Arg2 == One))
{
Return (Package (0x02)
{
One,
Package (0x02)
{
Zero,
One
}
})
}
}
}
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231012125623.21101-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9a5c9dd5dd24e58454825594545c731d1c66a8c1
https://github.com/qemu/qemu/commit/9a5c9dd5dd24e58454825594545c731d1c66a8c1
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Update DSDT.cxl with QTG DSM
Description of change in previous patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20231012125623.21101-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b106c85080e3d31347af49db4acd4ba79d9dfc0c
https://github.com/qemu/qemu/commit/b106c85080e3d31347af49db4acd4ba79d9dfc0c
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M docs/interop/vhost-user.rst
M include/hw/virtio/vhost-user.h
M subprojects/libvhost-user/libvhost-user.h
Log Message:
-----------
vhost-user: Fix protocol feature bit conflict
The VHOST_USER_PROTOCOL_F_XEN_MMAP feature bit was defined in
f21e95ee97d, which has been part of qemu's 8.1.0 release. However, it
seems it was never added to qemu's code, but it is well possible that it
is already used by different front-ends outside of qemu (i.e., Xen).
VHOST_USER_PROTOCOL_F_SHARED_OBJECT in contrast was added to qemu's code
in 16094766627, but never defined in the vhost-user specification. As a
consequence, both bits were defined to be 17, which cannot work.
Regardless of whether actual code or the specification should take
precedence, F_XEN_MMAP is already part of a qemu release, while
F_SHARED_OBJECT is not. Therefore, bump the latter to take number 18
instead of 17, and add this to the specification.
Take the opportunity to add at least a little note on the
VhostUserShared structure to the specification. This structure is
referenced by the new commands introduced in 16094766627, but was not
defined.
Fixes: 160947666276c5b7f6bca4d746bcac2966635d79
("vhost-user: add shared_object msg")
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016083201.23736-1-hreitz@redhat.com>
Reviewed-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: edfdf14791271a12cfd1e36c3e9d59a691b69bf5
https://github.com/qemu/qemu/commit/edfdf14791271a12cfd1e36c3e9d59a691b69bf5
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section
i8259.c is already listed here, so the corresponding header should
be mentioned in this section, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231017152625.229022-1-thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 16ef005ba922d5af498e9f0f2ee6b29a318821a8
https://github.com/qemu/qemu/commit/16ef005ba922d5af498e9f0f2ee6b29a318821a8
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel-iommu: Report interrupt remapping faults, fix return value
A generic X86IOMMUClass->int_remap function should not return VT-d
specific values; fix it to return 0 if the interrupt was successfully
translated or -EINVAL if not.
The VTD_FR_IR_xxx values are supposed to be used to actually raise
faults through the fault reporting mechanism, so do that instead for
the case where the IRQ is actually being injected.
There is more work to be done here, as pretranslations for the KVM IRQ
routing table can't fault; an untranslatable IRQ should be handled in
userspace and the fault raised only when the IRQ actually happens (if
indeed the IRTE is still not valid at that time). But we can work on
that later; we can at least raise faults for the direct case.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <31bbfc9041690449d3ac891f4431ec82174ee1b4.camel@infradead.org>
Acked-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: deb1ef950bace69c204a9e9de3893fcff0e37fee
https://github.com/qemu/qemu/commit/deb1ef950bace69c204a9e9de3893fcff0e37fee
Author: Luc Michel <luc@lmichel.fr>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M .mailmap
Log Message:
-----------
mailmap: update email addresses for Luc Michel
Map my old and now invalid work email addresses to my personal one.
Signed-off-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230929140326.2056658-2-luc@lmichel.fr>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 28900f9b2c23870915f8a5df90ae23af6a663965
https://github.com/qemu/qemu/commit/28900f9b2c23870915f8a5df90ae23af6a663965
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Split vt82c686 out of fuloong2e
The VIA south bridges are now mostly used by other machines not just
fuloong2e so split off into a separate section and take maintainership.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20231015141517.219317456A7@zero.eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 8db0760354eb0bab5005dd0d9115cc6650033326
https://github.com/qemu/qemu/commit/8db0760354eb0bab5005dd0d9115cc6650033326
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add hw/input/lasips2.c to the HPPA machine section
hw/input/lasips2.c and the corresponding header include/hw/input/lasips2.h
are only used by the HPPA machine, so add them to the corresponding section
in the MAINTAINERS file.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-ID: <20231017151933.213780-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b5b47424b4676cbbc6c1bd8dbe8409c4c0124a8e
https://github.com/qemu/qemu/commit/b5b47424b4676cbbc6c1bd8dbe8409c4c0124a8e
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add include/hw/intc/loongson_liointc.h to the Loongson-3 virt
section
The corresponding .c file is already listed here, so we should
mention the header here, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20231017153345.233807-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e257b8ca49388a0ad1728b4dfcd04803d694db77
https://github.com/qemu/qemu/commit/e257b8ca49388a0ad1728b4dfcd04803d694db77
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add include/hw/openrisc/ to the OpenRISC section
hw/openrisc/ is already listed here, so we should mention
the folder for the headers here, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231017154242.234133-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: dfd3bb0a99ae9627b4cc9b310ecef1b214188f71
https://github.com/qemu/qemu/commit/dfd3bb0a99ae9627b4cc9b310ecef1b214188f71
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M util/cutils.c
Log Message:
-----------
cutils: Fix get_relocated_path on Windows
get_relocated_path() did not have error handling for PathCchSkipRoot()
because a path given to get_relocated_path() was expected to be a valid
path containing a drive letter or UNC server/share path elements on
Windows, but sometimes it turned out otherwise.
The paths passed to get_relocated_path() are defined by macros generated
by Meson. Meson in turn uses a prefix given by the configure script to
generate them. For Windows, the script passes /qemu as a prefix to
Meson by default.
As documented in docs/about/build-platforms.rst, typically MSYS2 is used
for the build system, but it is also possible to use Linux as well. When
MSYS2 is used, its Bash variant recognizes /qemu as a MSYS2 path, and
converts it to a Windows path, adding the MSYS2 prefix including a drive
letter or UNC server/share path elements. Such a conversion does not
happen on a shell on Linux however, and /qemu will be passed as is in
the case.
Implement a proper error handling of PathCchSkipRoot() in
get_relocated_path() so that it can handle a path without a drive letter
or UNC server/share path elements.
Reported-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231005064726.6945-1-akihiko.odaki@daynix.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: da6f5544ce0ba351ffaeeac1c0c900d808774ad5
https://github.com/qemu/qemu/commit/da6f5544ce0ba351ffaeeac1c0c900d808774ad5
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M meson.build
Log Message:
-----------
buildsys: Only display Objective-C information when Objective-C is used
When configuring with '--disable-cocoa --disable-coreaudio'
on Darwin, we get:
meson.build:4081:58: ERROR: Tried to access compiler for language "objc", not
specified for host machine.
meson.build:4097:47: ERROR: Tried to access unknown option 'objc_args'.
Instead of unconditionally display Objective-C informations
on Darwin, display them when Objective-C is discovered.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20231009093812.52915-1-philmd@linaro.org>
Commit: 47538e44d6e7a3aa04873d84cf620345fd29a366
https://github.com/qemu/qemu/commit/47538e44d6e7a3aa04873d84cf620345fd29a366
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M system/memory_mapping.c
Log Message:
-----------
memory: drop needless argument
The argument is unused since commit bdc44640c ("cpu: Use QTAILQ for CPU list").
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231009075231.150568-1-marcandre.lureau@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 8a5b974b981725019c31faa156c36d8141517e15
https://github.com/qemu/qemu/commit/8a5b974b981725019c31faa156c36d8141517e15
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/core/cpu-sysemu.c
M include/hw/core/cpu.h
M include/hw/core/sysemu-cpu-ops.h
M include/sysemu/memory_mapping.h
M system/memory_mapping.c
M target/i386/arch_memory_mapping.c
M target/i386/cpu.h
Log Message:
-----------
memory: follow Error API guidelines
Return true/false on success/failure.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231009075310.153617-1-marcandre.lureau@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 946df4d500888c8ddad580b28fa72b138f106823
https://github.com/qemu/qemu/commit/946df4d500888c8ddad580b28fa72b138f106823
Author: Lu Gao <lu.gao@verisilicon.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
hw/sd/sdhci: Block Size Register bits [14:12] is lost
Block Size Register bits [14:12] is SDMA Buffer Boundary, it is missed
in register write, but it is needed in SDMA transfer. e.g. it will be
used in sdhci_sdma_transfer_multi_blocks to calculate boundary_ variables.
Missing this field will cause wrong operation for different SDMA Buffer
Boundary settings.
Fixes: d7dfca0807 ("hw/sdhci: introduce standard SD host controller")
Fixes: dfba99f17f ("hw/sdhci: Fix DMA Transfer Block Size field")
Signed-off-by: Lu Gao <lu.gao@verisilicon.com>
Signed-off-by: Jianxian Wen <jianxian.wen@verisilicon.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-ID: <20220321055618.4026-1-lu.gao@verisilicon.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 9ce8c6ddd302d23df503e89e03544c5e832b4dc3
https://github.com/qemu/qemu/commit/9ce8c6ddd302d23df503e89e03544c5e832b4dc3
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use sdram_type enum from 'hw/i2c/smbus_eeprom.h'
Since commit 93198b6cad ("i2c: Split smbus into parts") the SDRAM
types are enumerated as sdram_type in "hw/i2c/smbus_eeprom.h".
Using the enum removes this global shadow warning:
hw/mips/malta.c:209:12: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
enum { SDR = 0x4, DDR2 = 0x8 } type;
^
include/hw/i2c/smbus_eeprom.h:33:19: note: previous declaration is here
enum sdram_type { SDR = 0x4, DDR = 0x7, DDR2 = 0x8 };
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231009092127.49778-1-philmd@linaro.org>
Commit: 30a8d3a14216e31f2539b00ff4e5df7f3a08ce89
https://github.com/qemu/qemu/commit/30a8d3a14216e31f2539b00ff4e5df7f3a08ce89
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/mips/cps.c
M hw/mips/fuloong2e.c
M hw/mips/jazz.c
M hw/mips/loongson3_virt.c
M hw/mips/malta.c
M hw/mips/mips_int.c
M hw/mips/mipssim.c
R include/hw/mips/cpudevs.h
M target/mips/cpu.h
M target/mips/sysemu/cp0_timer.c
M target/mips/tcg/sysemu/tlb_helper.c
Log Message:
-----------
hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'
"hw/mips/cpudevs.h" contains declarations which are specific
to the MIPS architecture; it doesn't make sense for these to
be called from a non-MIPS architecture. Move the declarations
to "target/mips/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231009171443.12145-2-philmd@linaro.org>
Commit: db646e830e58f611a112210972332711f9c28af9
https://github.com/qemu/qemu/commit/db646e830e58f611a112210972332711f9c28af9
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M include/hw/misc/mips_itu.h
M target/mips/cpu.h
M target/mips/tcg/sysemu/cp0_helper.c
Log Message:
-----------
hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'
We already provide "hw/misc/mips_itu.h" to declare prototype
related to MIPSITUState. Move itc_reconfigure() declaration
there.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231009171443.12145-3-philmd@linaro.org>
Commit: 53af33a5b4e799d92e6687984349a098c3d37732
https://github.com/qemu/qemu/commit/53af33a5b4e799d92e6687984349a098c3d37732
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/misc/mips_itu.c
M include/hw/misc/mips_itu.h
Log Message:
-----------
hw/misc/mips_itu: Make MIPSITUState target agnostic
When prototyping a heterogenous machine including the ITU,
we get:
include/hw/misc/mips_itu.h:76:5: error: unknown type name 'MIPSCPU'
MIPSCPU *cpu0;
^
MIPSCPU is declared in the target specific "cpu.h" header,
but we don't want to include it, because "cpu.h" is target
specific and its inclusion taints all files including
"mips_itu.h", which become target specific too. We can
however use the 'ArchCPU *' type in the public header.
By keeping the TYPE_MIPS_CPU QOM type check in the link
property declaration, QOM core code will still check the
property is a correct MIPS CPU.
TYPE_MIPS_ITU is still built per-(MIPS)target, but its header
can now be included by other targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231009171443.12145-4-philmd@linaro.org>
Commit: bf9e5c1f22f6b4995672b72dd96bb363317fe574
https://github.com/qemu/qemu/commit/bf9e5c1f22f6b4995672b72dd96bb363317fe574
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/pci-host/sh_pci.c
Log Message:
-----------
hw/pci-host/sh_pcic: Declare CPU QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20231012041237.22281-2-philmd@linaro.org>
Commit: 6db7f62b34150162b76be5b9f54caa89af0f6c7d
https://github.com/qemu/qemu/commit/6db7f62b34150162b76be5b9f54caa89af0f6c7d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/pci-host/sh_pci.c
Log Message:
-----------
hw/pci-host/sh_pcic: Correct PCI host / devfn#0 function names
Host bridge device and PCI function #0 are inverted.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20231012041237.22281-3-philmd@linaro.org>
Commit: f158d3befe25bef38a2ff364318076466c47a114
https://github.com/qemu/qemu/commit/f158d3befe25bef38a2ff364318076466c47a114
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/pci-host/sh_pci.c
Log Message:
-----------
hw/pci-host/sh_pcic: Replace magic value by proper definition
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20231012041237.22281-4-philmd@linaro.org>
Commit: 4aa07e864911b77dc7fb4704554bb041776b8ec7
https://github.com/qemu/qemu/commit/4aa07e864911b77dc7fb4704554bb041776b8ec7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/sparc64/sun4u.c
Log Message:
-----------
hw/sparc64/ebus: Access memory regions via pci_address_space_io()
PCI functions are plugged on a PCI bus. They can only access
external memory regions via the bus.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231011185954.10337-5-philmd@linaro.org>
Commit: 305ab2b9716551e486cbdcff111610a2cf8da095
https://github.com/qemu/qemu/commit/305ab2b9716551e486cbdcff111610a2cf8da095
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/acpi/pcihp.c
M include/hw/acpi/pcihp.h
Log Message:
-----------
hw/acpi/pcihp: Clean up global variable shadowing in acpi_pcihp_init()
Fix:
hw/acpi/pcihp.c:499:36: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
MemoryRegion *address_space_io,
^
include/exec/address-spaces.h:35:21: note: previous declaration is here
extern AddressSpace address_space_io;
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231010115048.11856-5-philmd@linaro.org>
Commit: 49909a0d0336fa682049544f284bbeda6f02c4ac
https://github.com/qemu/qemu/commit/49909a0d0336fa682049544f284bbeda6f02c4ac
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/pci/pci.c
M include/hw/pci/pci.h
Log Message:
-----------
hw/pci: Clean up global variable shadowing of address_space_io variable
Fix:
hw/pci/pci.c:504:54: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
MemoryRegion *address_space_io,
^
hw/pci/pci.c:533:38: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
MemoryRegion *address_space_io,
^
hw/pci/pci.c:543:40: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
MemoryRegion *address_space_io,
^
hw/pci/pci.c:590:45: error: declaration shadows a variable in the global
scope [-Werror,-Wshadow]
MemoryRegion *address_space_io,
^
include/exec/address-spaces.h:35:21: note: previous declaration is here
extern AddressSpace address_space_io;
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231010115048.11856-6-philmd@linaro.org>
Commit: b2b5b09045e61798d5454f6b32721172d736c828
https://github.com/qemu/qemu/commit/b2b5b09045e61798d5454f6b32721172d736c828
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/s390x/sclpquiesce.c
Log Message:
-----------
hw/s390x: Clean up global variable shadowing in quiesce_powerdown_req()
Fix:
hw/s390x/sclpquiesce.c:90:22: error: declaration shadows a variable in the
global scope [-Werror,-Wshadow]
QuiesceNotifier *qn = container_of(n, QuiesceNotifier, notifier);
^
hw/s390x/sclpquiesce.c:86:3: note: previous declaration is here
} qn;
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20231010115048.11856-7-philmd@linaro.org>
Commit: 0459c141f8d9dc99274ca3cffe632a37a0575c9e
https://github.com/qemu/qemu/commit/0459c141f8d9dc99274ca3cffe632a37a0575c9e
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/intc/apic_common.c
Log Message:
-----------
hw/intc/apic: Use ERRP_GUARD() in apic_common_realize()
APICCommonClass::realize() is a DeviceRealize() handler which
take an Error** parameter and can fail. Do not proceed further
on failure.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-Id: <20231003082728.83496-2-philmd@linaro.org>
Commit: 880e26074c271e88235b453107fdfd40b0940f7f
https://github.com/qemu/qemu/commit/880e26074c271e88235b453107fdfd40b0940f7f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/ppc/spapr_vio.c
Log Message:
-----------
hw/ppc/spapr_vio: Realize SPAPR_VIO_BRIDGE device before accessing it
qbus_new() should not be called on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231019131647.19690-2-philmd@linaro.org>
Commit: 90ac3862ff59a31563f81915dcc709d1eec52cdb
https://github.com/qemu/qemu/commit/90ac3862ff59a31563f81915dcc709d1eec52cdb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
hw/ppc/pnv_xscom: Rename pnv_xscom_realize(Error **) -> pnv_xscom_init()
pnv_xscom_realize() is not used to *realize* QDev object, rename
it as pnv_xscom_init(). The Error** argument is unused: remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231019131647.19690-3-philmd@linaro.org>
Commit: 326f7acb81fd75eb7cb5aaa49139b1586a94c624
https://github.com/qemu/qemu/commit/326f7acb81fd75eb7cb5aaa49139b1586a94c624
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
hw/ppc/pnv_xscom: Move sysbus_mmio_map() call within pnv_xscom_init()
In order to make the next commit trivial, move sysbus_init_mmio()
calls just before the corresponding sysbus_mmio_map() calls.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231019131647.19690-4-philmd@linaro.org>
Commit: bddb677544986abed53fe9a538d207dbef8aff88
https://github.com/qemu/qemu/commit/bddb677544986abed53fe9a538d207dbef8aff88
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/ppc/pnv_xscom.c
Log Message:
-----------
hw/ppc/pnv_xscom: Do not use SysBus API to map local MMIO region
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Transformation done using the following coccinelle script:
@@
expression sbdev;
expression index;
expression addr;
expression subregion;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map(sbdev, index, addr);
+ memory_region_add_subregion(get_system_memory(), addr, subregion);
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231019131647.19690-5-philmd@linaro.org>
Commit: bf3b9754b7cd8ae493b186e8da2ab8d6d7145c77
https://github.com/qemu/qemu/commit/bf3b9754b7cd8ae493b186e8da2ab8d6d7145c77
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
hw/ppc/pnv: Do not use SysBus API to map local MMIO region
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Transformation done using the following coccinelle script:
@@
expression sbdev;
expression index;
expression addr;
expression subregion;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map(sbdev, index, addr);
+ memory_region_add_subregion(get_system_memory(), addr, subregion);
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231019131647.19690-6-philmd@linaro.org>
Commit: e061eed80263a3de929871098f01bd28fb758dfb
https://github.com/qemu/qemu/commit/e061eed80263a3de929871098f01bd28fb758dfb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/intc/spapr_xive.c
Log Message:
-----------
hw/intc/spapr_xive: Move sysbus_init_mmio() calls around
In order to make the next commit trivial, move sysbus_init_mmio()
calls just before the corresponding sysbus_mmio_map() calls.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231019131647.19690-7-philmd@linaro.org>
Commit: 6c9dcd8760092e455f86f6afb05d87ea827da8f3
https://github.com/qemu/qemu/commit/6c9dcd8760092e455f86f6afb05d87ea827da8f3
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/intc/spapr_xive.c
Log Message:
-----------
hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Transformation done using the following coccinelle script:
@@
expression sbdev;
expression index;
expression addr;
expression subregion;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map(sbdev, index, addr);
+ memory_region_add_subregion(get_system_memory(), addr, subregion);
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231019131647.19690-8-philmd@linaro.org>
Commit: 40f8214fcde40bab3ef6d1ab0b2353c7f8bc62aa
https://github.com/qemu/qemu/commit/40f8214fcde40bab3ef6d1ab0b2353c7f8bc62aa
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/pc.c
M hw/isa/i82378.c
M hw/mips/jazz.c
M include/hw/audio/pcspk.h
Log Message:
-----------
hw/audio/pcspk: Inline pcspk_init()
pcspk_init() is a legacy init function, inline and remove it.
Since the device is realized using &error_fatal, use the same
error for setting the "pit" link.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231019073307.99608-1-philmd@linaro.org>
Commit: 544f07f6394ab940021f3b512d8bb1b34380dcd6
https://github.com/qemu/qemu/commit/544f07f6394ab940021f3b512d8bb1b34380dcd6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/amd_iommu.c
Log Message:
-----------
hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Transformation done using the following coccinelle script:
@@
expression sbdev;
expression index;
expression addr;
expression subregion;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map(sbdev, index, addr);
+ memory_region_add_subregion(get_system_memory(), addr, subregion);
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231018141151.87466-2-philmd@linaro.org>
Commit: a540087f608f1996e3581ddb39456be23db577a8
https://github.com/qemu/qemu/commit/a540087f608f1996e3581ddb39456be23db577a8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Transformation done using the following coccinelle script:
@@
expression sbdev;
expression index;
expression addr;
expression subregion;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map(sbdev, index, addr);
+ memory_region_add_subregion(get_system_memory(), addr, subregion);
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231018141151.87466-3-philmd@linaro.org>
Commit: d71af7c83eb4a6adbaf3ce0afba1d3dfbf4a6e2c
https://github.com/qemu/qemu/commit/d71af7c83eb4a6adbaf3ce0afba1d3dfbf4a6e2c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/misc/allwinner-r40-dramc.c
Log Message:
-----------
hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize
In order to make the next commit trivial, move the sysbus_init_mmio()
call in allwinner_r40_dramc_init() just before the corresponding
sysbus_mmio_map_overlap() call in allwinner_r40_dramc_realize().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231019071611.98885-4-philmd@linaro.org>
Commit: faef398291598e39a4484947d44bb177b4596120
https://github.com/qemu/qemu/commit/faef398291598e39a4484947d44bb177b4596120
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/misc/allwinner-r40-dramc.c
Log Message:
-----------
hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Transformation done using the following coccinelle script:
@@
expression sbdev;
expression index;
expression addr;
expression subregion;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map(sbdev, index, addr);
+ memory_region_add_subregion(get_system_memory(),
+ addr, subregion);
@@
expression priority;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map_overlap(sbdev, index, addr, priority);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ addr,
+ subregion, priority);
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231019071611.98885-5-philmd@linaro.org>
Commit: 0493aafb1abbe6256522c32b5686418b5b192e7e
https://github.com/qemu/qemu/commit/0493aafb1abbe6256522c32b5686418b5b192e7e
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/pci-host/bonito.c
Log Message:
-----------
hw/pci-host/bonito: Do not use SysBus API to map local MMIO region
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Transformation done using the following coccinelle script:
@@
expression sbdev;
expression index;
expression addr;
expression subregion;
@@
- sysbus_init_mmio(sbdev, subregion);
... when != sbdev
- sysbus_mmio_map(sbdev, index, addr);
+ memory_region_add_subregion(get_system_memory(), addr, subregion);
and manually adding the local 'host_mem' variable to
avoid multiple calls to get_system_memory().
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231019071611.98885-6-philmd@linaro.org>
Commit: bec4be77ea18feb9d50a6c2ee42b6c3ffe4ae78b
https://github.com/qemu/qemu/commit/bec4be77ea18feb9d50a6c2ee42b6c3ffe4ae78b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/virt.c
M hw/i386/microvm.c
M hw/loongarch/virt.c
Log Message:
-----------
hw/acpi: Realize ACPI_GED sysbus device before accessing it
sysbus_mmio_map() should not be called on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231018141151.87466-7-philmd@linaro.org>
Commit: 8a89bb060765e26e0f0d55a495caf3c0fd8615ba
https://github.com/qemu/qemu/commit/8a89bb060765e26e0f0d55a495caf3c0fd8615ba
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it
sysbus_mmio_map() should not be called on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231018141151.87466-8-philmd@linaro.org>
Commit: 675d717b9ee2d8dea9cfdca9aa69ed97d8bc54d3
https://github.com/qemu/qemu/commit/675d717b9ee2d8dea9cfdca9aa69ed97d8bc54d3
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/isa/isa-bus.c
Log Message:
-----------
hw/isa: Realize ISA bridge device before accessing it
qbus_new() should not be called on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231019071611.98885-9-philmd@linaro.org>
Commit: 840b4495ef5c2d90d75f3f0d00d9018146f27d8e
https://github.com/qemu/qemu/commit/840b4495ef5c2d90d75f3f0d00d9018146f27d8e
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/s390x/css-bridge.c
Log Message:
-----------
hw/s390x/css-bridge: Realize sysbus device before accessing it
qbus_new() should not be called on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231019071611.98885-10-philmd@linaro.org>
Commit: 5960f254dbb46f0c7a9f5f44bf4d27c19c34cb97
https://github.com/qemu/qemu/commit/5960f254dbb46f0c7a9f5f44bf4d27c19c34cb97
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/virtio/virtio-pmem.c
Log Message:
-----------
hw/virtio/virtio-pmem: Replace impossible check by assertion
The get_memory_region() handler is used when (un)plugging the
device, which can only occur *after* it is realized.
virtio_pmem_realize() ensure the instance can not be realized
without 'memdev'. Remove the superfluous check, replacing it
by an assertion.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20231017140150.44995-2-philmd@linaro.org>
Commit: 11591b586620ae62155d6bc36650283e7c05efa9
https://github.com/qemu/qemu/commit/11591b586620ae62155d6bc36650283e7c05efa9
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/block/vhost-user-blk.c
Log Message:
-----------
hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros
Access QOM parent with the proper QOM [VIRTIO_]DEVICE() macros.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231017140150.44995-3-philmd@linaro.org>
Commit: 3daccfff75dd536117abde15169bede707646977
https://github.com/qemu/qemu/commit/3daccfff75dd536117abde15169bede707646977
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/display/virtio-gpu.c
Log Message:
-----------
hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro
Access QOM parent with the proper QOM VIRTIO_DEVICE() macro.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231017140150.44995-4-philmd@linaro.org>
Commit: 7794fc9799afb32436d9927900a63f7f73d2ebce
https://github.com/qemu/qemu/commit/7794fc9799afb32436d9927900a63f7f73d2ebce
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/scsi/virtio-scsi.c
Log Message:
-----------
hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro
Access QOM parent with the proper QOM VIRTIO_SCSI_COMMON() macro.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231017140150.44995-5-philmd@linaro.org>
Commit: 1f9d714e9a92d382f5f7c054de647d3dde4ba803
https://github.com/qemu/qemu/commit/1f9d714e9a92d382f5f7c054de647d3dde4ba803
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/dma/xilinx_axidma.c
M hw/dma/xlnx-zdma.c
M hw/dma/xlnx_csu_dma.c
Log Message:
-----------
hw/dma: Declare link using static DEFINE_PROP_LINK() macro
Declare link statically using DEFINE_PROP_LINK().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231017140150.44995-6-philmd@linaro.org>
Commit: 08d45942972ada0e4d051799fb8ba1b47225a6b3
https://github.com/qemu/qemu/commit/08d45942972ada0e4d051799fb8ba1b47225a6b3
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M hw/net/cadence_gem.c
Log Message:
-----------
hw/net: Declare link using static DEFINE_PROP_LINK() macro
Declare link statically using DEFINE_PROP_LINK().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231017140150.44995-7-philmd@linaro.org>
Commit: b1be65f6436f53618408d9c6fc6959054f5afed6
https://github.com/qemu/qemu/commit/b1be65f6436f53618408d9c6fc6959054f5afed6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M chardev/msmouse.c
M chardev/wctablet.c
M hw/char/escc.c
M hw/display/xenfb.c
M hw/input/adb-kbd.c
M hw/input/hid.c
M hw/input/ps2.c
M hw/input/virtio-input-hid.c
M include/hw/virtio/virtio-input.h
M include/ui/input.h
M ui/input-legacy.c
M ui/input.c
M ui/vdagent.c
Log Message:
-----------
ui/input: Constify QemuInputHandler structure
Access to QemuInputHandlerState::handler are read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231017131251.43708-1-philmd@linaro.org>
Commit: e029bb00a79bea226477749f9b10a2ff9e7930ef
https://github.com/qemu/qemu/commit/e029bb00a79bea226477749f9b10a2ff9e7930ef
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
A hw/pci-host/astro.c
M hw/pci-host/trace-events
A include/hw/pci-host/astro.h
Log Message:
-----------
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA)
with Elroy PCI host chips.
Later generation Astro chips were named Pluto, Ike and REO.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 1a960c8915ff3d8827d09a4afacf15b1f12c5e04
https://github.com/qemu/qemu/commit/1a960c8915ff3d8827d09a4afacf15b1f12c5e04
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/hppa/Kconfig
M hw/pci-host/Kconfig
M hw/pci-host/meson.build
Log Message:
-----------
pci-host: Wire up new Astro/Elroy PCI bridge
Allow the Astro source to be built.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: ae759c96c3174ccbc1438b2b9ee265bee6a167a5
https://github.com/qemu/qemu/commit/ae759c96c3174ccbc1438b2b9ee265bee6a167a5
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update HP-PARISC entries
Add the new HP C3700 machine, the new Astro PCI host and
add the missing entry for the seabios-hppa directory.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: bcd4dd4c22f2df17def72668c75cdf01fb47b6ff
https://github.com/qemu/qemu/commit/bcd4dd4c22f2df17def72668c75cdf01fb47b6ff
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg
Provide necessary info to SeaBIOS-hppa.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: e2c41ee557f4389d577ad54b1c131d2e0b558558
https://github.com/qemu/qemu/commit/e2c41ee557f4389d577ad54b1c131d2e0b558558
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/hppa/hppa_hardware.h
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Provide RTC and DebugOutputPort on CPU #0
For SeaBIOS-hppa, the RTC and DebugOutputPort were in the I/O area of
the LASI chip of the emulated B160L machine.
Since we will add other machines without a LASI chip, move the emulated
devices into the I/O area of CPU#0 instead.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 7df6f7511769af63c209d2fdcd6c7638f680e35a
https://github.com/qemu/qemu/commit/7df6f7511769af63c209d2fdcd6c7638f680e35a
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Split out machine creation
This is a preparation patch to allow the creation of additional
hppa machine.
It splits out the creation of the machine into a
- machine_HP_common_init_cpus(), and a
- machine_HP_common_init_tail()
function.
This will allow to reuse the basic functions which are common to
all parisc machines.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 2ed4faa03fa92e3ab9160c09f3eb866fbdd60ecc
https://github.com/qemu/qemu/commit/2ed4faa03fa92e3ab9160c09f3eb866fbdd60ecc
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Add new HP C3700 machine
Add code to create an emulated C3700 machine.
It includes the following components:
- HP Powerbar SP2 Diva BMC card (serial port only)
- PCI 4x serial card (for serial ports #1-#4)
- USB OHCI controller with USB keyboard and USB mouse
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 3da4aef81ca61c82c67b86af369ccd251607622e
https://github.com/qemu/qemu/commit/3da4aef81ca61c82c67b86af369ccd251607622e
Author: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M qapi/machine.json
Log Message:
-----------
qapi: machine.json: change docs regarding CPU topology
Clarify roles of different architectures.
Also change things a bit in anticipation of additional members being
added.
Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-2-nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
[thuth: Updated some comments according to suggestions from Markus]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 5de1aff2555275ef182197eddcadb276364ace38
https://github.com/qemu/qemu/commit/5de1aff2555275ef182197eddcadb276364ace38
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/core/machine-smp.c
M hw/core/machine.c
M hw/core/qdev-properties-system.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/hw/qdev-properties-system.h
A qapi/machine-common.json
M qapi/machine.json
M qapi/meson.build
M qapi/qapi-schema.json
M qemu-options.hx
M system/vl.c
M target/s390x/cpu.c
M target/s390x/cpu.h
Log Message:
-----------
CPU topology: extend with s390 specifics
S390 adds two new SMP levels, drawers and books to the CPU
topology.
S390 CPUs have specific topology features like dedication and
entitlement. These indicate to the guest information on host
vCPU scheduling and help the guest make better scheduling decisions.
Add the new levels to the relevant QAPI structs.
Add all the supported topology levels, dedication and entitlement
as properties to S390 CPUs.
Create machine-common.json so we can later include it in
machine-target.json also.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-3-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: c809bbc8e98cf7fa254fac91084ade0a22877dec
https://github.com/qemu/qemu/commit/c809bbc8e98cf7fa254fac91084ade0a22877dec
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
A hw/s390x/cpu-topology.c
M hw/s390x/meson.build
M hw/s390x/s390-virtio-ccw.c
A include/hw/s390x/cpu-topology.h
Log Message:
-----------
s390x/cpu topology: add topology entries on CPU hotplug
The topology information are attributes of the CPU and are
specified during the CPU device creation.
On hot plug we:
- calculate the default values for the topology for drawers,
books and sockets in the case they are not specified.
- verify the CPU attributes
- check that we have still room on the desired socket
The possibility to insert a CPU in a mask is dependent on the
number of cores allowed in a socket, a book or a drawer, the
checking is done during the hot plug of the CPU to have an
immediate answer.
If the complete topology is not specified, the core is added
in the physical topology based on its core ID and it gets
defaults values for the modifier attributes.
This way, starting QEMU without specifying the topology can
still get some advantage of the CPU topology.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-4-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: f4f54b582f4b78f4cfd5a6912e88aef4f11e3e3c
https://github.com/qemu/qemu/commit/f4f54b582f4b78f4cfd5a6912e88aef4f11e3e3c
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/s390x/cpu-topology.c
M include/hw/s390x/cpu-topology.h
M include/hw/s390x/sclp.h
M qapi/machine-target.json
M target/s390x/cpu.h
M target/s390x/kvm/kvm.c
M target/s390x/kvm/meson.build
A target/s390x/kvm/stsi-topology.c
Log Message:
-----------
target/s390x/cpu topology: handle STSI(15) and build the SYSIB
On interception of STSI(15.1.x) the System Information Block
(SYSIB) is built from the list of pre-ordered topology entries.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-5-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: a67f05b39106bf3477475297d8508bcb7d8eb0d8
https://github.com/qemu/qemu/commit/a67f05b39106bf3477475297d8508bcb7d8eb0d8
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/s390x/sclp.c
M include/hw/s390x/sclp.h
Log Message:
-----------
s390x/sclp: reporting the maximum nested topology entries
The maximum nested topology entries is used by the guest to
know how many nested topology are available on the machine.
Let change the MNEST value from 2 to 4 in the SCLP READ INFO
structure now that we support books and drawers.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-6-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 3d6e75f4df67980479cc0912b842202f2093aeeb
https://github.com/qemu/qemu/commit/3d6e75f4df67980479cc0912b842202f2093aeeb
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/s390x/cpu-topology.h
M target/s390x/cpu-sysemu.c
M target/s390x/cpu.h
M target/s390x/kvm/kvm.c
M target/s390x/kvm/kvm_s390x.h
Log Message:
-----------
s390x/cpu topology: resetting the Topology-Change-Report
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case of a subsystem reset.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-7-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: af37bad52e7c216c044f919d6254c77be0eacbc6
https://github.com/qemu/qemu/commit/af37bad52e7c216c044f919d6254c77be0eacbc6
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M include/hw/s390x/s390-virtio-ccw.h
M target/s390x/kvm/kvm.c
Log Message:
-----------
s390x/cpu topology: interception of PTF instruction
When the host supports the CPU topology facility, the PTF
instruction with function code 2 is interpreted by the SIE,
provided that the userland hypervisor activates the interpretation
by using the KVM_CAP_S390_CPU_TOPOLOGY KVM extension.
The PTF instructions with function code 0 and 1 are intercepted
and must be emulated by the userland hypervisor.
During RESET all CPU of the configuration are placed in
horizontal polarity.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-8-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: f530b9e7dad69511f79bbeb3e6683f854ebf703c
https://github.com/qemu/qemu/commit/f530b9e7dad69511f79bbeb3e6683f854ebf703c
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M target/s390x/cpu_models.c
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/cpu topology: activate CPU topology
The KVM capability KVM_CAP_S390_CPU_TOPOLOGY is used to
activate the S390_FEAT_CONFIGURATION_TOPOLOGY feature and
the topology facility in the host CPU model for the guest
in the case the topology is available in QEMU and in KVM.
The feature is disabled by default and fenced for SE
(secure execution).
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-9-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: a457c2ab5af7d69fd96f0aef2d33800bdc082b8c
https://github.com/qemu/qemu/commit/a457c2ab5af7d69fd96f0aef2d33800bdc082b8c
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M qapi/machine-target.json
Log Message:
-----------
qapi/s390x/cpu topology: set-cpu-topology qmp command
The modification of the CPU attributes are done through a monitor
command.
It allows to move the core inside the topology tree to optimize
the cache usage in the case the host's hypervisor previously
moved the CPU.
The same command allows to modify the CPU attributes modifiers
like polarization entitlement and the dedicated attribute to notify
the guest if the host admin modified scheduling or dedication of a vCPU.
With this knowledge the guest has the possibility to optimize the
usage of the vCPUs.
The command has a feature unstable for the moment.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20231016183925.2384704-10-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: ad2d1afc1d7158e1d94f6f7a3efe6efc15dca51c
https://github.com/qemu/qemu/commit/ad2d1afc1d7158e1d94f6f7a3efe6efc15dca51c
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M qapi/machine.json
M target/s390x/cpu.c
Log Message:
-----------
machine: adding s390 topology to query-cpu-fast
S390x provides two more topology attributes, entitlement and dedication.
Let's add these CPU attributes to the QAPI command query-cpu-fast.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-11-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: bb2df37a6286e24edd6bbad162bc3eef07c97c34
https://github.com/qemu/qemu/commit/bb2df37a6286e24edd6bbad162bc3eef07c97c34
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/core/machine-hmp-cmds.c
Log Message:
-----------
machine: adding s390 topology to info hotpluggable-cpus
S390 topology adds books and drawers topology containers.
Let's add these to the HMP information for hotpluggable cpus.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-12-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 1cfe52b7824067962357493475f0c36c7900f799
https://github.com/qemu/qemu/commit/1cfe52b7824067962357493475f0c36c7900f799
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M qapi/machine-target.json
Log Message:
-----------
qapi/s390x/cpu topology: CPU_POLARIZATION_CHANGE QAPI event
When the guest asks to change the polarization this change
is forwarded to the upper layer using QAPI.
The upper layer is supposed to take according decisions concerning
CPU provisioning.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-13-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 154893a784cb3f1349fce65ab6038e0bc462d218
https://github.com/qemu/qemu/commit/154893a784cb3f1349fce65ab6038e0bc462d218
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M qapi/machine-target.json
Log Message:
-----------
qapi/s390x/cpu topology: add query-s390x-cpu-polarization command
The query-s390x-cpu-polarization qmp command returns the current
CPU polarization of the machine.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-14-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 0d177cdd2ba402f7f0aee301e56037311c7a8781
https://github.com/qemu/qemu/commit/0d177cdd2ba402f7f0aee301e56037311c7a8781
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
M docs/devel/index-internals.rst
A docs/devel/s390-cpu-topology.rst
A docs/system/s390x/cpu-topology.rst
M docs/system/target-s390x.rst
M qapi/machine.json
Log Message:
-----------
docs/s390x/cpu topology: document s390x cpu topology
Add some basic examples for the definition of cpu topology
in s390x.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-15-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: e5bc49d54d94fb680b0f200ae0529dda2c91c8db
https://github.com/qemu/qemu/commit/e5bc49d54d94fb680b0f200ae0529dda2c91c8db
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
A tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology core
Introduction of the s390x cpu topology core functions and
basic tests.
We test the correlation between the command line and
the QMP results in query-cpus-fast for various CPU topology.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-16-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: cb042c73f37e820fe8fe5bdc71cb92836aea5955
https://github.com/qemu/qemu/commit/cb042c73f37e820fe8fe5bdc71cb92836aea5955
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology polarization
Polarization is changed on a request from the guest.
Let's verify the polarization is accordingly set by QEMU.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-17-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 16ab722edb0c308e18364b70a84ef9f7dfd0a946
https://github.com/qemu/qemu/commit/16ab722edb0c308e18364b70a84ef9f7dfd0a946
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology entitlement tests
Test changes in the entitlement from both a guest and a host point of
view, depending on the polarization.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-18-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 471676bfd2e182746b9bb0ff4e613908dc4c8842
https://github.com/qemu/qemu/commit/471676bfd2e182746b9bb0ff4e613908dc4c8842
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology test dedicated CPU
A dedicated CPU in vertical polarization can only have
a high entitlement.
Let's check this from both host and guest point of view.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-19-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 944e03006d0fa17332d4cbf82e26d63c10d320d2
https://github.com/qemu/qemu/commit/944e03006d0fa17332d4cbf82e26d63c10d320d2
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology test socket full
This test verifies that QMP set-cpu-topology does not accept
to overload a socket.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-20-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 22ac7809bbd0dc338836ac9f0e5330c18e13e08c
https://github.com/qemu/qemu/commit/22ac7809bbd0dc338836ac9f0e5330c18e13e08c
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology dedicated errors
Let's test that QEMU refuses to setup a dedicated CPU with
low or medium entitlement.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-21-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 219922ef9b7af4b425c85a7c14c79c2f68f1a19b
https://github.com/qemu/qemu/commit/219922ef9b7af4b425c85a7c14c79c2f68f1a19b
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology bad move
This test verifies that QEMU refuses to move a CPU to an
nonexistent location.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-22-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: c35a79cbd7dc2ff3435355177290b7b31b589993
https://github.com/qemu/qemu/commit/c35a79cbd7dc2ff3435355177290b7b31b589993
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/kvm: Turn KVM_CAP_SYNC_REGS into a hard requirement
Since we already require at least kernel 3.15 in the s390x KVM code,
we can assume that the KVM_CAP_SYNC_REGS capability is always there.
Thus turn this into a hard requirement now.
Reviewed-by: Christian Borntraeger <borntraeger@linux.ibm.com>
Message-ID: <20231011080538.796999-2-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 1d1071665012e378510494e99466c042b3ac1be0
https://github.com/qemu/qemu/commit/1d1071665012e378510494e99466c042b3ac1be0
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/kvm: Simplify the GPRs, ACRs, CRs and prefix synchronization code
KVM_SYNC_GPRS, KVM_SYNC_ACRS, KVM_SYNC_CRS and KVM_SYNC_PREFIX are
available since kernel 3.10. Since we already require at least kernel
3.15 in the s390x KVM code, we can also assume that the KVM_CAP_SYNC_REGS
sync code is always possible for these registers, and remove the
related checks and fallbacks via KVM_SET_REGS and KVM_GET_REGS.
Message-ID: <20231011080538.796999-3-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 18424d9591c73178bdfd6a4518091064db22e1d9
https://github.com/qemu/qemu/commit/18424d9591c73178bdfd6a4518091064db22e1d9
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration-test: Disable the analyze-migration.py test on s390x
The analyze-migration.py script fails on s390x hosts:
Traceback (most recent call last):
File "scripts/analyze-migration.py", line 662, in <module>
dump.read(dump_memory = args.memory)
File "scripts/analyze-migration.py", line 596, in read
classdesc = self.section_classes[section_key]
KeyError: ('s390-storage_attributes', 0)
It obviously never has been adapted to s390x yet, so until this
has been done, disable this test on s390x.
Message-ID: <20231018091239.164452-1-thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 04131e00097c5b85f96af6a66b1c009446c90ec1
https://github.com/qemu/qemu/commit/04131e00097c5b85f96af6a66b1c009446c90ec1
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration-test: Disable the analyze-migration.py test on s390x
The analyze-migration.py script fails on s390x hosts:
Traceback (most recent call last):
File "scripts/analyze-migration.py", line 662, in <module>
dump.read(dump_memory = args.memory)
File "scripts/analyze-migration.py", line 596, in read
classdesc = self.section_classes[section_key]
KeyError: ('s390-storage_attributes', 0)
It obviously never has been adapted to s390x yet, so until this
has been done, disable this test on s390x.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018091239.164452-1-thuth@redhat.com>
Commit: c8a7fc5179c649eed1d4286776a23e8a1a183cdc
https://github.com/qemu/qemu/commit/c8a7fc5179c649eed1d4286776a23e8a1a183cdc
Author: Steve Sistare <steven.sistare@oracle.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M backends/tpm/tpm_emulator.c
M block/parallels.c
M block/qcow.c
M block/vdi.c
M block/vhdx.c
M block/vmdk.c
M block/vpc.c
M block/vvfat.c
M dump/dump.c
M hw/9pfs/9p.c
M hw/display/virtio-gpu-base.c
M hw/intc/arm_gic_kvm.c
M hw/intc/arm_gicv3_its_kvm.c
M hw/intc/arm_gicv3_kvm.c
M hw/misc/ivshmem.c
M hw/ppc/pef.c
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_rtas.c
M hw/remote/proxy.c
M hw/s390x/s390-virtio-ccw.c
M hw/scsi/vhost-scsi.c
M hw/vfio/common.c
M hw/vfio/migration.c
M hw/virtio/vhost.c
M include/migration/blocker.h
M migration/migration.c
M stubs/migr-blocker.c
M target/i386/kvm/kvm.c
M target/i386/nvmm/nvmm-all.c
M target/i386/sev.c
M target/i386/whpx/whpx-all.c
M ui/vdagent.c
Log Message:
-----------
migration: simplify blockers
Modify migrate_add_blocker and migrate_del_blocker to take an Error **
reason. This allows migration to own the Error object, so that if
an error occurs in migrate_add_blocker, migration code can free the Error
and clear the client handle, simplifying client code. It also simplifies
the migrate_del_blocker call site.
In addition, this is a pre-requisite for a proposed future patch that would
add a mode argument to migration requests to support live update, and
maintain a list of blockers for each mode. A blocker may apply to a single
mode or to multiple modes, and passing Error** will allow one Error object
to be registered for multiple modes.
No functional change.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com>
Tested-by: Michael Galaxy <mgalaxy@akamai.com>
Reviewed-by: Michael Galaxy <mgalaxy@akamai.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <1697634216-84215-1-git-send-email-steven.sistare@oracle.com>
Commit: 2c36076a1153e321e32a28b735f5c0fe70d8d10f
https://github.com/qemu/qemu/commit/2c36076a1153e321e32a28b735f5c0fe70d8d10f
Author: Peter Xu <peterx@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M migration/ram.c
Log Message:
-----------
migration: Fix parse_ramblock() on overwritten retvals
It's possible that some errors can be overwritten with success retval later
on, and then ignored. Always capture all errors and report.
Reported by Coverity 1522861, but actually I spot one more in the same
function.
Fixes: CID 1522861
Signed-off-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231017203855.298260-1-peterx@redhat.com>
Commit: d9cda21303a2b92cf3be48b75d4201896aa06857
https://github.com/qemu/qemu/commit/d9cda21303a2b92cf3be48b75d4201896aa06857
Author: Steve Sistare <steven.sistare@oracle.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M hw/net/virtio-net.c
M hw/vfio/migration.c
M include/migration/misc.h
M migration/migration.c
M net/vhost-vdpa.c
M ui/spice-core.c
Log Message:
-----------
migration: simplify notifiers
Pass the callback function to add_migration_state_change_notifier so
that migration can initialize the notifier on add and clear it on
delete, which simplifies the call sites. Shorten the function names
so the extra arg can be added more legibly. Hide the global notifier
list in a new function migration_call_notifiers, and make it externally
visible so future live update code can call it.
No functional change.
Signed-off-by: Steve Sistare <steven.sistare@oracle.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Tested-by: Michael Galaxy <mgalaxy@akamai.com>
Reviewed-by: Michael Galaxy <mgalaxy@akamai.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <1686148954-250144-1-git-send-email-steven.sistare@oracle.com>
Commit: 175e63c9829f9887c04bed8e0c4906e1166c9a87
https://github.com/qemu/qemu/commit/175e63c9829f9887c04bed8e0c4906e1166c9a87
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M migration/multifd.c
Log Message:
-----------
migration/multifd: Stop checking p->quit in multifd_send_thread
We don't need to check p->quit in the multifd_send_thread() because it
is shadowed by the 'exiting' flag. Ever since that flag was added
p->quit became obsolete as a way to stop the thread.
Since p->quit is set at multifd_send_terminate_threads() under the
p->mutex lock, the thread will only see it once it loops, so 'exiting'
will always be seen first.
Note that setting p->quit at multifd_send_terminate_threads() still
makes sense because we need a way to inform multifd_send_pages() that
the channel has stopped.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231012140651.13122-3-farosas@suse.de>
Commit: f4a7b30fcd5b60ca9b0215f9a6fa1faf9bd73f7b
https://github.com/qemu/qemu/commit/f4a7b30fcd5b60ca9b0215f9a6fa1faf9bd73f7b
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/libqtest.c
Log Message:
-----------
tests/qtest: Allow qtest_qemu_binary to use a custom environment variable
We're adding support for testing migration using two different QEMU
binaries. We'll provide the second binary in a new environment
variable.
Allow qtest_qemu_binary() to receive the name of the new variable. If
the new environment variable is not set, that's not an error, we use
QTEST_QEMU_BINARY as a fallback.
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-2-farosas@suse.de>
Commit: 9931215bd33b640dcc824e07431e67e6ddb6b1e1
https://github.com/qemu/qemu/commit/9931215bd33b640dcc824e07431e67e6ddb6b1e1
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
tests/qtest: Introduce qtest_init_with_env
Add a version of qtest_init() that takes an environment variable
containing the path of the QEMU binary. This allows tests to use more
than one QEMU binary.
If no variable is provided or the environment variable does not exist,
that is not an error. Fallback to using QTEST_QEMU_BINARY.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-3-farosas@suse.de>
Commit: 41b2eba4e5c480b8515db60f23b0cb5eeae0dc50
https://github.com/qemu/qemu/commit/41b2eba4e5c480b8515db60f23b0cb5eeae0dc50
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/libqtest.c
Log Message:
-----------
tests/qtest: Allow qtest_get_machines to use an alternate QEMU binary
We're adding support for using more than one QEMU binary in
tests. Modify qtest_get_machines() to take an environment variable
that contains the QEMU binary path.
Since the function keeps a cache of the machines list in the form of a
static variable, refresh it any time the environment variable changes.
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-4-farosas@suse.de>
Commit: 1027fc0ae4fcd24c11a43d1f217a1d11579a574b
https://github.com/qemu/qemu/commit/1027fc0ae4fcd24c11a43d1f217a1d11579a574b
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
tests/qtest: Introduce qtest_has_machine_with_env
Add a variant of qtest_has_machine() that receives an environment
variable containing an alternate QEMU binary path.
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-5-farosas@suse.de>
Commit: a3c0ebc9b09cb15cac35690412eb66aaa5eb4f23
https://github.com/qemu/qemu/commit/a3c0ebc9b09cb15cac35690412eb66aaa5eb4f23
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
tests/qtest: Introduce qtest_resolve_machine_alias
The migration tests are being enhanced to test migration between
different QEMU versions. A requirement of migration is that the
machine type between source and destination matches, including the
version.
We cannot hardcode machine types in the tests because those change
with each release. QEMU provides a machine type alias that has a fixed
name, but points to the latest machine type at each release.
Add a helper to resolve the alias into the exact machine
type. E.g. "-machine pc" resolves to "pc-i440fx-8.2"
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-6-farosas@suse.de>
Commit: dcf389cbc84c2b714d49887775918c5f03f73864
https://github.com/qemu/qemu/commit/dcf389cbc84c2b714d49887775918c5f03f73864
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-helpers.c
M tests/qtest/migration-helpers.h
Log Message:
-----------
tests/qtest/migration: Introduce find_common_machine_version
When using two different QEMU binaries for migration testing, we'll
need to find what is the machine version that will work with both
binaries. Add a helper for that.
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-7-farosas@suse.de>
Commit: c99613910106fd9a79005a3e8f47b1ce7d46dbc4
https://github.com/qemu/qemu/commit/c99613910106fd9a79005a3e8f47b1ce7d46dbc4
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration: Define a machine for all architectures
Stop relying on defaults and select a machine explicitly for every
architecture.
This is a prerequisite for being able to select machine types for
migration using different QEMU binaries for source and destination.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-8-farosas@suse.de>
Commit: 3cb9c6553be28b01761c97768abb41c4b5aaa333
https://github.com/qemu/qemu/commit/3cb9c6553be28b01761c97768abb41c4b5aaa333
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration: Specify the geometry of the bootsector
We're about to enable the x86_64 tests to run with the q35 machine,
but that machine does not work with the program we use to dirty the
memory for the tests.
The issue is that QEMU needs to guess the geometry of the "disk" we
give to it and the guessed geometry doesn't pass the sanity checks
done by SeaBIOS. This causes SeaBIOS to interpret the geometry as if
needing a translation from LBA to CHS and SeaBIOS ends up miscomputing
the number of cylinders and aborting due to that.
The reason things work with the "pc" machine is that is uses ATA
instead of AHCI like q35 and SeaBIOS has an exception for ATA that
ends up skipping the sanity checks and ignoring translation
altogether.
Workaround this situation by specifying a geometry in the command
line.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-9-farosas@suse.de>
Commit: fa35b0cb25775abb95f61e219b14b63084fb7c5a
https://github.com/qemu/qemu/commit/fa35b0cb25775abb95f61e219b14b63084fb7c5a
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration: Set q35 as the default machine for x86_86
Change the x86_64 to use the q35 machines in tests from now on. Keep
testing the pc macine on 32bit.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-10-farosas@suse.de>
Commit: 5050ad2a380832a62c7dedda147bbee06c8fe924
https://github.com/qemu/qemu/commit/5050ad2a380832a62c7dedda147bbee06c8fe924
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration: Support more than one QEMU binary
We have strict rules around migration compatibility between different
QEMU versions but no test to validate the migration state between
different binaries.
Add infrastructure to allow running the migration tests with two
different QEMU binaries as migration source and destination.
The code now recognizes two new environment variables
QTEST_QEMU_BINARY_SRC and QTEST_QEMU_BINARY_DST. In the absence of
either of them, the test will use the QTEST_QEMU_BINARY variable. If
both are missing then the tests are run with single binary as
previously.
The machine type is selected automatically as the latest machine type
version that works with both binaries.
Usage (only one of SRC|DST is allowed):
QTEST_QEMU_BINARY_SRC=../build-8.2.0/qemu-system-x86_64 \
QTEST_QEMU_BINARY=../build-8.1.0/qemu-system-x86_64 \
./tests/qtest/migration-test
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-11-farosas@suse.de>
Commit: 6c6d2330a07d8a1ba1c1613d8631599a072c5544
https://github.com/qemu/qemu/commit/6c6d2330a07d8a1ba1c1613d8631599a072c5544
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/migration-helpers.c
M tests/qtest/migration-helpers.h
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration: Allow user to specify a machine type
Accept the QTEST_QEMU_MACHINE_TYPE environment variable to take a
machine type to use in the tests.
The full machine type is recognized (e.g. pc-q35-8.2). Aliases
(e.g. pc) are also allowed and resolve to the latest machine version
for that alias, or, if using two QEMU binaries, to the latest common
machine version between the two.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231018192741.25885-12-farosas@suse.de>
Commit: 7789331b03ae3bffcb2de925a093796b3b9907ff
https://github.com/qemu/qemu/commit/7789331b03ae3bffcb2de925a093796b3b9907ff
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M tests/qtest/libqtest.c
Log Message:
-----------
tests/qtest: Don't print messages from query instances
Now that we can query more than one binary, the "starting QEMU..."
message can get a little noisy. Mute those messages unless we're
running with --verbose.
Only affects qtest_init() calls from within libqtest. The tests
continue to output as usual.
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-ID: <20231018192741.25885-13-farosas@suse.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Commit: 1712520489194af2b89bff06bf89de4df53dd59a
https://github.com/qemu/qemu/commit/1712520489194af2b89bff06bf89de4df53dd59a
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
M contrib/elf2dmp/addrspace.c
M contrib/elf2dmp/main.c
M contrib/elf2dmp/pdb.c
M contrib/elf2dmp/qemu_elf.c
M docs/system/arm/emulation.rst
M hw/arm/boot.c
M hw/arm/sbsa-ref.c
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/misc/bcm2835_property.c
M hw/nvram/xlnx-bbram.c
M hw/nvram/xlnx-versal-efuse-ctrl.c
M hw/nvram/xlnx-zynqmp-efuse.c
M hw/timer/npcm7xx_timer.c
A include/hw/arm/bsa.h
M include/hw/arm/exynos4210.h
A include/hw/arm/raspberrypi-fw-defs.h
M include/hw/arm/virt.h
R include/hw/misc/raspberrypi-fw-defs.h
M include/hw/nvram/xlnx-bbram.h
M target/arm/arm-powerctl.c
M target/arm/common-semi-target.h
M target/arm/cpu-qom.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/kvm.c
M target/arm/kvm64.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/translate.c
Log Message:
-----------
Merge tag 'pull-target-arm-20231019' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
* hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot'
* xlnx devices: remove deprecated device reset
* xlnx-bbram: hw/nvram: Use dot in device type name
* elf2dmp: fix coverity issues
* elf2dmp: convert to g_malloc, g_new and g_free
* target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
* hw/arm: refactor virt PPI logic
* arm/kvm: convert to kvm_set_one_reg, kvm_get_one_reg
* target/arm: Permit T32 LDM with single register
* smmuv3: Advertise SMMUv3.1-XNX
* target/arm: Implement FEAT_HPMN0
* Remove some unnecessary include lines
* target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
* hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 19 Oct 2023 06:34:22 PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20231019' of
https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits)
contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
target/arm/common-semi-target.h: Remove unnecessary boot.h include
target/arm/kvm64.c: Remove unused include
target/arm: Implement FEAT_HPMN0
hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
hw/arm/smmuv3: Sort ID register setting into field order
hw/arm/smmuv3: Update ID register bit field definitions
target/arm: Permit T32 LDM with single register
arm/kvm: convert to kvm_get_one_reg
arm/kvm: convert to kvm_set_one_reg
hw/arm/sbsa-ref: use bsa.h for PPI definitions
include/hw/arm: move BSA definitions to bsa.h
{include/}hw/arm: refactor virt PPI logic
target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
elf2dmp: check array bounds in pdb_get_file_size
elf2dmp: limit print length for sign_rsds
xlnx-bbram: hw/nvram: Use dot in device type name
xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: fc00b60eb17075b96575aa17dcd80691dcec92e9
https://github.com/qemu/qemu/commit/fc00b60eb17075b96575aa17dcd80691dcec92e9
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M qapi/compat.json
M scripts/qapi/gen.py
M scripts/qapi/parser.py
M scripts/qapi/schema.py
Log Message:
-----------
Merge tag 'pull-qapi-2023-10-19' of https://repo.or.cz/qemu/armbru into
staging
QAPI patches patches for 2023-10-19
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 19 Oct 2023 07:00:34 PDT
# gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* tag 'pull-qapi-2023-10-19' of https://repo.or.cz/qemu/armbru:
qapi: provide a friendly string representation of QAPI classes
qapi: Belatedly update CompatPolicy documentation for unstable
qapi: re-establish linting baseline
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: ae56ad41386983501839cbdad8db71164c9ad19a
https://github.com/qemu/qemu/commit/ae56ad41386983501839cbdad8db71164c9ad19a
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
M docs/interop/vhost-user.rst
M docs/system/target-i386-desc.rst.inc
M hw/acpi/cxl.c
M hw/block/vhost-user-blk.c
M hw/display/virtio-dmabuf.c
M hw/i386/Kconfig
M hw/i386/acpi-build.c
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/isa/Kconfig
M hw/isa/lpc_ich9.c
M hw/isa/meson.build
A hw/isa/piix.c
R hw/isa/piix3.c
R hw/isa/piix4.c
M hw/mips/Kconfig
M hw/mips/malta.c
M hw/scsi/vhost-scsi-common.c
M hw/scsi/vhost-scsi.c
M hw/scsi/vhost-user-scsi.c
M hw/timer/i8254_common.c
M hw/virtio/vhost-backend.c
M hw/virtio/vhost-shadow-virtqueue.c
M hw/virtio/vhost-shadow-virtqueue.h
M hw/virtio/vhost-user-gpio.c
M hw/virtio/vhost-user.c
M hw/virtio/vhost.c
M hw/virtio/virtio.c
M include/exec/memory.h
M include/hw/acpi/cxl.h
M include/hw/i386/pc.h
M include/hw/southbridge/piix.h
M include/hw/virtio/vhost-scsi-common.h
M include/hw/virtio/vhost-user-scsi.h
M include/hw/virtio/vhost-user.h
M include/hw/virtio/vhost.h
M meson.build
M net/vhost-vdpa.c
M subprojects/libvhost-user/libvhost-user.h
A tests/data/acpi/q35/APIC.core-count
M tests/data/acpi/q35/APIC.core-count2
A tests/data/acpi/q35/APIC.thread-count
A tests/data/acpi/q35/APIC.thread-count2
A tests/data/acpi/q35/APIC.type4-count
A tests/data/acpi/q35/DSDT.core-count
M tests/data/acpi/q35/DSDT.core-count2
M tests/data/acpi/q35/DSDT.cxl
A tests/data/acpi/q35/DSDT.thread-count
A tests/data/acpi/q35/DSDT.thread-count2
A tests/data/acpi/q35/DSDT.type4-count
A tests/data/acpi/q35/FACP.core-count
A tests/data/acpi/q35/FACP.thread-count
A tests/data/acpi/q35/FACP.thread-count2
A tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test.c
M tests/unit/test-smp-parse.c
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: features, cleanups
infrastructure for vhost-vdpa shadow work
piix south bridge rework
reconnect for vhost-user-scsi
dummy ACPI QTG DSM for cxl
tests, cleanups, fixes all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# -----BEGIN PGP SIGNATURE-----
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# =NV0t
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 19 Oct 2023 11:20:02 PDT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (78
commits)
intel-iommu: Report interrupt remapping faults, fix return value
MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section
vhost-user: Fix protocol feature bit conflict
tests/acpi: Update DSDT.cxl with QTG DSM
hw/cxl: Add QTG _DSM support for ACPI0017 device
tests/acpi: Allow update of DSDT.cxl
hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range
vhost-user: fix lost reconnect
vhost-user-scsi: start vhost when guest kicks
vhost-user-scsi: support reconnect to backend
vhost: move and rename the conn retry times
vhost-user-common: send get_inflight_fd once
hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
hw/isa/piix: Implement multi-process QEMU support also for PIIX4
hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
hw/isa/piix: Share PIIX3's base class with PIIX4
hw/isa/piix: Harmonize names of reset control memory regions
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 90efb1c9e1ca1b596ba0bd6f03ffa6b847505e54
https://github.com/qemu/qemu/commit/90efb1c9e1ca1b596ba0bd6f03ffa6b847505e54
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M .mailmap
M MAINTAINERS
M chardev/msmouse.c
M chardev/wctablet.c
M hw/acpi/pcihp.c
M hw/arm/virt.c
M hw/block/vhost-user-blk.c
M hw/char/escc.c
M hw/core/cpu-sysemu.c
M hw/display/virtio-gpu.c
M hw/display/xenfb.c
M hw/dma/xilinx_axidma.c
M hw/dma/xlnx-zdma.c
M hw/dma/xlnx_csu_dma.c
M hw/i386/amd_iommu.c
M hw/i386/intel_iommu.c
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/input/adb-kbd.c
M hw/input/hid.c
M hw/input/ps2.c
M hw/input/virtio-input-hid.c
M hw/intc/apic_common.c
M hw/intc/spapr_xive.c
M hw/isa/i82378.c
M hw/isa/isa-bus.c
M hw/loongarch/virt.c
M hw/mips/cps.c
M hw/mips/fuloong2e.c
M hw/mips/jazz.c
M hw/mips/loongson3_virt.c
M hw/mips/malta.c
M hw/mips/mips_int.c
M hw/mips/mipssim.c
M hw/misc/allwinner-r40-dramc.c
M hw/misc/mips_itu.c
M hw/net/cadence_gem.c
M hw/pci-host/bonito.c
M hw/pci-host/sh_pci.c
M hw/pci/pci.c
M hw/ppc/pnv.c
M hw/ppc/pnv_xscom.c
M hw/ppc/spapr_vio.c
M hw/s390x/css-bridge.c
M hw/s390x/sclpquiesce.c
M hw/scsi/virtio-scsi.c
M hw/sd/sdhci.c
M hw/sparc64/sun4u.c
M hw/virtio/virtio-pmem.c
M include/hw/acpi/pcihp.h
M include/hw/audio/pcspk.h
M include/hw/core/cpu.h
M include/hw/core/sysemu-cpu-ops.h
R include/hw/mips/cpudevs.h
M include/hw/misc/mips_itu.h
M include/hw/pci/pci.h
M include/hw/ppc/pnv_xscom.h
M include/hw/virtio/virtio-input.h
M include/sysemu/memory_mapping.h
M include/ui/input.h
M meson.build
M system/memory_mapping.c
M target/i386/arch_memory_mapping.c
M target/i386/cpu.h
M target/mips/cpu.h
M target/mips/sysemu/cp0_timer.c
M target/mips/tcg/sysemu/cp0_helper.c
M target/mips/tcg/sysemu/tlb_helper.c
M ui/input-legacy.c
M ui/input.c
M ui/vdagent.c
M util/cutils.c
Log Message:
-----------
Merge tag 'hw-misc-20231019' of https://github.com/philmd/qemu into staging
Misc hardware patch queue
- MAINTAINERS updates (Zoltan, Thomas)
- Fix cutils::get_relocated_path on Windows host (Akihiko)
- Housekeeping in Memory APIs (Marc-André)
- SDHCI fix for SDMA transfer (Lu, Jianxian)
- Various QOM/QDev/SysBus cleanups (Philippe)
- Constify QemuInputHandler structure (Philippe)
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# gpg: Signature made Thu 19 Oct 2023 14:16:16 PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20231019' of https://github.com/philmd/qemu: (46 commits)
ui/input: Constify QemuInputHandler structure
hw/net: Declare link using static DEFINE_PROP_LINK() macro
hw/dma: Declare link using static DEFINE_PROP_LINK() macro
hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro
hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro
hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros
hw/virtio/virtio-pmem: Replace impossible check by assertion
hw/s390x/css-bridge: Realize sysbus device before accessing it
hw/isa: Realize ISA bridge device before accessing it
hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it
hw/acpi: Realize ACPI_GED sysbus device before accessing it
hw/pci-host/bonito: Do not use SysBus API to map local MMIO region
hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region
hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize
hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region
hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region
hw/audio/pcspk: Inline pcspk_init()
hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region
hw/intc/spapr_xive: Move sysbus_init_mmio() calls around
hw/ppc/pnv: Do not use SysBus API to map local MMIO region
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: e09eff86a517c5de40974a00e3220e3e7781338f
https://github.com/qemu/qemu/commit/e09eff86a517c5de40974a00e3220e3e7781338f
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/hppa/Kconfig
M hw/hppa/hppa_hardware.h
M hw/hppa/machine.c
M hw/input/lasips2.c
M hw/net/tulip.c
M hw/pci-host/Kconfig
A hw/pci-host/astro.c
M hw/pci-host/meson.build
M hw/pci-host/trace-events
A include/hw/pci-host/astro.h
M include/hw/pci/pci_ids.h
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
Log Message:
-----------
Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into
staging
target/hppa: Add emulation of a C3700 HP-PARISC workstation
This series adds a new PA-RISC machine emulation for the HP-PARISC
C3700 workstation.
The physical HP C3700 machine has a PA2.0 (64-bit) CPU, in contrast to
the existing emulation of a B160L workstation which is a 32-bit only
machine and where it's Dino PCI controller isn't 64-bit capable.
With the HP C3700 machine emulation (together with the emulated Astro
Memory controller and the Elroy PCI bridge) it's now possible to
enhance the hppa CPU emulation to support the 64-bit instruction set
in upcoming patches.
Helge
v4 changes:
- Fix testsuite error in astro by adding a realize() implementation
v3 changes:
based on feedback from BALATON Zoltan <balaton@eik.bme.hu>:
- apply paches in different order to bring them logically closer to each other
- update comments in lasips2
- rephrased title and commit message of MAINTAINERS patch
v2 changes:
suggestions by BALATON Zoltan <balaton@eik.bme.hu>:
- merged pci_ids and tulip patch
- dropped comments in lasips2
- mention additional cleanups in patch "Require at least SeaBIOS-hppa version
10"
suggestions by Philippe Mathieu-Daudé <philmd@linaro.org>:
- dropped static pci_bus variable
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 19 Oct 2023 15:51:57 PDT
# gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg: aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603
# Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F
* tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa:
hw/hppa: Add new HP C3700 machine
hw/hppa: Split out machine creation
hw/hppa: Provide RTC and DebugOutputPort on CPU #0
hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg
MAINTAINERS: Update HP-PARISC entries
pci-host: Wire up new Astro/Elroy PCI bridge
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
lasips2: LASI PS/2 devices are not user-createable
pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip
hw/hppa: Require at least SeaBIOS-hppa version 10
target/hppa: Update to SeaBIOS-hppa version 10
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 06bb108ddef93150cbd601da30a7027094730a2f
https://github.com/qemu/qemu/commit/06bb108ddef93150cbd601da30a7027094730a2f
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M MAINTAINERS
M docs/devel/index-internals.rst
A docs/devel/s390-cpu-topology.rst
A docs/system/s390x/cpu-topology.rst
M docs/system/target-s390x.rst
M hw/core/machine-hmp-cmds.c
M hw/core/machine-smp.c
M hw/core/machine.c
M hw/core/qdev-properties-system.c
A hw/s390x/cpu-topology.c
M hw/s390x/meson.build
M hw/s390x/s390-virtio-ccw.c
M hw/s390x/sclp.c
M include/hw/boards.h
M include/hw/qdev-properties-system.h
A include/hw/s390x/cpu-topology.h
M include/hw/s390x/s390-virtio-ccw.h
M include/hw/s390x/sclp.h
A qapi/machine-common.json
M qapi/machine-target.json
M qapi/machine.json
M qapi/meson.build
M qapi/qapi-schema.json
M qemu-options.hx
M system/vl.c
M target/s390x/cpu-sysemu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/cpu_models.c
M target/s390x/kvm/kvm.c
M target/s390x/kvm/kvm_s390x.h
M target/s390x/kvm/meson.build
A target/s390x/kvm/stsi-topology.c
A tests/avocado/s390_topology.py
M tests/qtest/migration-test.c
Log Message:
-----------
Merge tag 'pull-request-2023-10-20' of https://gitlab.com/thuth/qemu into
staging
* s390x CPU topology support
* Simplify the KVM register synchronization code
* Disable the analyze-migration.py test on s390x
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# gpg: Signature made Thu 19 Oct 2023 22:17:55 PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-10-20' of https://gitlab.com/thuth/qemu: (24 commits)
tests/qtest/migration-test: Disable the analyze-migration.py test on s390x
target/s390x/kvm: Simplify the GPRs, ACRs, CRs and prefix synchronization code
target/s390x/kvm: Turn KVM_CAP_SYNC_REGS into a hard requirement
tests/avocado: s390x cpu topology bad move
tests/avocado: s390x cpu topology dedicated errors
tests/avocado: s390x cpu topology test socket full
tests/avocado: s390x cpu topology test dedicated CPU
tests/avocado: s390x cpu topology entitlement tests
tests/avocado: s390x cpu topology polarization
tests/avocado: s390x cpu topology core
docs/s390x/cpu topology: document s390x cpu topology
qapi/s390x/cpu topology: add query-s390x-cpu-polarization command
qapi/s390x/cpu topology: CPU_POLARIZATION_CHANGE QAPI event
machine: adding s390 topology to info hotpluggable-cpus
machine: adding s390 topology to query-cpu-fast
qapi/s390x/cpu topology: set-cpu-topology qmp command
target/s390x/cpu topology: activate CPU topology
s390x/cpu topology: interception of PTF instruction
s390x/cpu topology: resetting the Topology-Change-Report
s390x/sclp: reporting the maximum nested topology entries
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 27ed6389d75bdf5517738c0a08edf7400b67752c
https://github.com/qemu/qemu/commit/27ed6389d75bdf5517738c0a08edf7400b67752c
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-20 (Fri, 20 Oct 2023)
Changed paths:
M backends/tpm/tpm_emulator.c
M block/parallels.c
M block/qcow.c
M block/vdi.c
M block/vhdx.c
M block/vmdk.c
M block/vpc.c
M block/vvfat.c
M dump/dump.c
M hw/9pfs/9p.c
M hw/display/virtio-gpu-base.c
M hw/intc/arm_gic_kvm.c
M hw/intc/arm_gicv3_its_kvm.c
M hw/intc/arm_gicv3_kvm.c
M hw/misc/ivshmem.c
M hw/net/virtio-net.c
M hw/ppc/pef.c
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_rtas.c
M hw/remote/proxy.c
M hw/s390x/s390-virtio-ccw.c
M hw/scsi/vhost-scsi.c
M hw/vfio/common.c
M hw/vfio/migration.c
M hw/virtio/vhost.c
M include/migration/blocker.h
M include/migration/misc.h
M migration/migration.c
M migration/multifd.c
M migration/ram.c
M net/vhost-vdpa.c
M stubs/migr-blocker.c
M target/i386/kvm/kvm.c
M target/i386/nvmm/nvmm-all.c
M target/i386/sev.c
M target/i386/whpx/whpx-all.c
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
M tests/qtest/migration-helpers.c
M tests/qtest/migration-helpers.h
M tests/qtest/migration-test.c
M ui/spice-core.c
M ui/vdagent.c
Log Message:
-----------
Merge tag 'migration-20231020-pull-request' of
https://gitlab.com/juan.quintela/qemu into staging
Migration Pull request (20231020)
In this pull request:
- disable analyze-migration on s390x (thomas)
- Fix parse_ramblock() (peter)
- start merging live update (steve)
- migration-test support for using several binaries (fabiano)
- multifd cleanups (fabiano)
CI: https://gitlab.com/juan.quintela/qemu/-/pipelines/1042492801
Please apply.
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# gpg: Signature made Thu 19 Oct 2023 23:57:15 PDT
# gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723
# gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full]
# gpg: aka "Juan Quintela <quintela@trasno.org>" [full]
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723
* tag 'migration-20231020-pull-request' of
https://gitlab.com/juan.quintela/qemu:
tests/qtest: Don't print messages from query instances
tests/qtest/migration: Allow user to specify a machine type
tests/qtest/migration: Support more than one QEMU binary
tests/qtest/migration: Set q35 as the default machine for x86_86
tests/qtest/migration: Specify the geometry of the bootsector
tests/qtest/migration: Define a machine for all architectures
tests/qtest/migration: Introduce find_common_machine_version
tests/qtest: Introduce qtest_resolve_machine_alias
tests/qtest: Introduce qtest_has_machine_with_env
tests/qtest: Allow qtest_get_machines to use an alternate QEMU binary
tests/qtest: Introduce qtest_init_with_env
tests/qtest: Allow qtest_qemu_binary to use a custom environment variable
migration/multifd: Stop checking p->quit in multifd_send_thread
migration: simplify notifiers
migration: Fix parse_ramblock() on overwritten retvals
migration: simplify blockers
tests/qtest/migration-test: Disable the analyze-migration.py test on s390x
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/0d239e513e01...27ed6389d75b