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[Qemu-commits] [qemu/qemu] ce32a9: target/hppa: Update to SeaBIOS-hppa v
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] ce32a9: target/hppa: Update to SeaBIOS-hppa version 10 |
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Date: |
Thu, 19 Oct 2023 05:29:55 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: ce32a9e9912fd091d5ca7d604ae367b9d705eb87
https://github.com/qemu/qemu/commit/ce32a9e9912fd091d5ca7d604ae367b9d705eb87
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-14 (Sat, 14 Oct 2023)
Changed paths:
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
Log Message:
-----------
target/hppa: Update to SeaBIOS-hppa version 10
Enhancements:
- Initial support for 64-bit CPUs with Astro/Elroy (e.g. C3700
workstation)
- USB support (OHCI)
- better PCI support
- esp-scsi fixes from Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: b88a3306fdfc768f09b2f2a56b739f3d054ce776
https://github.com/qemu/qemu/commit/b88a3306fdfc768f09b2f2a56b739f3d054ce776
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/migration.c
Log Message:
-----------
migration: RDMA is not compatible with anything else
So give an error instead of just ignoring the other methods.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-ID: <20230613145757.10131-4-quintela@redhat.com>
Commit: 809f188a1a874ead74a784977e15dec33100891e
https://github.com/qemu/qemu/commit/809f188a1a874ead74a784977e15dec33100891e
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/migration.c
M migration/ram-compress.c
Log Message:
-----------
migration: Move compression_counters cleanup ram-compress.c
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-ID: <20230613145757.10131-6-quintela@redhat.com>
Commit: 6f609005730d51e085d7404fcfc72576add237e1
https://github.com/qemu/qemu/commit/6f609005730d51e085d7404fcfc72576add237e1
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/migration.c
M migration/ram-compress.c
M migration/ram-compress.h
Log Message:
-----------
migration: Create populate_compress()
So we don't have to access compression_counters from outside
ram-compress.c.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-ID: <20230613145757.10131-7-quintela@redhat.com>
Commit: f504789de509cded05562bb3bb9abfa222446222
https://github.com/qemu/qemu/commit/f504789de509cded05562bb3bb9abfa222446222
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/ram-compress.c
M migration/ram-compress.h
M migration/ram.c
Log Message:
-----------
migration: Create ram_compressed_pages()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-ID: <20230613145757.10131-8-quintela@redhat.com>
Commit: 1fd03d41b86daa1eb8c941dfa013cc806bcaf053
https://github.com/qemu/qemu/commit/1fd03d41b86daa1eb8c941dfa013cc806bcaf053
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/ram-compress.c
M migration/ram-compress.h
M migration/ram.c
Log Message:
-----------
migration: Move update_compress_threads_counts() to ram-compress.c
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-ID: <20230613145757.10131-9-quintela@redhat.com>
Commit: 4703d1958ca149b3baa8df73945c5ddfc9808e73
https://github.com/qemu/qemu/commit/4703d1958ca149b3baa8df73945c5ddfc9808e73
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/ram-compress.c
Log Message:
-----------
migration: Simplify decompress_data_with_multi_threads()
Doing a break to do another break is just confused. Just call return
when we know we want to return.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-ID: <20230613145757.10131-14-quintela@redhat.com>
Commit: bef4e2ed8ea9de96f3c5493deadcd0f33367da2e
https://github.com/qemu/qemu/commit/bef4e2ed8ea9de96f3c5493deadcd0f33367da2e
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/ram-compress.c
Log Message:
-----------
migration: Use "i" as an for index in ram-compress.c
It is used everywhere else in C. Once there, make sure that we don't
use the index outside of the for declaring the variable there.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-ID: <20230613145757.10131-15-quintela@redhat.com>
Commit: 17cd011d06ba91eb8f8f1ba97d0b1be6effcad41
https://github.com/qemu/qemu/commit/17cd011d06ba91eb8f8f1ba97d0b1be6effcad41
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M migration/migration-hmp-cmds.c
Log Message:
-----------
migration: Print block status when needed
The new line was only printed when command options were used. When we
used migration parameters and capabilities, it wasn't.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Message-ID: <20231017172307.22858-2-quintela@redhat.com>
Commit: a536f564d3281014478ef100a0cd1204a47eb9e1
https://github.com/qemu/qemu/commit/a536f564d3281014478ef100a0cd1204a47eb9e1
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Require at least SeaBIOS-hppa version 10
The new SeaBIOS-hppa version 10 includes initial support
for PA2.0 CPUs.
Additionally update copyright and drop commented-out code.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 2e90154eea04c25bd30042ba4d6a9056e781437f
https://github.com/qemu/qemu/commit/2e90154eea04c25bd30042ba4d6a9056e781437f
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/net/tulip.c
M include/hw/pci/pci_ids.h
Log Message:
-----------
pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: a1e6a5c46219bada2c7b932748527553b36559ae
https://github.com/qemu/qemu/commit/a1e6a5c46219bada2c7b932748527553b36559ae
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/input/lasips2.c
Log Message:
-----------
lasips2: LASI PS/2 devices are not user-createable
Those PS/2 ports are created with the LASI controller when
a 32-bit PA-RISC machine is created.
Mark them not user-createable to avoid showing them in
the qemu device list.
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: qemu-stable@nongnu.org
Commit: 506cd36352f0354a0202381c079a8e27ac2fa075
https://github.com/qemu/qemu/commit/506cd36352f0354a0202381c079a8e27ac2fa075
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
A hw/pci-host/astro.c
M hw/pci-host/trace-events
A include/hw/pci-host/astro.h
Log Message:
-----------
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA)
with Elroy PCI host chips.
Later generation Astro chips were named Pluto, Ike and REO.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: d43c5b464e5959210fbde1e66fa42f07ea99bc15
https://github.com/qemu/qemu/commit/d43c5b464e5959210fbde1e66fa42f07ea99bc15
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/hppa/Kconfig
M hw/pci-host/Kconfig
M hw/pci-host/meson.build
Log Message:
-----------
pci-host: Wire up new Astro/Elroy PCI bridge
Allow the Astro source to be built.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 15aa2b7ccc99835e18175a06ee34f68de6254ceb
https://github.com/qemu/qemu/commit/15aa2b7ccc99835e18175a06ee34f68de6254ceb
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update HP-PARISC entries
Add the new HP C3700 machine, the new Astro PCI host and
add the missing entry for the seabios-hppa directory.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 5971abb70dd85f4315678c31800482f6cb29c708
https://github.com/qemu/qemu/commit/5971abb70dd85f4315678c31800482f6cb29c708
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg
Provide necessary info to SeaBIOS-hppa.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: a203004fc37b9a7f7276e9b68b1f9332b516cbde
https://github.com/qemu/qemu/commit/a203004fc37b9a7f7276e9b68b1f9332b516cbde
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/hppa/hppa_hardware.h
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Provide RTC and DebugOutputPort on CPU #0
For SeaBIOS-hppa, the RTC and DebugOutputPort were in the I/O area of
the LASI chip of the emulated B160L machine.
Since we will add other machines without a LASI chip, move the emulated
devices into the I/O area of CPU#0 instead.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 8b44dba3dfa56ea09210a3f15092b45302997333
https://github.com/qemu/qemu/commit/8b44dba3dfa56ea09210a3f15092b45302997333
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Split out machine creation
This is a preparation patch to allow the creation of additional
hppa machine.
It splits out the creation of the machine into a
- machine_HP_common_init_cpus(), and a
- machine_HP_common_init_tail()
function.
This will allow to reuse the basic functions which are common to
all parisc machines.
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 6120e493c9c5b7d2b122f2501ea1c2cc2b64d1e3
https://github.com/qemu/qemu/commit/6120e493c9c5b7d2b122f2501ea1c2cc2b64d1e3
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-17 (Tue, 17 Oct 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Add new HP C3700 machine
Add code to create an emulated C3700 machine.
It includes the following components:
- HP Powerbar SP2 Diva BMC card (serial port only)
- PCI 4x serial card (for serial ports #1-#4)
- USB OHCI controller with USB keyboard and USB mouse
Signed-off-by: Helge Deller <deller@gmx.de>
Commit: 97a47dda3a8141f0dbee9ecd8212d98a6ef30208
https://github.com/qemu/qemu/commit/97a47dda3a8141f0dbee9ecd8212d98a6ef30208
Author: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M qapi/machine.json
Log Message:
-----------
qapi: machine.json: change docs regarding CPU topology
Clarify roles of different architectures.
Also change things a bit in anticipation of additional members being
added.
Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-2-nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
[thuth: Updated some comments according to suggestions from Markus]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: ac722c8f7b7a2f5c4f64df204928d03fd4629ae2
https://github.com/qemu/qemu/commit/ac722c8f7b7a2f5c4f64df204928d03fd4629ae2
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/core/machine-smp.c
M hw/core/machine.c
M hw/core/qdev-properties-system.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/hw/qdev-properties-system.h
A qapi/machine-common.json
M qapi/machine.json
M qapi/meson.build
M qapi/qapi-schema.json
M qemu-options.hx
M system/vl.c
M target/s390x/cpu.c
M target/s390x/cpu.h
Log Message:
-----------
CPU topology: extend with s390 specifics
S390 adds two new SMP levels, drawers and books to the CPU
topology.
S390 CPUs have specific topology features like dedication and
entitlement. These indicate to the guest information on host
vCPU scheduling and help the guest make better scheduling decisions.
Add the new levels to the relevant QAPI structs.
Add all the supported topology levels, dedication and entitlement
as properties to S390 CPUs.
Create machine-common.json so we can later include it in
machine-target.json also.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-3-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: f937f06201ecdb61f458418b4875d5a8fdce6eb6
https://github.com/qemu/qemu/commit/f937f06201ecdb61f458418b4875d5a8fdce6eb6
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M MAINTAINERS
A hw/s390x/cpu-topology.c
M hw/s390x/meson.build
M hw/s390x/s390-virtio-ccw.c
A include/hw/s390x/cpu-topology.h
Log Message:
-----------
s390x/cpu topology: add topology entries on CPU hotplug
The topology information are attributes of the CPU and are
specified during the CPU device creation.
On hot plug we:
- calculate the default values for the topology for drawers,
books and sockets in the case they are not specified.
- verify the CPU attributes
- check that we have still room on the desired socket
The possibility to insert a CPU in a mask is dependent on the
number of cores allowed in a socket, a book or a drawer, the
checking is done during the hot plug of the CPU to have an
immediate answer.
If the complete topology is not specified, the core is added
in the physical topology based on its core ID and it gets
defaults values for the modifier attributes.
This way, starting QEMU without specifying the topology can
still get some advantage of the CPU topology.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-4-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 28c0ac0c760ade7b9829c4195fa189a1c1444ff1
https://github.com/qemu/qemu/commit/28c0ac0c760ade7b9829c4195fa189a1c1444ff1
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/s390x/cpu-topology.c
M include/hw/s390x/cpu-topology.h
M include/hw/s390x/sclp.h
M qapi/machine-target.json
M target/s390x/cpu.h
M target/s390x/kvm/kvm.c
M target/s390x/kvm/meson.build
A target/s390x/kvm/stsi-topology.c
Log Message:
-----------
target/s390x/cpu topology: handle STSI(15) and build the SYSIB
On interception of STSI(15.1.x) the System Information Block
(SYSIB) is built from the list of pre-ordered topology entries.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-5-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 71e3e489dd5cddabbd0c458f5edceec21676dd7b
https://github.com/qemu/qemu/commit/71e3e489dd5cddabbd0c458f5edceec21676dd7b
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/sclp.c
M include/hw/s390x/sclp.h
Log Message:
-----------
s390x/sclp: reporting the maximum nested topology entries
The maximum nested topology entries is used by the guest to
know how many nested topology are available on the machine.
Let change the MNEST value from 2 to 4 in the SCLP READ INFO
structure now that we support books and drawers.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-6-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 7358aeb3c6460cfe35145e78fcbf1d9727820ca8
https://github.com/qemu/qemu/commit/7358aeb3c6460cfe35145e78fcbf1d9727820ca8
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/s390x/cpu-topology.h
M target/s390x/cpu-sysemu.c
M target/s390x/cpu.h
M target/s390x/kvm/kvm.c
M target/s390x/kvm/kvm_s390x.h
Log Message:
-----------
s390x/cpu topology: resetting the Topology-Change-Report
During a subsystem reset the Topology-Change-Report is cleared
by the machine.
Let's ask KVM to clear the Modified Topology Change Report (MTCR)
bit of the SCA in the case of a subsystem reset.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-7-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: cd917d36cecb97e1e245320a3ddf6d24e78b0107
https://github.com/qemu/qemu/commit/cd917d36cecb97e1e245320a3ddf6d24e78b0107
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M include/hw/s390x/s390-virtio-ccw.h
M target/s390x/kvm/kvm.c
Log Message:
-----------
s390x/cpu topology: interception of PTF instruction
When the host supports the CPU topology facility, the PTF
instruction with function code 2 is interpreted by the SIE,
provided that the userland hypervisor activates the interpretation
by using the KVM_CAP_S390_CPU_TOPOLOGY KVM extension.
The PTF instructions with function code 0 and 1 are intercepted
and must be emulated by the userland hypervisor.
During RESET all CPU of the configuration are placed in
horizontal polarity.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-8-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: edd1673ea893f525811ee48bf17634713da38469
https://github.com/qemu/qemu/commit/edd1673ea893f525811ee48bf17634713da38469
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M target/s390x/cpu_models.c
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/cpu topology: activate CPU topology
The KVM capability KVM_CAP_S390_CPU_TOPOLOGY is used to
activate the S390_FEAT_CONFIGURATION_TOPOLOGY feature and
the topology facility in the host CPU model for the guest
in the case the topology is available in QEMU and in KVM.
The feature is disabled by default and fenced for SE
(secure execution).
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-9-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2182142c80354482edff90990012050f25a46ae2
https://github.com/qemu/qemu/commit/2182142c80354482edff90990012050f25a46ae2
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M qapi/machine-target.json
Log Message:
-----------
qapi/s390x/cpu topology: set-cpu-topology qmp command
The modification of the CPU attributes are done through a monitor
command.
It allows to move the core inside the topology tree to optimize
the cache usage in the case the host's hypervisor previously
moved the CPU.
The same command allows to modify the CPU attributes modifiers
like polarization entitlement and the dedicated attribute to notify
the guest if the host admin modified scheduling or dedication of a vCPU.
With this knowledge the guest has the possibility to optimize the
usage of the vCPUs.
The command has a feature unstable for the moment.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20231016183925.2384704-10-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 54de762cef91d7500bbeeebf08aa8248a894fd1e
https://github.com/qemu/qemu/commit/54de762cef91d7500bbeeebf08aa8248a894fd1e
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M qapi/machine.json
M target/s390x/cpu.c
Log Message:
-----------
machine: adding s390 topology to query-cpu-fast
S390x provides two more topology attributes, entitlement and dedication.
Let's add these CPU attributes to the QAPI command query-cpu-fast.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-11-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 9787e0b7ac5cd46b1d3044517bf6d10beda8b65a
https://github.com/qemu/qemu/commit/9787e0b7ac5cd46b1d3044517bf6d10beda8b65a
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/core/machine-hmp-cmds.c
Log Message:
-----------
machine: adding s390 topology to info hotpluggable-cpus
S390 topology adds books and drawers topology containers.
Let's add these to the HMP information for hotpluggable cpus.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-12-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 0261678bd434bbaa46f40a156d335fc0550ed86b
https://github.com/qemu/qemu/commit/0261678bd434bbaa46f40a156d335fc0550ed86b
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M qapi/machine-target.json
Log Message:
-----------
qapi/s390x/cpu topology: CPU_POLARIZATION_CHANGE QAPI event
When the guest asks to change the polarization this change
is forwarded to the upper layer using QAPI.
The upper layer is supposed to take according decisions concerning
CPU provisioning.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-13-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 69fa1467b646530f73ef02205d565edb4c9d9f9b
https://github.com/qemu/qemu/commit/69fa1467b646530f73ef02205d565edb4c9d9f9b
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/cpu-topology.c
M qapi/machine-target.json
Log Message:
-----------
qapi/s390x/cpu topology: add query-s390x-cpu-polarization command
The query-s390x-cpu-polarization qmp command returns the current
CPU polarization of the machine.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-14-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 54d51cfdeeaa1b727e645687b577dfc7ede2597a
https://github.com/qemu/qemu/commit/54d51cfdeeaa1b727e645687b577dfc7ede2597a
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M MAINTAINERS
M docs/devel/index-internals.rst
A docs/devel/s390-cpu-topology.rst
A docs/system/s390x/cpu-topology.rst
M docs/system/target-s390x.rst
M qapi/machine.json
Log Message:
-----------
docs/s390x/cpu topology: document s390x cpu topology
Add some basic examples for the definition of cpu topology
in s390x.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-15-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 294adb51152f804c443dd2114a4ebe13dbd1cff3
https://github.com/qemu/qemu/commit/294adb51152f804c443dd2114a4ebe13dbd1cff3
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M MAINTAINERS
A tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology core
Introduction of the s390x cpu topology core functions and
basic tests.
We test the correlation between the command line and
the QMP results in query-cpus-fast for various CPU topology.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-16-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: cf2b4a633aec618c85f8b7b4d02949724b2a52fd
https://github.com/qemu/qemu/commit/cf2b4a633aec618c85f8b7b4d02949724b2a52fd
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology polarization
Polarization is changed on a request from the guest.
Let's verify the polarization is accordingly set by QEMU.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-17-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: ad34f9144d540f0067b2d5db44c868a5efd9492d
https://github.com/qemu/qemu/commit/ad34f9144d540f0067b2d5db44c868a5efd9492d
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology entitlement tests
Test changes in the entitlement from both a guest and a host point of
view, depending on the polarization.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-18-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2fcabf9ce68b3c20f466146df516fb61923d811d
https://github.com/qemu/qemu/commit/2fcabf9ce68b3c20f466146df516fb61923d811d
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology test dedicated CPU
A dedicated CPU in vertical polarization can only have
a high entitlement.
Let's check this from both host and guest point of view.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231016183925.2384704-19-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 56f0d21b41468d5e6b32700b2430d677fbb3b6de
https://github.com/qemu/qemu/commit/56f0d21b41468d5e6b32700b2430d677fbb3b6de
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology test socket full
This test verifies that QMP set-cpu-topology does not accept
to overload a socket.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-20-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 74889a0c7301ff1c93591de48a312ec5e8e56a34
https://github.com/qemu/qemu/commit/74889a0c7301ff1c93591de48a312ec5e8e56a34
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology dedicated errors
Let's test that QEMU refuses to setup a dedicated CPU with
low or medium entitlement.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-21-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 1f2ae80b15dd76a0eaddea9d07d4e45d1aca6116
https://github.com/qemu/qemu/commit/1f2ae80b15dd76a0eaddea9d07d4e45d1aca6116
Author: Pierre Morel <pmorel@linux.ibm.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/avocado/s390_topology.py
Log Message:
-----------
tests/avocado: s390x cpu topology bad move
This test verifies that QEMU refuses to move a CPU to an
nonexistent location.
Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231016183925.2384704-22-nsg@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 84313097994d67dadcce1ca5cc93c04c48fc7f4c
https://github.com/qemu/qemu/commit/84313097994d67dadcce1ca5cc93c04c48fc7f4c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/s390x/sclpquiesce.c
Log Message:
-----------
hw/s390x: Clean up global variable shadowing in quiesce_powerdown_req()
Fix:
hw/s390x/sclpquiesce.c:90:22: error: declaration shadows a variable in the
global scope [-Werror,-Wshadow]
QuiesceNotifier *qn = container_of(n, QuiesceNotifier, notifier);
^
hw/s390x/sclpquiesce.c:86:3: note: previous declaration is here
} qn;
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231009094747.54240-7-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d637a182b98a082bf0b9cd1853fe3192c7ea88e8
https://github.com/qemu/qemu/commit/d637a182b98a082bf0b9cd1853fe3192c7ea88e8
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M migration/ram.c
Log Message:
-----------
migration: save_compress_page() can take block through pss
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Commit: 944853c201bc229ef02f209d2e6e42ada9d745dd
https://github.com/qemu/qemu/commit/944853c201bc229ef02f209d2e6e42ada9d745dd
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M migration/ram.c
Log Message:
-----------
migration: control_save_page() can take block through pss
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Commit: e8e4e7acd8e2113d900fe6b9a9870daa7ecf1042
https://github.com/qemu/qemu/commit/e8e4e7acd8e2113d900fe6b9a9870daa7ecf1042
Author: Juan Quintela <quintela@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M migration/ram.c
Log Message:
-----------
migration: save_zero_page() can take block through pss
Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Commit: 715edde348358f6d1c3541c7d17245223ddad481
https://github.com/qemu/qemu/commit/715edde348358f6d1c3541c7d17245223ddad481
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/kvm: Turn KVM_CAP_SYNC_REGS into a hard requirement
Since we already require at least kernel 3.15 in the s390x KVM code,
we can assume that the KVM_CAP_SYNC_REGS capability is always there.
Thus turn this into a hard requirement now.
Reviewed-by: Christian Borntraeger <borntraeger@linux.ibm.com>
Message-ID: <20231011080538.796999-2-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 67338a537d16b149e28d852de30dca954a53bc91
https://github.com/qemu/qemu/commit/67338a537d16b149e28d852de30dca954a53bc91
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/kvm: Simplify the GPRs, ACRs, CRs and prefix synchronization code
KVM_SYNC_GPRS, KVM_SYNC_ACRS, KVM_SYNC_CRS and KVM_SYNC_PREFIX are
available since kernel 3.10. Since we already require at least kernel
3.15 in the s390x KVM code, we can also assume that the KVM_CAP_SYNC_REGS
sync code is always possible for these registers, and remove the
related checks and fallbacks via KVM_SET_REGS and KVM_GET_REGS.
Message-ID: <20231011080538.796999-3-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 1a1bd94d4274d30fad9e0faf19591a4336f5c22a
https://github.com/qemu/qemu/commit/1a1bd94d4274d30fad9e0faf19591a4336f5c22a
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest/migration-test: Disable the analyze-migration.py test on s390x
The analyze-migration.py script fails on s390x hosts:
Traceback (most recent call last):
File "scripts/analyze-migration.py", line 662, in <module>
dump.read(dump_memory = args.memory)
File "scripts/analyze-migration.py", line 596, in read
classdesc = self.section_classes[section_key]
KeyError: ('s390-storage_attributes', 0)
It obviously never has been adapted to s390x yet, so until this
has been done, disable this test on s390x.
Message-ID: <20231018091239.164452-1-thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 0e6bff0d43bf04c6e7a16c2775879816ca056b3d
https://github.com/qemu/qemu/commit/0e6bff0d43bf04c6e7a16c2775879816ca056b3d
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Use iovec for vhost_vdpa_net_cvq_add()
Next patches in this series will no longer perform an
immediate poll and check of the device's used buffers
for each CVQ state load command. Consequently, there
will be multiple pending buffers in the shadow VirtQueue,
making it a must for every control command to have its
own buffer.
To achieve this, this patch refactor vhost_vdpa_net_cvq_add()
to accept `struct iovec`, which eliminates the coupling of
control commands to `s->cvq_cmd_out_buffer` and `s->status`,
allowing them to use their own buffer.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<8a328f146fb043f34edb75ba6d043d2d6de88f99.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 327dedb8df91f57ef917ab5b5db519146ee6f08b
https://github.com/qemu/qemu/commit/327dedb8df91f57ef917ab5b5db519146ee6f08b
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load()
Next patches in this series will refactor vhost_vdpa_net_load_cmd()
to iterate through the control commands shadow buffers, allowing QEMU
to send CVQ state load commands in parallel at device startup.
Considering that QEMU always forwards the CVQ command serialized
outside of vhost_vdpa_net_load(), it is more elegant to send the
CVQ commands directly without invoking vhost_vdpa_net_load_*() helpers.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<254f0618efde7af7229ba4fdada667bb9d318991.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 24e59cfe0cb53416b06c2c117bc22ff22dc54df3
https://github.com/qemu/qemu/commit/24e59cfe0cb53416b06c2c117bc22ff22dc54df3
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Check device ack in vhost_vdpa_net_load_rx_mode()
Considering that vhost_vdpa_net_load_rx_mode() is only called
within vhost_vdpa_net_load_rx() now, this patch refactors
vhost_vdpa_net_load_rx_mode() to include a check for the
device's ack, simplifying the code and improving its maintainability.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<68811d52f96ae12d68f0d67d996ac1642a623943.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a864a3219d7e63569583d204c12bff2a0f90463e
https://github.com/qemu/qemu/commit/a864a3219d7e63569583d204c12bff2a0f90463e
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add()
This patch moves vhost_svq_poll() to the caller of
vhost_vdpa_net_cvq_add() and introduces a helper funtion.
By making this change, next patches in this series is
able to refactor vhost_vdpa_net_load_x() only to delay
the polling and checking process until either the SVQ
is full or control commands shadow buffers are full.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<196cadb55175a75275660c6634a538289f027ae3.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1d7e2a8fd4996fdb20d74fce41fe897311f3b06a
https://github.com/qemu/qemu/commit/1d7e2a8fd4996fdb20d74fce41fe897311f3b06a
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Introduce cursors to vhost_vdpa_net_loadx()
This patch introduces two new arugments, `out_cursor`
and `in_cursor`, to vhost_vdpa_net_loadx(). Addtionally,
it includes a helper function
vhost_vdpa_net_load_cursor_reset() for resetting these
cursors.
Furthermore, this patch refactors vhost_vdpa_net_load_cmd()
so that vhost_vdpa_net_load_cmd() prepares buffers
for the device using the cursors arguments, instead
of directly accesses `s->cvq_cmd_out_buffer` and
`s->status` fields.
By making these change, next patches in this series
can refactor vhost_vdpa_net_load_cmd() directly to
iterate through the control commands shadow buffers,
allowing QEMU to send CVQ state load commands in parallel
at device startup.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<1c6516e233a14cc222f0884e148e4e1adceda78d.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 99d6a32469debf1a48921125879b614d15acfb7a
https://github.com/qemu/qemu/commit/99d6a32469debf1a48921125879b614d15acfb7a
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
M hw/virtio/vhost-shadow-virtqueue.h
Log Message:
-----------
vhost: Expose vhost_svq_available_slots()
Next patches in this series will delay the polling
and checking of buffers until either the SVQ is
full or control commands shadow buffers are full,
no longer perform an immediate poll and check of
the device's used buffers for each CVQ state load command.
To achieve this, this patch exposes
vhost_svq_available_slots(), allowing QEMU to know
whether the SVQ is full.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<25938079f0bd8185fd664c64e205e629f7a966be.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: acec5f685c7ad6bd3c9bb9a57d4e509160480376
https://github.com/qemu/qemu/commit/acec5f685c7ad6bd3c9bb9a57d4e509160480376
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Send cvq state load commands in parallel
This patch enables sending CVQ state load commands
in parallel at device startup by following steps:
* Refactor vhost_vdpa_net_load_cmd() to iterate through
the control commands shadow buffers. This allows different
CVQ state load commands to use their own unique buffers.
* Delay the polling and checking of buffers until either
the SVQ is full or control commands shadow buffers are full.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1578
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id:
<9350f32278e39f7bce297b8f2d82dac27c6f8c9a.1697165821.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1908cfd6e1748d94680e468b9df6321087b8fcf2
https://github.com/qemu/qemu/commit/1908cfd6e1748d94680e468b9df6321087b8fcf2
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Restore hash calculation state
This patch introduces vhost_vdpa_net_load_rss() to restore
the hash calculation state at device's startup.
Note that vhost_vdpa_net_load_rss() has `do_rss` argument,
which allows future code to reuse this function to restore
the receive-side scaling state when the VIRTIO_NET_F_RSS
feature is enabled in SVQ. Currently, vhost_vdpa_net_load_rss()
could only be invoked when `do_rss` is set to false.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<f5ffad10699001107022851e0560cb394039d6b0.1693297766.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8fa37f3529265496ffe6546105152b379ae222b8
https://github.com/qemu/qemu/commit/8fa37f3529265496ffe6546105152b379ae222b8
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Allow VIRTIO_NET_F_HASH_REPORT in SVQ
Enable SVQ with VIRTIO_NET_F_HASH_REPORT feature.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<a67d4abc2c8c5c7636addc729daa5432fa8193bd.1693297766.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d81b1e625ed823096e173e92b91d56f825d50fe9
https://github.com/qemu/qemu/commit/d81b1e625ed823096e173e92b91d56f825d50fe9
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Add SetSteeringEBPF method for NetClientState
At present, to enable the VIRTIO_NET_F_RSS feature, eBPF must
be loaded for the vhost backend.
Given that vhost-vdpa is one of the vhost backend, we need to
implement the SetSteeringEBPF method to support RSS for vhost-vdpa,
even if vhost-vdpa calculates the rss hash in the hardware device
instead of in the kernel by eBPF.
Although this requires QEMU to be compiled with `--enable-bpf`
configuration even if the vdpa device does not use eBPF to
calculate the rss hash, this can avoid adding the specific
conditional statements for vDPA case to enable the VIRTIO_NET_F_RSS
feature, which reduces code maintainbility.
Suggested-by: Eugenio Pérez <eperezma@redhat.com>
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<30509e3c3b07bcadd95d5932aeb16820cb022902.1693299194.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 49f5836bacfb9d4bb96d29f16d04822d64e0ad52
https://github.com/qemu/qemu/commit/49f5836bacfb9d4bb96d29f16d04822d64e0ad52
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Restore receive-side scaling state
This patch reuses vhost_vdpa_net_load_rss() with some
refactorings to restore the receive-side scaling state
at device's startup.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<47b17e160ba4e55b24790b7d73b22d2b437ebe3c.1693299194.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aa3f4bcf7ea05df09c30b193e752b2d71db06148
https://github.com/qemu/qemu/commit/aa3f4bcf7ea05df09c30b193e752b2d71db06148
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Allow VIRTIO_NET_F_RSS in SVQ
Enable SVQ with VIRTIO_NET_F_RSS feature.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<2d2a378291bfac4144a0c0c473cf80415bb580b3.1693299194.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fd95464d7111b89f676a6f39576cd7cb1c074074
https://github.com/qemu/qemu/commit/fd95464d7111b89f676a6f39576cd7cb1c074074
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/unit/test-smp-parse.c
Log Message:
-----------
tests: test-smp-parse: Add the test for cores/threads per socket helpers
Use the different ways to calculate cores/threads per socket, so that
the new CPU topology levels won't be missed in these 2 helpes:
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
threads per socket").
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-2-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a70daba18aff95f0f3a29d4d80eabe35510dae1e
https://github.com/qemu/qemu/commit/a70daba18aff95f0f3a29d4d80eabe35510dae1e
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.type4-count
A tests/data/acpi/q35/DSDT.type4-count
A tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count
test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 count.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-3-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 335c9675408d8b72a31f5fd34ca7cdfc219968fe
https://github.com/qemu/qemu/commit/335c9675408d8b72a31f5fd34ca7cdfc219968fe
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 count
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
calculation").
In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built
for each socket, so the count of type4 tables should be equal to the
number of sockets.
Thus for the topology in this case, there're the following considerations:
1. The topology should include multiple sockets to ensure smbios could
create type4 tables for each socket.
2. In addition to sockets, for the more general topology, we should also
configure as many topology levels as possible (multiple dies, no
module since x86 hasn't supported it), to ensure that smbios is able
to exclude the effect of other topology levels to create the type4
tables only for sockets.
3. The original miscalculation bug also misused "smp.cpus", so it's
necessary to configure "cpus" (presented threads for machine) and
"maxcpus" (total threads for machine) as well to make sure that
configuring unpluged CPUs in smp (cpus < maxcpus) does not affect
the correctness of the count of type4 tables.
Based on these considerations, select the topology as the follow:
-smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3
The expected count of type4 tables = sockets (5).
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-4-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5b080806b8bdffca8952c2db89d1105b4df4e665
https://github.com/qemu/qemu/commit/5b080806b8bdffca8952c2db89d1105b4df4e665
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.type4-count
M tests/data/acpi/q35/DSDT.type4-count
M tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000430
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : C5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
+[3E5h 0997 1] Length : 08
+[3E6h 0998 1] Processor ID : 77
+[3E7h 0999 1] Local Apic ID : 9E
+[3E8h 1000 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
+[3EDh 1005 1] Length : 0C
+[3EEh 1006 1] I/O Apic ID : 00
+[3EFh 1007 1] Reserved : 00
+[3F0h 1008 4] Address : FEC00000
+[3F4h 1012 4] Interrupt : 00000000
+
+[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
+[3F9h 1017 1] Length : 0A
+[3FAh 1018 1] Bus : 00
+[3FBh 1019 1] Source : 00
+[3FCh 1020 4] Interrupt : 00000002
+[400h 1024 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
+[403h 1027 1] Length : 0A
+[404h 1028 1] Bus : 00
+[405h 1029 1] Source : 05
+[406h 1030 4] Interrupt : 00000005
+[40Ah 1034 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
+[40Dh 1037 1] Length : 0A
+[40Eh 1038 1] Bus : 00
+[40Fh 1039 1] Source : 09
+[410h 1040 4] Interrupt : 00000009
+[414h 1044 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
+[417h 1047 1] Length : 0A
+[418h 1048 1] Bus : 00
+[419h 1049 1] Source : 0A
+[41Ah 1050 4] Interrupt : 0000000A
+[41Eh 1054 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
+[421h 1057 1] Length : 0A
+[422h 1058 1] Bus : 00
+[423h 1059 1] Source : 0B
+[424h 1060 4] Interrupt : 0000000B
+[428h 1064 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
+[42Bh 1067 1] Length : 06
+[42Ch 1068 1] Processor ID : FF
+[42Dh 1069 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[42Fh 1071 1] Interrupt Input LINT : 01
+
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000489D (18589)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDB
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
[snip]
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C077, 0x77, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x77))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 //
..w.....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x77)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x77, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-5-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7b2522a83f744f8fbadfa03c05c2076b5d12535c
https://github.com/qemu/qemu/commit/7b2522a83f744f8fbadfa03c05c2076b5d12535c
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.core-count
A tests/data/acpi/q35/DSDT.core-count
A tests/data/acpi/q35/FACP.core-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core
count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 core count
field.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-6-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 91320097ee799a31facb8c6d16efacd4ddc41a3f
https://github.com/qemu/qemu/commit/91320097ee799a31facb8c6d16efacd4ddc41a3f
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 core count
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
cores in the socket is not more than 255, then smbios type4 table
encodes cores per socket into the core count field.
So for the topology in this case, there're the following considerations:
1. cores per socket should be not more than 255 to ensure we could cover
the core count field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count field is correct.
Based on these considerations, select the topology with multiple sockets
and dies:
-smp 54,sockets=2,dies=3,cores=3,threads=3
The expected core count = cores per socket = cores (3) * dies (3) = 9.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-7-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ece9021e24c95b43cb36aa4cdb7bd38be753d98f
https://github.com/qemu/qemu/commit/ece9021e24c95b43cb36aa4cdb7bd38be753d98f
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.core-count
M tests/data/acpi/q35/DSDT.core-count
M tests/data/acpi/q35/FACP.core-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count
test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 3C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID:
Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) //
_CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
[snip]
+ If ((Arg0 == 0x35))
+ {
+ Notify (C035, Arg1)
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 //
..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-8-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5a91859db1e0d2909c454d45a5b6696814db24b0
https://github.com/qemu/qemu/commit/5a91859db1e0d2909c454d45a5b6696814db24b0
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core
count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be changed about the type 4 core count2
test case.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-9-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4d47fd5f5bdc030b1c6054c43e932d69a1c7580f
https://github.com/qemu/qemu/commit/4d47fd5f5bdc030b1c6054c43e932d69a1c7580f
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Extend smbios core count2 test to cover general
topology
The commit 196ea60a734c3 ("hw/smbios: Fix core count in type4") fixed
the miscalculation of cores per socket.
The original core count2 test (with the topology configured by
"-smp 275") didn't recognize that topology-related but because it just
created a special topology with only one socket and one die by default,
ignoring the effect of more topology levels (between socket and core) on
the cores per socket calculation.
So for the topology in this case, there're the following considerations:
1. cores per socket should be more than 255 to ensure we could cover
the core count2 field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (mutiple
sockets or dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count2 field is correct.
Based on these considerations, select the topology with multiple dies:
-smp 260,dies=2,cores=130,threads=1
Note, here we doesn't configure multiple sockets to avoid the error
("kvm_init_vcpu: kvm_get_vcpu failed (*): Too many open files") if user
uses the default ulimit seeting on his machine.
And the cores per socket calculation for multiple sockets has already
been covered by the core count test case, so that only multiple dies
configuration is enough.
The expected core count2 = cores per socket = cores (130) * dies (2) =
260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-10-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9d09a20bf422a8587b74cd468b6d2838e285d95a
https://github.com/qemu/qemu/commit/9d09a20bf422a8587b74cd468b6d2838e285d95a
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.core-count2
M tests/data/acpi/q35/DSDT.core-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Update ACPI table binaries for smbios core count2
test
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51
2023
+ * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
-[004h 0004 4] Table Length : 000009AE
+[004h 0004 4] Table Length : 00000CA6
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : CE
+[009h 0009 1] Checksum : FA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
@@ -1051,1256 +1051,1136 @@
[42Ch 1068 1] Subtable Type : 00 [Processor Local APIC]
[42Dh 1069 1] Length : 08
[42Eh 1070 1] Processor ID : 80
[42Fh 1071 1] Local Apic ID : 80
[430h 1072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
[435h 1077 1] Length : 08
[436h 1078 1] Processor ID : 81
[437h 1079 1] Local Apic ID : 81
[438h 1080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
-[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC]
-[43Dh 1085 1] Length : 08
-[43Eh 1086 1] Processor ID : 82
-[43Fh 1087 1] Local Apic ID : 82
-[440h 1088 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
-
-[444h 1092 1] Subtable Type : 00 [Processor Local APIC]
-[445h 1093 1] Length : 08
-[446h 1094 1] Processor ID : 83
-[447h 1095 1] Local Apic ID : 83
-[448h 1096 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
[snip]
-
-[964h 2404 1] Subtable Type : 01 [I/O APIC]
-[965h 2405 1] Length : 0C
-[966h 2406 1] I/O Apic ID : 00
-[967h 2407 1] Reserved : 00
-[968h 2408 4] Address : FEC00000
-[96Ch 2412 4] Interrupt : 00000000
-
-[970h 2416 1] Subtable Type : 02 [Interrupt Source Override]
-[971h 2417 1] Length : 0A
-[972h 2418 1] Bus : 00
-[973h 2419 1] Source : 00
-[974h 2420 4] Interrupt : 00000002
-[978h 2424 2] Flags (decoded below) : 0000
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
+
+[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC]
+[44Dh 1101 1] Length : 10
+[44Eh 1102 2] Reserved : 0000
+[450h 1104 4] Processor x2Apic ID : 00000101
+[454h 1108 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[458h 1112 4] Processor UID : 00000083
+
[snip]
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override]
-[97Bh 2427 1] Length : 0A
-[97Ch 2428 1] Bus : 00
-[97Dh 2429 1] Source : 05
-[97Eh 2430 4] Interrupt : 00000005
-[982h 2434 2] Flags (decoded below) : 000D
+[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override]
+[C73h 3187 1] Length : 0A
+[C74h 3188 1] Bus : 00
+[C75h 3189 1] Source : 05
+[C76h 3190 4] Interrupt : 00000005
+[C7Ah 3194 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[984h 2436 1] Subtable Type : 02 [Interrupt Source Override]
-[985h 2437 1] Length : 0A
-[986h 2438 1] Bus : 00
-[987h 2439 1] Source : 09
-[988h 2440 4] Interrupt : 00000009
-[98Ch 2444 2] Flags (decoded below) : 000D
+[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override]
+[C7Dh 3197 1] Length : 0A
+[C7Eh 3198 1] Bus : 00
+[C7Fh 3199 1] Source : 09
+[C80h 3200 4] Interrupt : 00000009
+[C84h 3204 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override]
-[98Fh 2447 1] Length : 0A
-[990h 2448 1] Bus : 00
-[991h 2449 1] Source : 0A
-[992h 2450 4] Interrupt : 0000000A
-[996h 2454 2] Flags (decoded below) : 000D
+[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override]
+[C87h 3207 1] Length : 0A
+[C88h 3208 1] Bus : 00
+[C89h 3209 1] Source : 0A
+[C8Ah 3210 4] Interrupt : 0000000A
+[C8Eh 3214 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[998h 2456 1] Subtable Type : 02 [Interrupt Source Override]
-[999h 2457 1] Length : 0A
-[99Ah 2458 1] Bus : 00
-[99Bh 2459 1] Source : 0B
-[99Ch 2460 4] Interrupt : 0000000B
-[9A0h 2464 2] Flags (decoded below) : 000D
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI]
-[9A3h 2467 1] Length : 0C
-[9A4h 2468 2] Flags (decoded below) : 0000
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[9A6h 2470 4] Processor UID : FFFFFFFF
-[9AAh 2474 1] Interrupt Input LINT : 01
-[9ABh 2475 3] Reserved : 000000
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51
2023
+ * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00007EEF (32495)
+ * Length 0x000083EA (33770)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x52
+ * Checksum 0x01
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\)
{
OperationRegion (DBG, SystemIO, 0x0402, One)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DBGB, 8
}
@@ -4196,107 +4196,32 @@
}
If ((Arg0 == 0x0101))
{
Notify (C101, Arg1)
}
If ((Arg0 == 0x0102))
{
Notify (C102, Arg1)
}
If ((Arg0 == 0x0103))
{
Notify (C103, Arg1)
}
-
- If ((Arg0 == 0x0104))
- {
- Notify (C104, Arg1)
- }
-
- If ((Arg0 == 0x0105))
- {
- Notify (C105, Arg1)
- }
-
- If ((Arg0 == 0x0106))
- {
- Notify (C106, Arg1)
- }
-
[snip]
- If ((Arg0 == 0x0112))
- {
- Notify (C112, Arg1)
- }
}
Method (CSTA, 1, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
If ((\_SB.PCI0.PRES.CPEN == One))
{
Local0 = 0x0F
}
Release (\_SB.PCI0.PRES.CPLK)
Return (Local0)
}
@@ -4306,33 +4231,33 @@
\_SB.PCI0.PRES.CSEL = Arg0
\_SB.PCI0.PRES.CEJ0 = One
Release (\_SB.PCI0.PRES.CPLK)
}
Method (CSCN, 0, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
{
Local4 = Zero
Local0 = One
Local1 = Zero
- While (((Local0 == One) && (Local3 < 0x0113)))
+ While (((Local0 == One) && (Local3 < 0x0104)))
{
Local0 = Zero
\_SB.PCI0.PRES.CSEL = Local3
\_SB.PCI0.PRES.CCMD = Zero
If ((\_SB.PCI0.PRES.CDAT < Local3))
{
Break
}
If ((Local1 == 0xFF))
{
Local4 = One
Break
}
Local3 = \_SB.PCI0.PRES.CDAT
@@ -7220,3281 +7145,3281 @@
Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
{
0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 //
........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x81)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x81, Arg0, Arg1, Arg2)
}
}
- Processor (C082, 0x82, 0x00000000, 0x00)
+ Device (C082)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x82) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x82))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x82)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x82, Arg0, Arg1, Arg2)
}
}
- Processor (C083, 0x83, 0x00000000, 0x00)
+ Device (C083)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x83) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x83))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x83)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x83, Arg0, Arg1, Arg2)
}
}
- Processor (C084, 0x84, 0x00000000, 0x00)
+ Device (C084)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x84) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x84))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x84)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x84, Arg0, Arg1, Arg2)
}
}
[snip]
- Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ Device (C0FE)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0xFE) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0xFE))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00,
0x00, // ....|...
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0xFE)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0xFE, Arg0, Arg1, Arg2)
}
}
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-11-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 03a8efb80813ef2a77be59de9ce41f2399b371d2
https://github.com/qemu/qemu/commit/03a8efb80813ef2a77be59de9ce41f2399b371d2
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.thread-count
A tests/data/acpi/q35/DSDT.thread-count
A tests/data/acpi/q35/FACP.thread-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4
thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-12-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 706fa69cfc9f3a4cf7677583cce31d742c0d2712
https://github.com/qemu/qemu/commit/706fa69cfc9f3a4cf7677583cce31d742c0d2712
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 thread count
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is not more than 255, then smbios type4 table
encodes threads per socket into the thread count field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be not more than 255 to ensure we could
cover the thread count field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count field.
Based on these considerations, select the topology as the follow:
-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3
The expected thread count = threads per socket = threads (3) * cores (3)
* dies (3) = 27.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20230928125943.1816922-13-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fc33930bd407244456561ffa64bbb1b9233f5007
https://github.com/qemu/qemu/commit/fc33930bd407244456561ffa64bbb1b9233f5007
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.thread-count
M tests/data/acpi/q35/DSDT.thread-count
M tests/data/acpi/q35/FACP.thread-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread
count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 63
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 //
..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-14-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 76869a486c0150cb66492bcd254e245d3d238161
https://github.com/qemu/qemu/commit/76869a486c0150cb66492bcd254e245d3d238161
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
A tests/data/acpi/q35/APIC.thread-count2
A tests/data/acpi/q35/DSDT.thread-count2
A tests/data/acpi/q35/FACP.thread-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4
thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count2 field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-15-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2b04a1eaf75f0a94b40be865198ab746cfb3034d
https://github.com/qemu/qemu/commit/2b04a1eaf75f0a94b40be865198ab746cfb3034d
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 thread count2
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is more than 255, then smbios type4 table encodes
threads per socket into the thread count2 field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be more than 255 to ensure we could cover
the thread count2 field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count2 field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count2 field.
Based on these considerations, select the topology as the follow:
-smp cpus=210,maxcpus=520,sockets=2,dies=2,cores=65,threads=2
The expected thread count2 = threads per socket = threads (2)
* cores (65) * dies (2) = 260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-16-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7b78c88ebbfa5668971fe487481381e8936fe9df
https://github.com/qemu/qemu/commit/7b78c88ebbfa5668971fe487481381e8936fe9df
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/data/acpi/q35/APIC.thread-count2
M tests/data/acpi/q35/DSDT.thread-count2
M tests/data/acpi/q35/FACP.thread-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread
count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-WOA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-UMA191, Wed Aug 23 22:29:53 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00001CE6
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : CA
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
+[435h 1077 1] Length : 08
+[436h 1078 1] Processor ID : 81
+[437h 1079 1] Local Apic ID : 81
+[438h 1080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
[snip]
+[1C8Ch 7308 1] Subtable Type : 09 [Processor Local x2APIC]
+[1C8Dh 7309 1] Length : 10
+[1C8Eh 7310 2] Reserved : 0000
+[1C90h 7312 4] Processor x2Apic ID : 00000381
+[1C94h 7316 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[1C98h 7320 4] Processor UID : 00000207
+
+[1C9Ch 7324 1] Subtable Type : 01 [I/O APIC]
+[1C9Dh 7325 1] Length : 0C
+[1C9Eh 7326 1] I/O Apic ID : 00
+[1C9Fh 7327 1] Reserved : 00
+[1CA0h 7328 4] Address : FEC00000
+[1CA4h 7332 4] Interrupt : 00000000
+
+[1CA8h 7336 1] Subtable Type : 02 [Interrupt Source Override]
+[1CA9h 7337 1] Length : 0A
+[1CAAh 7338 1] Bus : 00
+[1CABh 7339 1] Source : 00
+[1CACh 7340 4] Interrupt : 00000002
+[1CB0h 7344 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1CB2h 7346 1] Subtable Type : 02 [Interrupt Source Override]
+[1CB3h 7347 1] Length : 0A
+[1CB4h 7348 1] Bus : 00
+[1CB5h 7349 1] Source : 05
+[1CB6h 7350 4] Interrupt : 00000005
+[1CBAh 7354 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CBCh 7356 1] Subtable Type : 02 [Interrupt Source Override]
+[1CBDh 7357 1] Length : 0A
+[1CBEh 7358 1] Bus : 00
+[1CBFh 7359 1] Source : 09
+[1CC0h 7360 4] Interrupt : 00000009
+[1CC4h 7364 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CC6h 7366 1] Subtable Type : 02 [Interrupt Source Override]
+[1CC7h 7367 1] Length : 0A
+[1CC8h 7368 1] Bus : 00
+[1CC9h 7369 1] Source : 0A
+[1CCAh 7370 4] Interrupt : 0000000A
+[1CCEh 7374 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CD0h 7376 1] Subtable Type : 02 [Interrupt Source Override]
+[1CD1h 7377 1] Length : 0A
+[1CD2h 7378 1] Bus : 00
+[1CD3h 7379 1] Source : 0B
+[1CD4h 7380 4] Interrupt : 0000000B
+[1CD8h 7384 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1CDAh 7386 1] Subtable Type : 0A [Local x2APIC NMI]
+[1CDBh 7387 1] Length : 0C
+[1CDCh 7388 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[1CDEh 7390 4] Processor UID : FFFFFFFF
+[1CE2h 7394 1] Interrupt Input LINT : 01
+[1CE3h 7395 3] Reserved : 000000
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-LWJ191, Wed Aug 23 22:29:53 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000F8B7 (63671)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xB7
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x81))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x81)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x81, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20230928125943.1816922-17-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b5d1fc465e97e2d8ff6ad86e986ea378978b8948
https://github.com/qemu/qemu/commit/b5d1fc465e97e2d8ff6ad86e986ea378978b8948
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: strip superfluous whitespace
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-2-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: af367c0813ed9c8ec1c95b3494fb57c7e3afb47a
https://github.com/qemu/qemu/commit/af367c0813ed9c8ec1c95b3494fb57c7e3afb47a
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: tighten "reply_supported" scope in "set_vring_addr"
In the vhost_user_set_vring_addr() function, we calculate
"reply_supported" unconditionally, even though we'll only need it if
"wait_for_reply" is also true.
Restrict the scope of "reply_supported" to the minimum.
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-3-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a5c395913c02a0cc2990dcda1225d3006c60190a
https://github.com/qemu/qemu/commit/a5c395913c02a0cc2990dcda1225d3006c60190a
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: factor out "vhost_user_write_sync"
The tails of the "vhost_user_set_vring_addr" and "vhost_user_set_u64"
functions are now byte-for-byte identical. Factor the common tail out to a
new function called "vhost_user_write_sync".
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-4-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 999280bc8c079d5ff9d956bfb598a2f1a42bc682
https://github.com/qemu/qemu/commit/999280bc8c079d5ff9d956bfb598a2f1a42bc682
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: flatten "enforce_reply" into "vhost_user_write_sync"
At this point, only "vhost_user_write_sync" calls "enforce_reply"; embed
the latter into the former.
This is purely refactoring -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-5-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1769f7b19207998b62e8a46b267f3ccfab6becbb
https://github.com/qemu/qemu/commit/1769f7b19207998b62e8a46b267f3ccfab6becbb
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: hoist "write_sync", "get_features", "get_u64"
In order to avoid a forward-declaration for "vhost_user_write_sync" in a
subsequent patch, hoist "vhost_user_write_sync" ->
"vhost_user_get_features" -> "vhost_user_get_u64" just above
"vhost_set_vring".
This is purely code movement -- no observable change.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-6-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3c501fe5baf0a50cda8f6da2d80c5f5c7c5c6eaf
https://github.com/qemu/qemu/commit/3c501fe5baf0a50cda8f6da2d80c5f5c7c5c6eaf
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: allow "vhost_set_vring" to wait for a reply
The "vhost_set_vring" function already centralizes the common parts of
"vhost_user_set_vring_num", "vhost_user_set_vring_base" and
"vhost_user_set_vring_enable". We'll want to allow some of those callers
to wait for a reply.
Therefore, rebase "vhost_set_vring" from just "vhost_user_write" to
"vhost_user_write_sync", exposing the "wait_for_reply" parameter.
This is purely refactoring -- there is no observable change. That's
because:
- all three callers pass in "false" for "wait_for_reply", which disables
all logic in "vhost_user_write_sync" except the call to
"vhost_user_write";
- the fds=NULL and fd_num=0 arguments of the original "vhost_user_write"
call inside "vhost_set_vring" are hard-coded within
"vhost_user_write_sync".
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-7-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 77b9150c60b3f26ea235cb7058b9b24bca6234f8
https://github.com/qemu/qemu/commit/77b9150c60b3f26ea235cb7058b9b24bca6234f8
Author: Laszlo Ersek <lersek@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously
(1) The virtio-1.2 specification
<http://docs.oasis-open.org/virtio/virtio/v1.2/virtio-v1.2.html> writes:
> 3 General Initialization And Device Operation
> 3.1 Device Initialization
> 3.1.1 Driver Requirements: Device Initialization
>
> [...]
>
> 7. Perform device-specific setup, including discovery of virtqueues for
> the device, optional per-bus setup, reading and possibly writing the
> device’s virtio configuration space, and population of virtqueues.
>
> 8. Set the DRIVER_OK status bit. At this point the device is “live”.
and
> 4 Virtio Transport Options
> 4.1 Virtio Over PCI Bus
> 4.1.4 Virtio Structure PCI Capabilities
> 4.1.4.3 Common configuration structure layout
> 4.1.4.3.2 Driver Requirements: Common configuration structure layout
>
> [...]
>
> The driver MUST configure the other virtqueue fields before enabling the
> virtqueue with queue_enable.
>
> [...]
(The same statements are present in virtio-1.0 identically, at
<http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.html>.)
These together mean that the following sub-sequence of steps is valid for
a virtio-1.0 guest driver:
(1.1) set "queue_enable" for the needed queues as the final part of device
initialization step (7),
(1.2) set DRIVER_OK in step (8),
(1.3) immediately start sending virtio requests to the device.
(2) When vhost-user is enabled, and the VHOST_USER_F_PROTOCOL_FEATURES
special virtio feature is negotiated, then virtio rings start in disabled
state, according to
<https://qemu-project.gitlab.io/qemu/interop/vhost-user.html#ring-states>.
In this case, explicit VHOST_USER_SET_VRING_ENABLE messages are needed for
enabling vrings.
Therefore setting "queue_enable" from the guest (1.1) -- which is
technically "buffered" on the QEMU side until the guest sets DRIVER_OK
(1.2) -- is a *control plane* operation, which -- after (1.2) -- travels
from the guest through QEMU to the vhost-user backend, using a unix domain
socket.
Whereas sending a virtio request (1.3) is a *data plane* operation, which
evades QEMU -- it travels from guest to the vhost-user backend via
eventfd.
This means that operations ((1.1) + (1.2)) and (1.3) travel through
different channels, and their relative order can be reversed, as perceived
by the vhost-user backend.
That's exactly what happens when OVMF's virtiofs driver (VirtioFsDxe) runs
against the Rust-language virtiofsd version 1.7.2. (Which uses version
0.10.1 of the vhost-user-backend crate, and version 0.8.1 of the vhost
crate.)
Namely, when VirtioFsDxe binds a virtiofs device, it goes through the
device initialization steps (i.e., control plane operations), and
immediately sends a FUSE_INIT request too (i.e., performs a data plane
operation). In the Rust-language virtiofsd, this creates a race between
two components that run *concurrently*, i.e., in different threads or
processes:
- Control plane, handling vhost-user protocol messages:
The "VhostUserSlaveReqHandlerMut::set_vring_enable" method
[crates/vhost-user-backend/src/handler.rs] handles
VHOST_USER_SET_VRING_ENABLE messages, and updates each vring's "enabled"
flag according to the message processed.
- Data plane, handling virtio / FUSE requests:
The "VringEpollHandler::handle_event" method
[crates/vhost-user-backend/src/event_loop.rs] handles the incoming
virtio / FUSE request, consuming the virtio kick at the same time. If
the vring's "enabled" flag is set, the virtio / FUSE request is
processed genuinely. If the vring's "enabled" flag is clear, then the
virtio / FUSE request is discarded.
Note that OVMF enables the queue *first*, and sends FUSE_INIT *second*.
However, if the data plane processor in virtiofsd wins the race, then it
sees the FUSE_INIT *before* the control plane processor took notice of
VHOST_USER_SET_VRING_ENABLE and green-lit the queue for the data plane
processor. Therefore the latter drops FUSE_INIT on the floor, and goes
back to waiting for further virtio / FUSE requests with epoll_wait.
Meanwhile OVMF is stuck waiting for the FUSET_INIT response -- a deadlock.
The deadlock is not deterministic. OVMF hangs infrequently during first
boot. However, OVMF hangs almost certainly during reboots from the UEFI
shell.
The race can be "reliably masked" by inserting a very small delay -- a
single debug message -- at the top of "VringEpollHandler::handle_event",
i.e., just before the data plane processor checks the "enabled" field of
the vring. That delay suffices for the control plane processor to act upon
VHOST_USER_SET_VRING_ENABLE.
We can deterministically prevent the race in QEMU, by blocking OVMF inside
step (1.2) -- i.e., in the write to the device status register that
"unleashes" queue enablement -- until VHOST_USER_SET_VRING_ENABLE actually
*completes*. That way OVMF's VCPU cannot advance to the FUSE_INIT
submission before virtiofsd's control plane processor takes notice of the
queue being enabled.
Wait for VHOST_USER_SET_VRING_ENABLE completion by:
- setting the NEED_REPLY flag on VHOST_USER_SET_VRING_ENABLE, and waiting
for the reply, if the VHOST_USER_PROTOCOL_F_REPLY_ACK vhost-user feature
has been negotiated, or
- performing a separate VHOST_USER_GET_FEATURES *exchange*, which requires
a backend response regardless of VHOST_USER_PROTOCOL_F_REPLY_ACK.
Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:vhost)
Cc: Eugenio Perez Martin <eperezma@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Liu Jiang <gerry@linux.alibaba.com>
Cc: Sergio Lopez Pascual <slp@redhat.com>
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Tested-by: Albert Esteve <aesteve@redhat.com>
[lersek@redhat.com: work Eugenio's explanation into the commit message,
about QEMU containing step (1.1) until step (1.2)]
Reviewed-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20231002203221.17241-8-lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 26f1dcaa0e9ff83187b8dba810545f8b2a940b5a
https://github.com/qemu/qemu/commit/26f1dcaa0e9ff83187b8dba810545f8b2a940b5a
Author: Ilya Maximets <i.maximets@ovn.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M include/exec/memory.h
Log Message:
-----------
memory: initialize 'fv' in MemoryRegionCache to make Coverity happy
Coverity scan reports multiple false-positive "defects" for the
following series of actions in virtio.c:
MemoryRegionCache indirect_desc_cache;
address_space_cache_init_empty(&indirect_desc_cache);
address_space_cache_destroy(&indirect_desc_cache);
For some reason it's unable to recognize the dependency between 'mrs.mr'
and 'fv' and insists that '!mrs.mr' check in address_space_cache_destroy
may take a 'false' branch, even though it is explicitly initialized to
NULL in the address_space_cache_init_empty():
*** CID 1522371: Memory - illegal accesses (UNINIT)
/qemu/hw/virtio/virtio.c: 1627 in virtqueue_split_pop()
1621 }
1622
1623 vq->inuse++;
1624
1625 trace_virtqueue_pop(vq, elem, elem->in_num, elem->out_num);
1626 done:
>>> CID 1522371: Memory - illegal accesses (UNINIT)
>>> Using uninitialized value "indirect_desc_cache.fv" when
>>> calling "address_space_cache_destroy".
1627 address_space_cache_destroy(&indirect_desc_cache);
1628
1629 return elem;
1630
1631 err_undo_map:
1632 virtqueue_undo_map_desc(out_num, in_num, iov);
** CID 1522370: Memory - illegal accesses (UNINIT)
Instead of trying to silence these false positive reports in 4
different places, initializing 'fv' as well, as this doesn't result
in any noticeable performance impact.
Signed-off-by: Ilya Maximets <i.maximets@ovn.org>
Message-Id: <20231009104322.3085887-1-i.maximets@ovn.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 984f07e6172035498cd9c9614074a3ee0e775c13
https://github.com/qemu/qemu/commit/984f07e6172035498cd9c9614074a3ee0e775c13
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: do not send RESET_OWNER on device reset
The VHOST_USER_RESET_OWNER message is deprecated in the spec:
This is no longer used. Used to be sent to request disabling all
rings, but some back-ends interpreted it to also discard connection
state (this interpretation would lead to bugs). It is recommended
that back-ends either ignore this message, or use it to disable all
rings.
The only caller of vhost_user_reset_device() is vhost_user_scsi_reset().
It checks that F_RESET_DEVICE was negotiated before calling it:
static void vhost_user_scsi_reset(VirtIODevice *vdev)
{
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(vdev);
struct vhost_dev *dev = &vsc->dev;
/*
* Historically, reset was not implemented so only reset devices
* that are expecting it.
*/
if (!virtio_has_feature(dev->protocol_features,
VHOST_USER_PROTOCOL_F_RESET_DEVICE)) {
return;
}
if (dev->vhost_ops->vhost_reset_device) {
dev->vhost_ops->vhost_reset_device(dev);
}
}
Therefore VHOST_USER_RESET_OWNER is actually never sent by
vhost_user_reset_device(). Remove the dead code. This effectively moves
the vhost-user protocol specific code from vhost-user-scsi.c into
vhost-user.c where it belongs.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-2-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Commit: 4c8cad564f032f9ecc0b726df9211df717629dab
https://github.com/qemu/qemu/commit/4c8cad564f032f9ecc0b726df9211df717629dab
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/virtio/vhost-backend.c
Log Message:
-----------
vhost-backend: remove vhost_kernel_reset_device()
vhost_kernel_reset_device() invokes RESET_OWNER, which disassociates the
owner process from the device. The device is left non-operational since
SET_OWNER is only called once during startup in vhost_dev_init().
vhost_kernel_reset_device() is never called so this latent bug never
appears. Get rid of vhost_kernel_reset_device() for now. If someone
needs it in the future they'll need to implement it correctly.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-3-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Hanna Czenczek <hreitz@redhat.com>
Commit: d96f0bf8e4edf8b4578cc1c737d354435a06080e
https://github.com/qemu/qemu/commit/d96f0bf8e4edf8b4578cc1c737d354435a06080e
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost.c
M hw/virtio/virtio.c
M include/hw/virtio/vhost.h
M meson.build
Log Message:
-----------
virtio: call ->vhost_reset_device() during reset
vhost-user-scsi has a VirtioDeviceClass->reset() function that calls
->vhost_reset_device(). The other vhost devices don't notify the vhost
device upon reset.
Stateful vhost devices may need to handle device reset in order to free
resources or prevent stale device state from interfering after reset.
Call ->vhost_device_reset() from virtio_reset() so that that vhost
devices are notified of device reset.
This patch affects behavior as follows:
- vhost-kernel: No change in behavior since ->vhost_reset_device() is
not implemented.
- vhost-user: back-ends that negotiate
VHOST_USER_PROTOCOL_F_RESET_DEVICE now receive a
VHOST_USER_DEVICE_RESET message upon device reset. Otherwise there is
no change in behavior. DPDK, SPDK, libvhost-user, and the
vhost-user-backend crate do not negotiate
VHOST_USER_PROTOCOL_F_RESET_DEVICE automatically.
- vhost-vdpa: an extra SET_STATUS 0 call is made during device reset.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20231004014532.1228637-4-stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Hanna Czenczek <hreitz@redhat.com>
Commit: 88638e868aa507c6047f8b3a51b1b73aa51ba3a1
https://github.com/qemu/qemu/commit/88638e868aa507c6047f8b3a51b1b73aa51ba3a1
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers
being identical
Commit 6103451aeb74 ("hw/i386: Build-time assertion on pc/q35 reset register
being identical.") introduced a build-time check where the addresses of the
reset registers are expected to be equal. Back then rev3 of the FADT was used
which required the reset register to be populated and there was common code.
In commit 3a3fcc75f92a ("pc: acpi: force FADT rev1 for 440fx based machine
types") the FADT was downgraded to rev1 for PIIX where the reset register isn't
available. Thus, there is no need for the assertion any longer, so remove it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231004092355.12929-1-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 83def49ca026a1707f4923266280b14c766a5bc3
https://github.com/qemu/qemu/commit/83def49ca026a1707f4923266280b14c766a5bc3
Author: Damien Zammit <damien@zamaudio.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/timer/i8254_common.c
Log Message:
-----------
timer/i8254: Fix one shot PIT mode
Currently, the one-shot (mode 1) PIT expires far too quickly,
due to the output being set under the wrong logic.
This change fixes the one-shot PIT mode to behave similarly to mode 0.
TESTED: using the one-shot PIT mode to calibrate a local apic timer.
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Message-Id: <20230226015755.52624-1-damien@zamaudio.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e09c736a1aaa3cfa56a7e3b77fa6d134eb268e33
https://github.com/qemu/qemu/commit/e09c736a1aaa3cfa56a7e3b77fa6d134eb268e33
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/display/virtio-dmabuf.c
Log Message:
-----------
hw/display: fix memleak from virtio_add_resource
When the given uuid is already present in the hash table,
virtio_add_resource() does not add the passed VirtioSharedObject. In
this case, free it in the callers to avoid leaking memory. This fixed
the following `make check` error, when built with --enable-sanitizers:
4/166 qemu:unit / test-virtio-dmabuf ERROR 1.51s exit status 1
==7716==ERROR: LeakSanitizer: detected memory leaks
Direct leak of 320 byte(s) in 20 object(s) allocated from:
#0 0x7f6fc16e3808 in __interceptor_malloc
../../../../src/libsanitizer/asan/asan_malloc_linux.cc:144
#1 0x7f6fc1503e98 in g_malloc
(/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57e98)
#2 0x564d63cafb6b in test_add_invalid_resource
../tests/unit/test-virtio-dmabuf.c:100
#3 0x7f6fc152659d (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x7a59d)
SUMMARY: AddressSanitizer: 320 byte(s) leaked in 20 allocation(s).
The changes at virtio_add_resource() itself are not strictly necessary
for the memleak fix, but they make it more obvious that, on an error
return, the passed object is not added to the hash.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Message-Id:
<c61c13f9a0c67dec473bdbfc8789c29ef26c900b.1696624734.git.quic_mathbern@quicinc.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Albert Esteve <aesteve@redhat.com>
Signed-off-by: Matheus Tavares Bernardino <<a
href="mailto:quic_mathbern@quicinc.com";
target="_blank">quic_mathbern@quicinc.com</a>><br>
Commit: 237b90d33a12914d4174d34269edf26c765b3b87
https://github.com/qemu/qemu/commit/237b90d33a12914d4174d34269edf26c765b3b87
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
hw/i386/pc: Merge two if statements into one
By being the only entity assigning a non-NULL value to "rtc_irq", the first if
statement determines whether the second if statement is executed. So merge the
two statements into one.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-2-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cd232c0a6ce02a5c9de103c2426a13005b9329a2
https://github.com/qemu/qemu/commit/cd232c0a6ce02a5c9de103c2426a13005b9329a2
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south
bridge
The next patches will need to take advantage of it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-3-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c89f01c55615ad112a2120c79d2b345cec434ba0
https://github.com/qemu/qemu/commit/c89f01c55615ad112a2120c79d2b345cec434ba0
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize()
Unlike its PIIX4 counterpart, TYPE_PIIX3_DEVICE doesn't instantiate a PIC
itself. Instead, it relies on the board to do so. This means that the board
needs to wire the ISA IRQs to the PIIX3 device model. As long as the board
assigns the ISA IRQs after PIIX3's realize(), internal devices can't be wired in
pci_piix3_realize() since the qemu_irqs are still NULL. Fix that by assigning
the ISA interrupts before realize(). This will allow for embedding child devices
into the host device as already done for PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-4-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 79583234651968bf9f73437eb2de14a485bd398a
https://github.com/qemu/qemu/commit/79583234651968bf9f73437eb2de14a485bd398a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-5-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c794a1fd25b256f3d56a382b395dcd87981ff0a4
https://github.com/qemu/qemu/commit/c794a1fd25b256f3d56a382b395dcd87981ff0a4
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property
Avoid assigning the private member of struct PIIX3State from outside which goes
against best QOM practices. Instead, implement best QOM practice by adding an
"isa-irqs" array property to TYPE_PIIX3_DEVICE and assign it in board code, i.e.
from outside.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-6-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 16880173d8a76d4423d377dd966a12d1f312d894
https://github.com/qemu/qemu/commit/16880173d8a76d4423d377dd966a12d1f312d894
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix: Remove redundant "piix3" variable
The variable is never used by its declared type. Eliminate it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-7-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 23926d6e3aeae32c0de63353af8b18e379b9e60c
https://github.com/qemu/qemu/commit/23926d6e3aeae32c0de63353af8b18e379b9e60c
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in"
TYPE_PIIX3_DEVICE doesn't instantiate a PIC since it relies on the board to do
so. The "pic" attribute, however, suggests that there is one. Rename the
attribute to reflect that it represents ISA interrupt lines. Use the same naming
convention as in the VIA south bridges as well as in TYPE_I82378.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-8-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1594e3eee0f85bdc017a7ebf089167296ef394a7
https://github.com/qemu/qemu/commit/1594e3eee0f85bdc017a7ebf089167296ef394a7
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_q35.c
M hw/isa/lpc_ich9.c
Log Message:
-----------
hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize()
When the board assigns the ISA IRQs after the device's realize(), internal
devices such as the RTC can't be wired in ich9_lpc_realize() since the qemu_irqs
are still NULL. Fix that by assigning the ISA interrupts before realize().
This change is necessary for PIIX consolidation because PIIX4 wires the RTC
interrupts in its realize() method, so PIIX3 needs to do so as well. Since the
PC and Q35 boards share RTC code, and since PIIX3 needs the change, ICH9 needs
to be adapted as well.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-9-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3cccc57a6adad904fe5e94e05326160965cfc4a6
https://github.com/qemu/qemu/commit/3cccc57a6adad904fe5e94e05326160965cfc4a6
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Wire PIC IRQs to ISA bus in host device
Thie PIIX3 south bridge implements both the PIC and the ISA bus, so wiring the
interrupts there makes the device model more self-contained. Furthermore, this
allows the ISA interrupts to be wired to internal child devices in
pci_piix3_realize() which will be performed in subsequent patches.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-10-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 899e94ffd8ecd3b399d466a31928f2eae790829b
https://github.com/qemu/qemu/commit/899e94ffd8ecd3b399d466a31928f2eae790829b
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc.c
M hw/isa/lpc_ich9.c
M hw/isa/piix3.c
Log Message:
-----------
hw/i386/pc: Wire RTC ISA IRQs in south bridges
Makes the south bridges a bit more self-contained and aligns PIIX3 more with
PIIX4. The latter is needed for consolidating the PIIX south bridges.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-11-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b9d03842452761ca6fec60352f7dc05287bc7c9a
https://github.com/qemu/qemu/commit/b9d03842452761ca6fec60352f7dc05287bc7c9a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/Kconfig
M hw/i386/pc_piix.c
M hw/isa/Kconfig
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Create IDE controller in host device
The IDE controller is an integral part of PIIX3 (function 1). So create it as
part of the south bridge.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-12-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3dc892613e32f09b6830fcbe3a3247e9cec88aaf
https://github.com/qemu/qemu/commit/3dc892613e32f09b6830fcbe3a3247e9cec88aaf
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/Kconfig
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Create USB controller in host device
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-13-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: be5b66b7c9448c6fb5350cdcb4097376a9ecff1f
https://github.com/qemu/qemu/commit/be5b66b7c9448c6fb5350cdcb4097376a9ecff1f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/Kconfig
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Create power management controller in host device
The power management controller is an integral part of PIIX3 (function 3). So
create it as part of the south bridge.
Note that the ACPI function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-14-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fa87c5f17c5c66309f21e42a5504a33daaf4b7bb
https://github.com/qemu/qemu/commit/fa87c5f17c5c66309f21e42a5504a33daaf4b7bb
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix3.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix3: Drop the "3" from PIIX base class name
TYPE_PIIX3_PCI_DEVICE was the former base class of the Xen and non-Xen variants
of the PIIX3 ISA device models. It will become the base class for the PIIX3 and
PIIX4 device models, so drop the "3" from the type names.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-15-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 18b1a595bd0d763856c58a308aaa25bf6e1c2a80
https://github.com/qemu/qemu/commit/18b1a595bd0d763856c58a308aaa25bf6e1c2a80
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Remove unused inbound ISA interrupt lines
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines. PIIX3 doesn't expose such interrupt lines
either, so remove them for PIIX4 for simplicity and consistency.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-16-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9f6357a5404fada0723c324f237293f9395e0020
https://github.com/qemu/qemu/commit/9f6357a5404fada0723c324f237293f9395e0020
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in"
Rename the "isa" attribute to align it with PIIX3 for consolidation.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-17-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ec32e56ddf74c6ae87b5cce8f7d7ab8498437c66
https://github.com/qemu/qemu/commit/ec32e56ddf74c6ae87b5cce8f7d7ab8498437c66
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Rename reset control operations to match PIIX3
Both implementations are the same and will be shared upon merging.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-18-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 14d6b2f62da4f8e586e80e6aff7c7c1dd0d38faf
https://github.com/qemu/qemu/commit/14d6b2f62da4f8e586e80e6aff7c7c1dd0d38faf
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix4.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix4: Reuse struct PIIXState from PIIX3
PIIX4 has its own, private PIIX4State structure. PIIX3 has almost the
same structure, provided in a public header. So reuse it and add a
cpu_intr attribute to it which is only used by PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-19-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 65d635838d43007c6b4996dbf5c6d61715b60d73
https://github.com/qemu/qemu/commit/65d635838d43007c6b4996dbf5c6d61715b60d73
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/i386/Kconfig
M hw/isa/Kconfig
M hw/isa/meson.build
A hw/isa/piix.c
R hw/isa/piix3.c
R hw/isa/piix4.c
M hw/mips/Kconfig
Log Message:
-----------
hw/isa/piix3: Merge hw/isa/piix4.c
Now that the PIIX3 and PIIX4 device models are sufficiently prepared, their
implementations can be merged into one file for further consolidation.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-20-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 051f087d67fb7cede89f091501187f773a99cd99
https://github.com/qemu/qemu/commit/051f087d67fb7cede89f091501187f773a99cd99
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix: Allow for optional PIC creation in PIIX3
In the PC machine, the PIC is created in board code to allow it to be
virtualized with various virtualization techniques. So explicitly disable its
creation in the PC machine via a property which defaults to enabled. Once the
PIIX implementations are consolidated this default will keep Malta working
without further ado.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-21-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9a43333153a589e122b185aee78971024d437ea0
https://github.com/qemu/qemu/commit/9a43333153a589e122b185aee78971024d437ea0
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix.c
M include/hw/southbridge/piix.h
Log Message:
-----------
hw/isa/piix: Allow for optional PIT creation in PIIX3
In the PC machine, the PIT is created in board code to allow it to be
virtualized with various virtualization techniques. So explicitly disable its
creation in the PC machine via a property which defaults to enabled. Once the
PIIX implementations are consolidated this default will keep Malta working
without further ado.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-22-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d45007395f005ca449e8b5e9d911d9f750a5c123
https://github.com/qemu/qemu/commit/d45007395f005ca449e8b5e9d911d9f750a5c123
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Harmonize names of reset control memory regions
There is no need for having different names here. Having the same name
further allows code to be shared between PIIX3 and PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-23-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1c976935844adb2b940ec5973a5e2d5ee0465845
https://github.com/qemu/qemu/commit/1c976935844adb2b940ec5973a5e2d5ee0465845
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Share PIIX3's base class with PIIX4
Having a common base class will allow for futher code sharing between PIIX3 and
PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-24-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f5d2d39a8c9d3294d71cb2ba12c5d796afe48723
https://github.com/qemu/qemu/commit/f5d2d39a8c9d3294d71cb2ba12c5d796afe48723
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix.c
M hw/mips/malta.c
Log Message:
-----------
hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
Resolves duplicate code. Also makes PIIX4 respect the PIIX3 properties which get
added, too. This allows for using PIIX4 in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-25-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 698f428a3c024c4e2352d0efb2e96e3129b817c7
https://github.com/qemu/qemu/commit/698f428a3c024c4e2352d0efb2e96e3129b817c7
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
PIIX4 will get the same optimizations which are already implemented for
PIIX3.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-26-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e81b6c46133d12aa94d06464affc40e64faa5d0d
https://github.com/qemu/qemu/commit/e81b6c46133d12aa94d06464affc40e64faa5d0d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen
which relies on pci_bus_fire_intx_routing_notifier() to be fired.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-27-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2731d8bd2b8b9ed842fe2c7928b702f97b5852a3
https://github.com/qemu/qemu/commit/2731d8bd2b8b9ed842fe2c7928b702f97b5852a3
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
Now that both PIIX3 and PIIX4 use piix_set_irq() to trigger PCI IRQs the wiring
in the respective realize methods can be shared, too.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-28-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 461585efb5d8ee352209cf5e37116046f1410b94
https://github.com/qemu/qemu/commit/461585efb5d8ee352209cf5e37116046f1410b94
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/isa/piix.c
Log Message:
-----------
hw/isa/piix: Implement multi-process QEMU support also for PIIX4
So far multi-process QEMU was only implemented for PIIX3. Move the support into
the base class to achieve feature parity between both device models.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-29-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8b152920ea5955b1cba164a0f18c544a69ced13b
https://github.com/qemu/qemu/commit/8b152920ea5955b1cba164a0f18c544a69ced13b
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M docs/system/target-i386-desc.rst.inc
M hw/i386/pc.c
M hw/i386/pc_piix.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
QEMU's PIIX3 implementation actually models the real PIIX4, but with different
PCI IDs. Usually, guests deal just fine with it. Still, in order to provide a
more consistent illusion to guests, allow QEMU's PIIX4 implementation to be used
in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-30-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 772346132e16f493c1cd354a0b9bd8561a1372b7
https://github.com/qemu/qemu/commit/772346132e16f493c1cd354a0b9bd8561a1372b7
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/scsi/vhost-scsi-common.c
Log Message:
-----------
vhost-user-common: send get_inflight_fd once
Currently the get_inflight_fd will be sent every time the device is started, and
the backend will allocate shared memory to save the inflight state. If the
backend finds that it receives the second get_inflight_fd, it will release the
previous shared memory, which breaks inflight working logic.
This patch is a preparation for the following patches.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-2-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: defb50258fc7bc7386c4666f69e9d73590580b6c
https://github.com/qemu/qemu/commit/defb50258fc7bc7386c4666f69e9d73590580b6c
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/virtio/vhost-user-gpio.c
M include/hw/virtio/vhost.h
Log Message:
-----------
vhost: move and rename the conn retry times
Multiple devices need this macro, move it to a common header.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-3-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1e78b466dd62c08d8b027119eff37d7d09cd9aa0
https://github.com/qemu/qemu/commit/1e78b466dd62c08d8b027119eff37d7d09cd9aa0
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/scsi/vhost-scsi-common.c
M hw/scsi/vhost-scsi.c
M hw/scsi/vhost-user-scsi.c
M include/hw/virtio/vhost-scsi-common.h
M include/hw/virtio/vhost-user-scsi.h
Log Message:
-----------
vhost-user-scsi: support reconnect to backend
If the backend crashes and restarts, the device is broken.
This patch adds reconnect for vhost-user-scsi.
This patch also improves the error messages, and reports some silent errors.
Tested with spdk backend.
Signed-off-by: Li Feng <fengli@smartx.com>
Message-Id: <20231009044735.941655-4-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Commit: 02c4863bd64f206011faecf3c0c934d9e1052b25
https://github.com/qemu/qemu/commit/02c4863bd64f206011faecf3c0c934d9e1052b25
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/scsi/vhost-user-scsi.c
Log Message:
-----------
vhost-user-scsi: start vhost when guest kicks
Let's keep the same behavior as vhost-user-blk.
Some old guests kick virtqueue before setting VIRTIO_CONFIG_S_DRIVER_OK.
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-5-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a68c0148e9bf105f9e83ff5e763b8fcb6f7ba9be
https://github.com/qemu/qemu/commit/a68c0148e9bf105f9e83ff5e763b8fcb6f7ba9be
Author: Li Feng <fengli@smartx.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost-user-gpio.c
M hw/virtio/vhost-user.c
M include/hw/virtio/vhost-user.h
Log Message:
-----------
vhost-user: fix lost reconnect
When the vhost-user is reconnecting to the backend, and if the vhost-user fails
at the get_features in vhost_dev_init(), then the reconnect will fail
and it will not be retriggered forever.
The reason is:
When the vhost-user fails at get_features, the vhost_dev_cleanup will be called
immediately.
vhost_dev_cleanup calls 'memset(hdev, 0, sizeof(struct vhost_dev))'.
The reconnect path is:
vhost_user_blk_event
vhost_user_async_close(.. vhost_user_blk_disconnect ..)
qemu_chr_fe_set_handlers <----- clear the notifier callback
schedule vhost_user_async_close_bh
The vhost->vdev is null, so the vhost_user_blk_disconnect will not be
called, then the event fd callback will not be reinstalled.
All vhost-user devices have this issue, including vhost-user-blk/scsi.
With this patch, if the vdev->vdev is null, the fd callback will still
be reinstalled.
Fixes: 71e076a07d ("hw/virtio: generalise CHR_EVENT_CLOSED handling")
Signed-off-by: Li Feng <fengli@smartx.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20231009044735.941655-6-fengli@smartx.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5c725185bd332203c070440b230450cbefa80c69
https://github.com/qemu/qemu/commit/5c725185bd332203c070440b230450cbefa80c69
Author: Ani Sinha <anisinha@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range
pc_get_device_memory_range() finds the device memory size by calculating the
difference between maxram and ram sizes. This calculation makes sense only when
maxram is greater than the ram size. Make sure we check for that before calling
pc_get_device_memory_range().
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231011105335.42296-1-anisinha@redhat.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c8c56b6a8baa3ccce56e7a0f76c365598f1f3b67
https://github.com/qemu/qemu/commit/c8c56b6a8baa3ccce56e7a0f76c365598f1f3b67
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Allow update of DSDT.cxl
Addition of QTG in following patch requires an update to the test
data.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20231012125623.21101-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eec8443204bab378ab835289d9fd5f604c606e09
https://github.com/qemu/qemu/commit/eec8443204bab378ab835289d9fd5f604c606e09
Author: Dave Jiang <dave.jiang@intel.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/acpi/cxl.c
M hw/i386/acpi-build.c
M include/hw/acpi/cxl.h
Log Message:
-----------
hw/cxl: Add QTG _DSM support for ACPI0017 device
Add a simple _DSM call support for the ACPI0017 device to return fake QTG
ID values of 0 and 1 in all cases. This for _DSM plumbing testing from the OS.
Following edited for readability
Device (CXLM)
{
Name (_HID, "ACPI0017") // _HID: Hardware ID
...
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("f365f9a6-a7de-4071-a66a-b40c0b4f8e52")))
{
If ((Arg2 == Zero))
{
Return (Buffer (One) { 0x01 })
}
If ((Arg2 == One))
{
Return (Package (0x02)
{
One,
Package (0x02)
{
Zero,
One
}
})
}
}
}
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231012125623.21101-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7c6f17793f3f3338d8a4018588c3fc3a1527c064
https://github.com/qemu/qemu/commit/7c6f17793f3f3338d8a4018588c3fc3a1527c064
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Update DSDT.cxl with QTG DSM
Description of change in previous patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20231012125623.21101-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7a71e4031156d9b0c3cdf34d4b48d5724da1eeec
https://github.com/qemu/qemu/commit/7a71e4031156d9b0c3cdf34d4b48d5724da1eeec
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M docs/interop/vhost-user.rst
M include/hw/virtio/vhost-user.h
M subprojects/libvhost-user/libvhost-user.h
Log Message:
-----------
vhost-user: Fix protocol feature bit conflict
The VHOST_USER_PROTOCOL_F_XEN_MMAP feature bit was defined in
f21e95ee97d, which has been part of qemu's 8.1.0 release. However, it
seems it was never added to qemu's code, but it is well possible that it
is already used by different front-ends outside of qemu (i.e., Xen).
VHOST_USER_PROTOCOL_F_SHARED_OBJECT in contrast was added to qemu's code
in 16094766627, but never defined in the vhost-user specification. As a
consequence, both bits were defined to be 17, which cannot work.
Regardless of whether actual code or the specification should take
precedence, F_XEN_MMAP is already part of a qemu release, while
F_SHARED_OBJECT is not. Therefore, bump the latter to take number 18
instead of 17, and add this to the specification.
Take the opportunity to add at least a little note on the
VhostUserShared structure to the specification. This structure is
referenced by the new commands introduced in 16094766627, but was not
defined.
Fixes: 160947666276c5b7f6bca4d746bcac2966635d79
("vhost-user: add shared_object msg")
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016083201.23736-1-hreitz@redhat.com>
Reviewed-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7e3fb8ca55db27393c83d4b683c84fca2621698d
https://github.com/qemu/qemu/commit/7e3fb8ca55db27393c83d4b683c84fca2621698d
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section
i8259.c is already listed here, so the corresponding header should
be mentioned in this section, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231017152625.229022-1-thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 49ca8f122f3e84d7d879f3b4d54a5294b39764d1
https://github.com/qemu/qemu/commit/49ca8f122f3e84d7d879f3b4d54a5294b39764d1
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel-iommu: Report interrupt remapping faults, fix return value
A generic X86IOMMUClass->int_remap function should not return VT-d
specific values; fix it to return 0 if the interrupt was successfully
translated or -EINVAL if not.
The VTD_FR_IR_xxx values are supposed to be used to actually raise
faults through the fault reporting mechanism, so do that instead for
the case where the IRQ is actually being injected.
There is more work to be done here, as pretranslations for the KVM IRQ
routing table can't fault; an untranslatable IRQ should be handled in
userspace and the fault raised only when the IRQ actually happens (if
indeed the IRTE is still not valid at that time). But we can work on
that later; we can at least raise faults for the direct case.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <31bbfc9041690449d3ac891f4431ec82174ee1b4.camel@infradead.org>
Acked-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 87eabd90e599c3e866ee052c14655a286966951a
https://github.com/qemu/qemu/commit/87eabd90e599c3e866ee052c14655a286966951a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Untabify tcg-target.c.inc
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1617f2dbc9952c2b44972b6778f27da100475339
https://github.com/qemu/qemu/commit/1617f2dbc9952c2b44972b6778f27da100475339
Author: Jordan Niethe <jniethe5@gmail.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB
Direct branch patching was disabled when using TCG_REG_TB in commit
736a1588c1 ("tcg/ppc: Fix race in goto_tb implementation").
The issue with direct branch patching with TCG_REG_TB is the lack of
synchronization between the new TCG_REG_TB being established and the
direct branch being patched in.
If each translation block is responsible for establishing its own
TCG_REG_TB then there can be no synchronization issue.
Make each translation block begin by setting up its own TCG_REG_TB.
Use the preferred 'bcl 20,31,$+4' sequence.
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
[rth: Split out tcg_out_tb_start, power9 addpcis]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2d2b1dc5da7a5debd47e90d3c74ea6830a93db26
https://github.com/qemu/qemu/commit/2d2b1dc5da7a5debd47e90d3c74ea6830a93db26
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Reinterpret tb-relative to TB+4
It saves one insn to load the address of TB+4 instead of TB.
Adjust all of the indexing to match.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e4948f1114f46d1596c2fbdafbbf4674386b7841
https://github.com/qemu/qemu/commit/e4948f1114f46d1596c2fbdafbbf4674386b7841
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use ADDPCIS in tcg_out_tb_start
With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIA.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4debaea68142c69d89497071d731e9052b09d62e
https://github.com/qemu/qemu/commit/4debaea68142c69d89497071d731e9052b09d62e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use ADDPCIS in tcg_out_movi_int
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 25ca1f3045f43cc0e43bc924faf3d69693e4c8a2
https://github.com/qemu/qemu/commit/25ca1f3045f43cc0e43bc924faf3d69693e4c8a2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use ADDPCIS for the constant pool
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fab2b7ea584f6a64a718f2c0bba24b7bbe389ec4
https://github.com/qemu/qemu/commit/fab2b7ea584f6a64a718f2c0bba24b7bbe389ec4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use ADDPCIS in tcg_out_goto_tb
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d877751e176115a14d86bb20b6d63ef051c1f89d
https://github.com/qemu/qemu/commit/d877751e176115a14d86bb20b6d63ef051c1f89d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use PADDI in tcg_out_movi
PADDI can load 34-bit immediates and 34-bit pc-relative addresses.
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 94fa412521c3cbac2d19d44870b3b29841a5444a
https://github.com/qemu/qemu/commit/94fa412521c3cbac2d19d44870b3b29841a5444a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use prefixed instructions in tcg_out_mem_long
When the offset is out of range of the non-prefixed insn, but
fits the 34-bit immediate of the prefixed insn, use that.
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f680f6468e2208ac8f3a34abf17745f084e04586
https://github.com/qemu/qemu/commit/f680f6468e2208ac8f3a34abf17745f084e04586
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use PLD in tcg_out_movi for constant pool
The prefixed instruction has a pc-relative form to use here.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: adf89b53031e81a1f94c0af762210853147b1497
https://github.com/qemu/qemu/commit/adf89b53031e81a1f94c0af762210853147b1497
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec
The prefixed instructions have a pc-relative form to use here.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: efa2a33b9f701b6dcddec5b628b859d8f8f4cbb8
https://github.com/qemu/qemu/commit/efa2a33b9f701b6dcddec5b628b859d8f8f4cbb8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use PLD in tcg_out_goto_tb
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: af1cedcb63207b58341adc69804b4856b96499c2
https://github.com/qemu/qemu/commit/af1cedcb63207b58341adc69804b4856b96499c2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Disable TCG_REG_TB for Power9/Power10
This appears to slightly improve performance on power9/10.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c02004acf6b2eebef04273d46728535e57545e88
https://github.com/qemu/qemu/commit/c02004acf6b2eebef04273d46728535e57545e88
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
tcg: Introduce tcg_use_softmmu
Begin disconnecting CONFIG_SOFTMMU from !CONFIG_USER_ONLY.
Introduce a variable which can be set at startup to select
one method or another for user-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cedcdad6344084efb753ff7eb29f6596dd443615
https://github.com/qemu/qemu/commit/cedcdad6344084efb753ff7eb29f6596dd443615
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Provide guest_base fallback for system mode
Provide a define to allow !tcg_use_softmmu code paths to
compile in system mode, but require elimination.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 77c83d74c1fb7b084141c3e6fcf7807a8160c9ff
https://github.com/qemu/qemu/commit/77c83d74c1fb7b084141c3e6fcf7807a8160c9ff
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 01b5b5207ad37faa3a8d995d9886dd34418bf28a
https://github.com/qemu/qemu/commit/01b5b5207ad37faa3a8d995d9886dd34418bf28a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d809d39e87728fac5580fa20a54e186231d21b22
https://github.com/qemu/qemu/commit/d809d39e87728fac5580fa20a54e186231d21b22
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8954eef92fc50b4a1a09702a925d5f3f2bf23dfa
https://github.com/qemu/qemu/commit/8954eef92fc50b4a1a09702a925d5f3f2bf23dfa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e8ac8a7366d9b35117d9596f399292b18e9e4745
https://github.com/qemu/qemu/commit/e8ac8a7366d9b35117d9596f399292b18e9e4745
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0396dd72510bfa124762d256a1915aa0ef11b3d9
https://github.com/qemu/qemu/commit/0396dd72510bfa124762d256a1915aa0ef11b3d9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Use tcg_use_softmmu
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 451ae08f3f0f3830f1f61bb271a68ab2ebd10d83
https://github.com/qemu/qemu/commit/451ae08f3f0f3830f1f61bb271a68ab2ebd10d83
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero
Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the
JIT")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: eb63c85e27c8e3df8fa0bddc76eaf7103910f005
https://github.com/qemu/qemu/commit/eb63c85e27c8e3df8fa0bddc76eaf7103910f005
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Use tcg_use_softmmu
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d57279fdba97076662786cb55f52d3e11a6eef81
https://github.com/qemu/qemu/commit/d57279fdba97076662786cb55f52d3e11a6eef81
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4d3978277f481781b29d972ee49aa19f2f39080c
https://github.com/qemu/qemu/commit/4d3978277f481781b29d972ee49aa19f2f39080c
Author: Mike Frysinger <vapier@gentoo.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M include/tcg/tcg-op.h
Log Message:
-----------
tcg: drop unused tcg_temp_free define
Use of the API was removed a while back, but the define wasn't.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231015010046.16020-1-vapier@gentoo.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: addb53142599525af112911c55181cefe0bfdd20
https://github.com/qemu/qemu/commit/addb53142599525af112911c55181cefe0bfdd20
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Use constant zero when expanding with divu2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 58c28f5f4f0f5f97072cee4f55bd0715d699d8c7
https://github.com/qemu/qemu/commit/58c28f5f4f0f5f97072cee4f55bd0715d699d8c7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg: Optimize past conditional branches
We already register allocate through extended basic blocks,
optimize through extended basic blocks as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cd7204c59058e5d0e91aa0309806818366b156b2
https://github.com/qemu/qemu/commit/cd7204c59058e5d0e91aa0309806818366b156b2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Add tcg_gen_{ld,st}_i128
Do not require the translators to jump through concat and
extract of i64 in order to move values to and from env.
Tested-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b540757b7f711eaf069f530916005cf8cfe7c00f
https://github.com/qemu/qemu/commit/b540757b7f711eaf069f530916005cf8cfe7c00f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Use i128 for 128 and 256-bit loads and stores
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e6e66b03287331abc6f184456dbc6d25505590ec
https://github.com/qemu/qemu/commit/e6e66b03287331abc6f184456dbc6d25505590ec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user: Fixes for zero_bss
The previous change, 2d385be6152, assumed !PAGE_VALID meant that
the page would be unmapped by the elf image. However, since we
reserved the entire image space via mmap, PAGE_VALID will always
be set. Instead, assume PROT_NONE for the same condition.
Furthermore, assume bss is only ever present for writable segments,
and that there is no page overlap between PT_LOAD segments.
Instead of an assert, return false to indicate failure.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1854
Fixes: 2d385be6152 ("linux-user: Do not adjust zero_bss for host page size")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6fad9b4bb91dcc824f9c00a36ee843883b58313b
https://github.com/qemu/qemu/commit/6fad9b4bb91dcc824f9c00a36ee843883b58313b
Author: Mikulas Patocka <mpatocka@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/mips/cpu_loop.c
Log Message:
-----------
linux-user/mips: fix abort on integer overflow
QEMU mips userspace emulation crashes with "qemu: unhandled CPU exception
0x15 - aborting" when one of the integer arithmetic instructions detects
an overflow.
This patch fixes it so that it delivers SIGFPE with FPE_INTOVF instead.
Cc: qemu-stable@nongnu.org
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Message-Id: <3ef979a8-3ee1-eb2d-71f7-d788ff88dd11@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3b894b699c9a9c064466e128c18be80a3f2113bc
https://github.com/qemu/qemu/commit/3b894b699c9a9c064466e128c18be80a3f2113bc
Author: Mikulas Patocka <mpatocka@redhat.com>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/sh4/signal.c
Log Message:
-----------
linux-user/sh4: Fix crashes on signal delivery
sh4 uses gUSA (general UserSpace Atomicity) to provide atomicity on CPUs
that don't have atomic instructions. A gUSA region that adds 1 to an
atomic variable stored in @R2 looks like this:
4004b6: 03 c7 mova 4004c4 <gusa+0x10>,r0
4004b8: f3 61 mov r15,r1
4004ba: 09 00 nop
4004bc: fa ef mov #-6,r15
4004be: 22 63 mov.l @r2,r3
4004c0: 01 73 add #1,r3
4004c2: 32 22 mov.l r3,@r2
4004c4: 13 6f mov r1,r15
R0 contains a pointer to the end of the gUSA region
R1 contains the saved stack pointer
R15 contains negative length of the gUSA region
When this region is interrupted by a signal, the kernel detects if
R15 >= -128U. If yes, the kernel rolls back PC to the beginning of the
region and restores SP by copying R1 to R15.
The problem happens if we are interrupted by a signal at address 4004c4.
R15 still holds the value -6, but the atomic value was already written by
an instruction at address 4004c2. In this situation we can't undo the
gUSA. The function unwind_gusa does nothing, the signal handler attempts
to push a signal frame to the address -6 and crashes.
This patch fixes it, so that if we are interrupted at the last instruction
in a gUSA region, we copy R1 to R15 to restore the correct stack pointer
and avoid crashing.
There's another bug: if we are interrupted in a delay slot, we save the
address of the instruction in the delay slot. We must save the address of
the previous instruction.
Cc: qemu-stable@nongnu.org
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourcefoege.jp>
Message-Id: <b16389f7-6c62-70b7-59b3-87533c0bcc@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a9f6004f677923f620e0927a626d1bdaa1eb2166
https://github.com/qemu/qemu/commit/a9f6004f677923f620e0927a626d1bdaa1eb2166
Author: Jiajie Chen <c@jia.je>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/elfload: Enable LSX/LASX in HWCAP for LoongArch
Since support for LSX and LASX is landed in QEMU recently, we can update
HWCAPS accordingly.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231001085315.1692667-1-c@jia.je>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 912ff698cae8879d981157fd8cca1354248fddcc
https://github.com/qemu/qemu/commit/912ff698cae8879d981157fd8cca1354248fddcc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/mmap.c
Log Message:
-----------
linux-user: Propagate failure in mmap_reserve_or_unmap back to target_munmap
Do not assert success, but return any failure received.
Additionally, fix the method of earlier error return in target_munmap.
Reported-by: Andreas Schwab <schwab@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b8b50f1e9ac8007831c2df1bd0d728f420d5818c
https://github.com/qemu/qemu/commit/b8b50f1e9ac8007831c2df1bd0d728f420d5818c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Split out die_with_signal
Because we trap so many signals for use by the guest,
we have to take extra steps to exit properly.
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ee72c47eebe119575b2bb684912bbb8c9efc9ba7
https://github.com/qemu/qemu/commit/ee72c47eebe119575b2bb684912bbb8c9efc9ba7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Exit not abort in die_with_backtrace
This line is supposed to be unreachable, but if we're going to
have it at all, SIGABRT via abort() is subject to the same signal
peril that created this function in the first place.
We can _exit immediately without peril.
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7dfd3ca8d95f9962cdd2ebdfcdd699279b98fa18
https://github.com/qemu/qemu/commit/7dfd3ca8d95f9962cdd2ebdfcdd699279b98fa18
Author: Helge Deller <deller@gmx.de>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Detect and report host crashes
If there is an internal program error in the qemu source code which
raises SIGSEGV or SIGBUS, we currently assume the signal belongs to
the guest. With an artificial error introduced, we will now print
QEMU internal SIGSEGV {code=MAPERR, addr=(nil)}
Signed-off-by: Helge Deller <deller@gmx.de>
Message-Id: <20230812164314.352131-1-deller@gmx.de>
[rth: Use in_code_gen_buffer and die_with_signal; drop backtrace]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: dbde2c0c0eec5f9d6228fd418a127def561ea516
https://github.com/qemu/qemu/commit/dbde2c0c0eec5f9d6228fd418a127def561ea516
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Only register handlers for core_dump_signal by default
The set of fatal signals is really immaterial. If one arrives,
and is unhandled, then the qemu process dies and the parent gets
the correct signal.
It is only for those signals which we would like to perform a
guest core dump instead of a host core dump that we need to catch.
Acked-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b60b91aa8f3f053064ab3c6be4b2e388a82ff6b4
https://github.com/qemu/qemu/commit/b60b91aa8f3f053064ab3c6be4b2e388a82ff6b4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Map unsupported signals to an out-of-bounds value
Do not return a valid signal number in one domain
when given an invalid signal number in the other domain.
Acked-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 58c4e36c4e7350d2e7c8ba2d72b74a347d687b68
https://github.com/qemu/qemu/commit/58c4e36c4e7350d2e7c8ba2d72b74a347d687b68
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Simplify signal_init
Install the host signal handler at the same time we are
probing the target signals for SIG_IGN/SIG_DFL. Ignore
unmapped target signals.
Acked-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f4e1168198a6306c3e337f2b91b1213f5bef52af
https://github.com/qemu/qemu/commit/f4e1168198a6306c3e337f2b91b1213f5bef52af
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Split out host_sig{segv,bus}_handler
Make host_signal_handler slightly easier to read.
Acked-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4a6ebc19a7e2d013a0e2ca79452ea733b1d5b686
https://github.com/qemu/qemu/commit/4a6ebc19a7e2d013a0e2ca79452ea733b1d5b686
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Detect and report host SIGILL, SIGFPE, SIGTRAP
These signals, when not spoofed via kill(), are always bugs.
Use die_from_signal to report this sensibly.
Acked-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 38ee0a7dfb4b15407678df26448e4a18fd9a51d4
https://github.com/qemu/qemu/commit/38ee0a7dfb4b15407678df26448e4a18fd9a51d4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-10-18 (Wed, 18 Oct 2023)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Remap guest SIGABRT
Distinguish host SIGABRT from guest SIGABRT by mapping
the guest signal onto one of the host RT signals.
This prevents a cycle by which a host assertion failure
is caught and handled by host_signal_handler, queued for
the guest, and then we attempt to continue past the
host abort. What happens next depends on the host libc,
but is neither good nor helpful.
Acked-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a8be26cd8e6ba4b433acbcd9b6807ccd436c0f0d
https://github.com/qemu/qemu/commit/a8be26cd8e6ba4b433acbcd9b6807ccd436c0f0d
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M migration/migration-hmp-cmds.c
M migration/migration.c
M migration/ram-compress.c
M migration/ram-compress.h
M migration/ram.c
Log Message:
-----------
Merge tag 'migration-20231018-pull-request' of
https://gitlab.com/juan.quintela/qemu into staging
Migration Pull request (20231018)
In this pull request:
- RDMA cleanups
- compression cleanups
CI: https://gitlab.com/juan.quintela/qemu/-/pipelines/1040780020
Please apply.
PD. I tried to get the deprecated bits integrated, but I broke
qemu-iotests duer to blk warning. Will resend it.
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* tag 'migration-20231018-pull-request' of
https://gitlab.com/juan.quintela/qemu:
migration: save_zero_page() can take block through pss
migration: control_save_page() can take block through pss
migration: save_compress_page() can take block through pss
migration: Print block status when needed
migration: Use "i" as an for index in ram-compress.c
migration: Simplify decompress_data_with_multi_threads()
migration: Move update_compress_threads_counts() to ram-compress.c
migration: Create ram_compressed_pages()
migration: Create populate_compress()
migration: Move compression_counters cleanup ram-compress.c
migration: RDMA is not compatible with anything else
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 9b9ffc665c05a99088e9e78c77466625d0827472
https://github.com/qemu/qemu/commit/9b9ffc665c05a99088e9e78c77466625d0827472
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
M docs/devel/index-internals.rst
A docs/devel/s390-cpu-topology.rst
A docs/system/s390x/cpu-topology.rst
M docs/system/target-s390x.rst
M hw/core/machine-hmp-cmds.c
M hw/core/machine-smp.c
M hw/core/machine.c
M hw/core/qdev-properties-system.c
A hw/s390x/cpu-topology.c
M hw/s390x/meson.build
M hw/s390x/s390-virtio-ccw.c
M hw/s390x/sclp.c
M hw/s390x/sclpquiesce.c
M include/hw/boards.h
M include/hw/qdev-properties-system.h
A include/hw/s390x/cpu-topology.h
M include/hw/s390x/s390-virtio-ccw.h
M include/hw/s390x/sclp.h
A qapi/machine-common.json
M qapi/machine-target.json
M qapi/machine.json
M qapi/meson.build
M qapi/qapi-schema.json
M qemu-options.hx
M system/vl.c
M target/s390x/cpu-sysemu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/cpu_models.c
M target/s390x/kvm/kvm.c
M target/s390x/kvm/kvm_s390x.h
M target/s390x/kvm/meson.build
A target/s390x/kvm/stsi-topology.c
A tests/avocado/s390_topology.py
M tests/qtest/migration-test.c
Log Message:
-----------
Merge tag 'pull-request-2023-10-18' of https://gitlab.com/thuth/qemu into
staging
* s390x CPU topology support
* Clean up global variable shadowing in s390x code
* Simplify the KVM register synchronization code
* Disable the analyze-migration.py test on s390x
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# =XLK/
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 18 Oct 2023 06:05:02 PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-10-18' of https://gitlab.com/thuth/qemu: (25 commits)
tests/qtest/migration-test: Disable the analyze-migration.py test on s390x
target/s390x/kvm: Simplify the GPRs, ACRs, CRs and prefix synchronization code
target/s390x/kvm: Turn KVM_CAP_SYNC_REGS into a hard requirement
hw/s390x: Clean up global variable shadowing in quiesce_powerdown_req()
tests/avocado: s390x cpu topology bad move
tests/avocado: s390x cpu topology dedicated errors
tests/avocado: s390x cpu topology test socket full
tests/avocado: s390x cpu topology test dedicated CPU
tests/avocado: s390x cpu topology entitlement tests
tests/avocado: s390x cpu topology polarization
tests/avocado: s390x cpu topology core
docs/s390x/cpu topology: document s390x cpu topology
qapi/s390x/cpu topology: add query-s390x-cpu-polarization command
qapi/s390x/cpu topology: CPU_POLARIZATION_CHANGE QAPI event
machine: adding s390 topology to info hotpluggable-cpus
machine: adding s390 topology to query-cpu-fast
qapi/s390x/cpu topology: set-cpu-topology qmp command
target/s390x/cpu topology: activate CPU topology
s390x/cpu topology: interception of PTF instruction
s390x/cpu topology: resetting the Topology-Change-Report
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: ac765199323990220dd90b4347c0c2b435daf3f9
https://github.com/qemu/qemu/commit/ac765199323990220dd90b4347c0c2b435daf3f9
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
M docs/interop/vhost-user.rst
M docs/system/target-i386-desc.rst.inc
M hw/acpi/cxl.c
M hw/block/vhost-user-blk.c
M hw/display/virtio-dmabuf.c
M hw/i386/Kconfig
M hw/i386/acpi-build.c
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/isa/Kconfig
M hw/isa/lpc_ich9.c
M hw/isa/meson.build
A hw/isa/piix.c
R hw/isa/piix3.c
R hw/isa/piix4.c
M hw/mips/Kconfig
M hw/mips/malta.c
M hw/scsi/vhost-scsi-common.c
M hw/scsi/vhost-scsi.c
M hw/scsi/vhost-user-scsi.c
M hw/timer/i8254_common.c
M hw/virtio/vhost-backend.c
M hw/virtio/vhost-shadow-virtqueue.c
M hw/virtio/vhost-shadow-virtqueue.h
M hw/virtio/vhost-user-gpio.c
M hw/virtio/vhost-user.c
M hw/virtio/vhost.c
M hw/virtio/virtio.c
M include/exec/memory.h
M include/hw/acpi/cxl.h
M include/hw/i386/pc.h
M include/hw/southbridge/piix.h
M include/hw/virtio/vhost-scsi-common.h
M include/hw/virtio/vhost-user-scsi.h
M include/hw/virtio/vhost-user.h
M include/hw/virtio/vhost.h
M meson.build
M net/vhost-vdpa.c
M subprojects/libvhost-user/libvhost-user.h
A tests/data/acpi/q35/APIC.core-count
M tests/data/acpi/q35/APIC.core-count2
A tests/data/acpi/q35/APIC.thread-count
A tests/data/acpi/q35/APIC.thread-count2
A tests/data/acpi/q35/APIC.type4-count
A tests/data/acpi/q35/DSDT.core-count
M tests/data/acpi/q35/DSDT.core-count2
M tests/data/acpi/q35/DSDT.cxl
A tests/data/acpi/q35/DSDT.thread-count
A tests/data/acpi/q35/DSDT.thread-count2
A tests/data/acpi/q35/DSDT.type4-count
A tests/data/acpi/q35/FACP.core-count
A tests/data/acpi/q35/FACP.thread-count
A tests/data/acpi/q35/FACP.thread-count2
A tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test.c
M tests/unit/test-smp-parse.c
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: features, cleanups
lots of vhost-vdpa shadow work
piix south bridge rework
reconnect for vhost-user-scsi
dummy ACPI QTG DSM for cxl
tests, cleanups, fixes all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# bUSnjsODjJ4jFkY+zgbu4rlPYNuX4LNiDH6vL7KHe8qQ7GEVPH8=
# =YKE8
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 18 Oct 2023 08:49:51 PDT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (83
commits)
intel-iommu: Report interrupt remapping faults, fix return value
MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section
vhost-user: Fix protocol feature bit conflict
tests/acpi: Update DSDT.cxl with QTG DSM
hw/cxl: Add QTG _DSM support for ACPI0017 device
tests/acpi: Allow update of DSDT.cxl
hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range
vhost-user: fix lost reconnect
vhost-user-scsi: start vhost when guest kicks
vhost-user-scsi: support reconnect to backend
vhost: move and rename the conn retry times
vhost-user-common: send get_inflight_fd once
hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
hw/isa/piix: Implement multi-process QEMU support also for PIIX4
hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
hw/isa/piix: Share PIIX3's base class with PIIX4
hw/isa/piix: Harmonize names of reset control memory regions
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 79cc3d6b8a4123cafeb65ae429d04cdc013f702e
https://github.com/qemu/qemu/commit/79cc3d6b8a4123cafeb65ae429d04cdc013f702e
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M MAINTAINERS
M hw/hppa/Kconfig
M hw/hppa/hppa_hardware.h
M hw/hppa/machine.c
M hw/input/lasips2.c
M hw/net/tulip.c
M hw/pci-host/Kconfig
A hw/pci-host/astro.c
M hw/pci-host/meson.build
M hw/pci-host/trace-events
A include/hw/pci-host/astro.h
M include/hw/pci/pci_ids.h
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
Log Message:
-----------
Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into
staging
target/hppa: Add emulation of a C3700 HP-PARISC workstation
This series adds a new PA-RISC machine emulation for the HP-PARISC
C3700 workstation.
The physical HP C3700 machine has a PA2.0 (64-bit) CPU, in contrast to
the existing emulation of a B160L workstation which is a 32-bit only
machine and where it's Dino PCI controller isn't 64-bit capable.
With the HP C3700 machine emulation (together with the emulated Astro
Memory controller and the Elroy PCI bridge) it's now possible to
enhance the hppa CPU emulation to support the 64-bit instruction set
in upcoming patches.
Helge
v4 changes:
- moved HP VENDOR PCI ID numerically into list (suggested by BALATON Zoltan)
v3 changes:
based on feedback from BALATON Zoltan <balaton@eik.bme.hu>:
- apply paches in different order to bring them logically closer to each other
- update comments in lasips2
- rephrased title and commit message of MAINTAINERS patch
v2 changes:
suggestions by BALATON Zoltan <balaton@eik.bme.hu>:
- merged pci_ids and tulip patch
- dropped comments in lasips2
- mention additional cleanups in patch "Require at least SeaBIOS-hppa version
10"
suggestions by Philippe Mathieu-Daudé <philmd@linaro.org>:
- dropped static pci_bus variable
# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZTBCpAAKCRD3ErUQojoP
# XydlAQDLnWPUE455zZoO+awqSQz3GCQq6Ntqiqjovyd/s/0EwAEAw52YAitYaIxQ
# l3EALFVQUOxIKdbhYBg2LagxpsTXFgM=
# =0i4o
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 18 Oct 2023 13:40:04 PDT
# gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg: aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603
# Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F
* tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa:
hw/hppa: Add new HP C3700 machine
hw/hppa: Split out machine creation
hw/hppa: Provide RTC and DebugOutputPort on CPU #0
hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg
MAINTAINERS: Update HP-PARISC entries
pci-host: Wire up new Astro/Elroy PCI bridge
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
lasips2: LASI PS/2 devices are not user-createable
pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip
hw/hppa: Require at least SeaBIOS-hppa version 10
target/hppa: Update to SeaBIOS-hppa version 10
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: fa26b060abddee2d73c7d8bca34dc8f6b98f7986
https://github.com/qemu/qemu/commit/fa26b060abddee2d73c7d8bca34dc8f6b98f7986
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M include/tcg/tcg-op.h
M include/tcg/tcg.h
M target/i386/tcg/translate.c
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
Merge tag 'pull-tcg-20231018' of https://gitlab.com/rth7680/qemu into staging
tcg: Drop unused tcg_temp_free define
tcg: Introduce tcg_use_softmmu
tcg: Optimize past conditional branches
tcg: Use constant zero when expanding with divu2
tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB
tcg/ppc: Use ADDPCIS for power9
tcg/ppc: Use prefixed instructions for power10
tcg/ppc: Disable TCG_REG_TB for Power9/Power10
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# gpg: Signature made Wed 18 Oct 2023 15:23:22 PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20231018' of https://gitlab.com/rth7680/qemu: (29 commits)
target/i386: Use i128 for 128 and 256-bit loads and stores
tcg: Add tcg_gen_{ld,st}_i128
tcg: Optimize past conditional branches
tcg: Use constant zero when expanding with divu2
tcg: drop unused tcg_temp_free define
tcg/s390x: Use tcg_use_softmmu
tcg/riscv: Use tcg_use_softmmu
tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero
tcg/ppc: Use tcg_use_softmmu
tcg/mips: Use tcg_use_softmmu
tcg/loongarch64: Use tcg_use_softmmu
tcg/i386: Use tcg_use_softmmu
tcg/aarch64: Use tcg_use_softmmu
tcg/arm: Use tcg_use_softmmu
tcg: Provide guest_base fallback for system mode
tcg: Introduce tcg_use_softmmu
tcg/ppc: Disable TCG_REG_TB for Power9/Power10
tcg/ppc: Use PLD in tcg_out_goto_tb
tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec
tcg/ppc: Use PLD in tcg_out_movi for constant pool
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 10d7aedab6ca317bd3906ffe42c8ba7eed975779
https://github.com/qemu/qemu/commit/10d7aedab6ca317bd3906ffe42c8ba7eed975779
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-19 (Thu, 19 Oct 2023)
Changed paths:
M linux-user/elfload.c
M linux-user/mips/cpu_loop.c
M linux-user/mmap.c
M linux-user/sh4/signal.c
M linux-user/signal.c
Log Message:
-----------
Merge tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu into staging
linux-user/mips: fix abort on integer overflow
linux-user/sh4: Fix crashes on signal delivery
linux-user/loongarch: Enable LSX/LASX in HWCAP
linux-user: Fixes for zero_bss
linux-user: Propagate failure in mmap_reserve_or_unmap back to target_munmap
linux-user: Detect and report host crashes
linux-user: Remap guest SIGABRT
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 18 Oct 2023 16:30:30 PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu:
linux-user: Remap guest SIGABRT
linux-user: Detect and report host SIGILL, SIGFPE, SIGTRAP
linux-user: Split out host_sig{segv,bus}_handler
linux-user: Simplify signal_init
linux-user: Map unsupported signals to an out-of-bounds value
linux-user: Only register handlers for core_dump_signal by default
linux-user: Detect and report host crashes
linux-user: Exit not abort in die_with_backtrace
linux-user: Split out die_with_signal
linux-user: Propagate failure in mmap_reserve_or_unmap back to target_munmap
linux-user/elfload: Enable LSX/LASX in HWCAP for LoongArch
linux-user/sh4: Fix crashes on signal delivery
linux-user/mips: fix abort on integer overflow
linux-user: Fixes for zero_bss
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/deaca3fd30d3...10d7aedab6ca
- [Qemu-commits] [qemu/qemu] ce32a9: target/hppa: Update to SeaBIOS-hppa version 10,
Alex Bennée <=