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[Qemu-commits] [qemu/qemu] b31750: Update AMD memory encryption document
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] b31750: Update AMD memory encryption document links. |
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Date: |
Thu, 12 Oct 2023 07:26:56 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: b3175081a1215339b741ee92a00d5678a3094249
https://github.com/qemu/qemu/commit/b3175081a1215339b741ee92a00d5678a3094249
Author: Jianlin Li <ljianlin99@gmail.com>
Date: 2023-10-11 (Wed, 11 Oct 2023)
Changed paths:
M docs/system/i386/amd-memory-encryption.rst
Log Message:
-----------
Update AMD memory encryption document links.
The previous links for the white paper and programmer's manual
are no longer available. Replace them with the new ones.
Signed-off-by: Jianlin Li <ljianlin99@gmail.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 99bb31585cccd474b852deb29bd982e2ee542871
https://github.com/qemu/qemu/commit/99bb31585cccd474b852deb29bd982e2ee542871
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-10-11 (Wed, 11 Oct 2023)
Changed paths:
M qga/commands-win32.c
Log Message:
-----------
qga: Remove platform GUID definitions
GUID_DEVINTERFACE_DISK and GUID_DEVINTERFACE_STORAGEPORT are already
defined by MinGW-w64. They are not only unnecessary, but can lead to
duplicate definition errors at link time with some unknown condition.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: d6f67b83b81bf49b5c62e77143ed39c020e51830
https://github.com/qemu/qemu/commit/d6f67b83b81bf49b5c62e77143ed39c020e51830
Author: Daniel Xu <dxu@dxuuu.xyz>
Date: 2023-10-11 (Wed, 11 Oct 2023)
Changed paths:
M qga/commands.c
Log Message:
-----------
qga: Fix memory leak when output stream is unused
If capture-output is requested but one of the channels goes unused (eg.
we attempt to capture stderr but the command never writes to stderr), we
can leak memory.
guest_exec_output_watch() is (from what I understand) unconditionally
called for both streams if output capture is requested. The first call
will always pass the `p->size == p->length` check b/c both values are
0. Then GUEST_EXEC_IO_SIZE bytes will be allocated for the stream.
But when we reap the exited process there's a `gei->err.length > 0`
check to actually free the buffer. Which does not get run if the command
doesn't write to the stream.
Fix by making free() unconditional.
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Signed-off-by: Daniel Xu <dxu@dxuuu.xyz>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: f897ef0d47d332d4c4498aed1140c6856fe56d79
https://github.com/qemu/qemu/commit/f897ef0d47d332d4c4498aed1140c6856fe56d79
Author: Daniel Xu <dxu@dxuuu.xyz>
Date: 2023-10-11 (Wed, 11 Oct 2023)
Changed paths:
M qga/qapi-schema.json
Log Message:
-----------
qapi: qga: Clarify when out-data and err-data are populated
If output is being captured for a guest-exec invocation, the out-data
and err-data fields of guest-exec-status are only populated after the
process is reaped. This is somewhat counter intuitive and too late to
change. Thus, it would be good to document the behavior.
Signed-off-by: Daniel Xu <dxu@dxuuu.xyz>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: bb30277273fdacff4635a59d5181f7a093cab6a8
https://github.com/qemu/qemu/commit/bb30277273fdacff4635a59d5181f7a093cab6a8
Author: Pierre Labatut <plabatut@google.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M subprojects/libvhost-user/libvhost-user.c
Log Message:
-----------
Fix compilation when UFFDIO_REGISTER is not set.
Signed-off-by: Pierre Labatut <plabatut@google.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 740ee84db8732c11e2db8bba6630046634f3c5e9
https://github.com/qemu/qemu/commit/740ee84db8732c11e2db8bba6630046634f3c5e9
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add g364fb and ds1225y to the Jazz section
These devices are only used by the Jazz machine, so they
should be listed in the corresponding section in MAINTAINERS.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 5d0ce90dd6881b044bf1a28dc966eee44bcc1dde
https://github.com/qemu/qemu/commit/5d0ce90dd6881b044bf1a28dc966eee44bcc1dde
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add unowned RISC-V related files to the right sections
There are a bunch of RISC-V files that are currently not covered
by the "get_maintainers.pl" script. Add them to the right sections
in MAINTAINERS to fix this problem.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Acked-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 63fc07233e7939d595ee4e8e24710c637b9785c0
https://github.com/qemu/qemu/commit/63fc07233e7939d595ee4e8e24710c637b9785c0
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add include folder to the hw/char/ section
The "Character devices" section only covers hw/char/ but
misses the corresponding include/hw/char/ folder. Add it now.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 145af2779c30d5a74c252b6146fa83e8d8120786
https://github.com/qemu/qemu/commit/145af2779c30d5a74c252b6146fa83e8d8120786
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add the CI-related doc files to the CI section
The docs/devel/ci* were not covered yet, add them to MAINTAINERS
so that the right people are put on CC: for related patches.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: e05ea75f75c023c0520cd9ea2f6e93b008822347
https://github.com/qemu/qemu/commit/e05ea75f75c023c0520cd9ea2f6e93b008822347
Author: Cornelia Huck <cohuck@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: add standard-headers to Hosts/LINUX
The files in there are updated via update-linux-headers.sh.
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 39131a4e530afb6d926cab871d8bcc99a2df1288
https://github.com/qemu/qemu/commit/39131a4e530afb6d926cab871d8bcc99a2df1288
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add section for overall sensors
Sensor devices depend on some bus, not a particular board.
While merged for a particular board, sensor devices don't
depend on it. They depend on a bus technology, and can be
used by any board exposing such bus.
In order to help merging sensor patches, when they fall out
of a particular board tree, add a section covering overall
sensors, to help out with patch review and merge queue
handling.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: d02ce621ea98517a40510f1540813b5dedbe3a79
https://github.com/qemu/qemu/commit/d02ce621ea98517a40510f1540813b5dedbe3a79
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add some unowned files to the SBSA-REF section
These files belong to the sbsa-ref machine and thus should
be listed here.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 17b8d8ac3309e2cfed0d8cb3861afdcc23f66ce0
https://github.com/qemu/qemu/commit/17b8d8ac3309e2cfed0d8cb3861afdcc23f66ce0
Author: Olaf Hering <olaf@aepfle.de>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M roms/Makefile
Log Message:
-----------
roms: use PYTHON to invoke python
python3 may not be the expected python version.
Use PYTHON to invoke python.
Fixes: 22e11539e1 ("edk2: replace build scripts")
Signed-off-by: Olaf Hering <olaf@aepfle.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 0848ca87b76b21639f314bd348ae8470db5b22e2
https://github.com/qemu/qemu/commit/0848ca87b76b21639f314bd348ae8470db5b22e2
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M scripts/xml-preprocess.py
Log Message:
-----------
scripts/xml-preprocess: Make sure this script is invoked via the right Python
If a script is executable and has a shebang line, Meson treats it as
a normal executable, so that this script here is run via the "python3"
binary in the $PATH. However, "python3" might not be in the $PATH at
all, or it might be a wrong version, so we should make sure to run
this script via the Python version that has been chosen for the QEMU
build process. The best way to do this is to remove the executable bit
from the access mode bits. (See also commit 4b424c757188f7a4)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1918
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: b216b5daa57ce068183ce865c163f4df01b74614
https://github.com/qemu/qemu/commit/b216b5daa57ce068183ce865c163f4df01b74614
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M include/sysemu/cpus.h
Log Message:
-----------
cpus: Remove unused smp_cores/smp_threads declarations
Commit a5e0b33119 ("vl.c: Replace smp global variables
with smp machine properties") removed the last uses of
the smp_cores / smp_threads variables but forgot to
remove their declarations. Do it now.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit: 8ea3fceff4e0622f16441e261d125709c8819577
https://github.com/qemu/qemu/commit/8ea3fceff4e0622f16441e261d125709c8819577
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] array for them. Add all these properties in
riscv_cpu_add_user_properties() as it is already being done today.
'mmu' and 'pmp' aren't really extensions in the usual way we think about
RISC-V extensions. These are closer to CPU features/options, so move
both to riscv_cpu_options[] too. In the near future we'll need to match
all extensions with all entries in isa_edata_arr[], and so it happens
that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv
spec version restriction). This further emphasizes the point that these
are more a CPU option than an extension.
No functional changes made.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bfb37c693a8dd19f41f9017821a48c188eed41e7
https://github.com/qemu/qemu/commit/bfb37c693a8dd19f41f9017821a48c188eed41e7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: skip 'bool' check when filtering KVM props
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 68aba1f2af89b0bc6231264dfcfc9e78e1fe2a10
https://github.com/qemu/qemu/commit/68aba1f2af89b0bc6231264dfcfc9e78e1fe2a10
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv/cpu.c: split kvm prop handling to its own helper
Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to share a couple of common
lines of code between the two.
Create a new kvm_riscv_cpu_add_kvm_properties() helper that will be
forked from riscv_cpu_add_user_properties() if we're running KVM. The
helper includes all properties that a KVM CPU will add. The rest of
riscv_cpu_add_user_properties() body will then be relieved from having
to deal with KVM constraints.
The helper was declared in kvm_stubs.h, while being implemented in
cpu.c, to allow '--enable-debug' builds to work. The compiler won't
remove the kvm_riscv_cpu_add_kvm_properties() reference when
'kvm_enabled()' is false if we end up with an unused function. Even
though being a KVM only helper we can't implement it in kvm.c due to its
many dependencies inside cpu.c, so make it public in kvm_riscv.h and
keep its implementation in cpu.c for now. We'll move it to kvm.c in the
near future.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d09d085a088bc7da92bbb68d9c2fed0e6dc8aed8
https://github.com/qemu/qemu/commit/d09d085a088bc7da92bbb68d9c2fed0e6dc8aed8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].
We also have a more sophisticated motivation behind this change. In the
future we might need to export riscv_cpu_options[] to other files, and
ARRAY_LIST() doesn't work properly in that case because the array size
isn't exposed to the header file. Here's a future sight of what we would
deal with:
./target/riscv/kvm.c:1057:5: error: nested extern declaration of
'riscv_cpu_add_misa_properties' [-Werror=nested-externs]
n file included from ../target/riscv/kvm.c:19:
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application
of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
| ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 | for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
| ^~~~~~~~~~
./target/riscv/kvm.c:1059:5: note: in expansion of macro
'ADD_UNAVAIL_KVM_PROP_ARRAY'
1059 | ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application
of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
| ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 | for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
Homogenize the present and change the future by using
DEFINE_PROP_END_OF_LIST() in riscv_cpu_options[].
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b955fd1a009153bf398ad91c84a9d9a85574193a
https://github.com/qemu/qemu/commit/b955fd1a009153bf398ad91c84a9d9a85574193a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratified properties to users.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 82822b5d5a5fe2a7f780c9d27534ecaa42cacdec
https://github.com/qemu/qemu/commit/82822b5d5a5fe2a7f780c9d27534ecaa42cacdec
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 370d7c8ef8fb4630fb422c4176477d134ac8793d
https://github.com/qemu/qemu/commit/370d7c8ef8fb4630fb422c4176477d134ac8793d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a helper to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b55c39b3f57dfad1fca00aaa042ec569ab6e8ecd
https://github.com/qemu/qemu/commit/b55c39b3f57dfad1fca00aaa042ec569ab6e8ecd
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230912132423.268494-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cbaac1d22b80364e31f075c651912451018d4459
https://github.com/qemu/qemu/commit/cbaac1d22b80364e31f075c651912451018d4459
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: limit cfg->vext_spec log message
Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.
We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
version is not specified" message from appearing. The usefulness of this
log message is debatable for the generic CPUs, but for a 'max' CPU type,
where we are supposed to deliver a CPU model with all features possible,
it's strange to force users to set 'vext_spec' to get rid of this
message.
Change riscv_cpu_validate_v() to not throw this log message if
env->vext_ver is already set.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230912132423.268494-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b97e5a6b0a93f8e8b83c18c89c4c408fb7ae7cb0
https://github.com/qemu/qemu/commit/b97e5a6b0a93f8e8b83c18c89c4c408fb7ae7cb0
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add 'max' CPU type
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to
ratified, non-vendor extensions. This means that we want the 'max' CPU
to enable all (possible) ratified extensions by default. The reasoning
behind this design is (1) vendor extensions can conflict with each other
and we won't play favorities deciding which one is default or not and
(2) non-ratified extensions are always prone to changes, not being
stable enough to be enabled by default.
All this said, we're still not able to enable all ratified extensions
due to conflicts between them. Zfinx and all its dependencies aren't
enabled because of a conflict with RVF. zce, zcmp and zcmt are also
disabled due to RVD conflicts. When running with 64 bits we're also
disabling zcf.
MISA bits RVG, RVJ and RVV are also being set manually since they're
default disabled.
This is the resulting 'riscv,isa' DT for this new CPU:
rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dfe7d2280a80cb3a212b99d1aa8ef23ddc1022a4
https://github.com/qemu/qemu/commit/dfe7d2280a80cb3a212b99d1aa8ef23ddc1022a4
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M tests/avocado/tuxrun_baselines.py
Log Message:
-----------
avocado, risc-v: add tuxboot tests for 'max' CPU
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new frozen/ratified RISC-V extensions.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f57d5f8004b70c3f7356eda574be7639d97ea2be
https://github.com/qemu/qemu/commit/f57d5f8004b70c3f7356eda574be7639d97ea2be
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M docs/about/deprecated.rst
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: deprecate the 'any' CPU type
The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't help us either in
knowing what was the original design of this CPU type.
The closest we have is a comment from Alistair [1] where he recalls from
memory that the 'any' CPU is supposed to behave like the newly added
'max' CPU. He also suggested that the 'any' CPU should be removed.
The default CPUs are rv32 and rv64, so removing the 'any' CPU will have
impact only on users that might have a script that uses '-cpu any'.
And those users are better off using the default CPUs or the new 'max'
CPU.
We would love to just remove the code and be done with it, but one does
not simply remove a feature in QEMU. We'll put the CPU in quarantine
first, letting users know that we have the intent of removing it in the
future.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5f2c80f1a014a90382752ad592ccc97183b53bae
https://github.com/qemu/qemu/commit/5f2c80f1a014a90382752ad592ccc97183b53bae
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 238fd586e0bc06d104d2d095170945b97ea56e19
https://github.com/qemu/qemu/commit/238fd586e0bc06d104d2d095170945b97ea56e19
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: make CPUCFG() macro public
The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.
Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 997e71952d1eb8d60b0807d01cf3956d84728067
https://github.com/qemu/qemu/commit/997e71952d1eb8d60b0807d01cf3956d84728067
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
During realize() time we're activating a lot of extensions based on some
criteria, e.g.:
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
This practice resulted in at least one case where we ended up enabling
something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that
has priv_spec older than 1.12.0.
We're also not considering user choice. There's no way of doing it now
but this is about to change in the next few patches.
cpu_cfg_ext_auto_update() will check for priv version mismatches before
enabling extensions. If we have a mismatch between the current priv
version and the extension we want to enable, do not enable it. In the
near future, this same function will also consider user choice when
deciding if we're going to enable/disable an extension or not.
For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c72b3791278a398b121c8482171b1a8f66481420
https://github.com/qemu/qemu/commit/c72b3791278a398b121c8482171b1a8f66481420
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).
We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every other extension enablement
during realize is now done via cpu_cfg_ext_auto_update().
The end goal is that only cpu init() functions will handle extension
flags directly via "cpu->cfg.ext_N = true|false".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 549cbf789ef8669a835207e020db67d20045b1a9
https://github.com/qemu/qemu/commit/549cbf789ef8669a835207e020db67d20045b1a9
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Property set()
callback. The set() callback also does init() time validations based on
the current KVM driver capabilities.
For TCG we would want a 'user_set' mechanic too, but we would look
ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set
or not. If we copy what was made in the KVM side we would look for
'user_set' for one into 60+ extension structs spreaded in 3 arrays
(riscv_cpu_extensions, riscv_cpu_experimental_exts,
riscv_cpu_vendor_exts).
We'll still need an extension struct but we won't be using the
'user_set' flag:
- 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to what
we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'.
DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by
MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct;
- the 'multi_ext_user_opts' hash will be used to store the offset of each
extension that the user set via the set() callback, cpu_set_multi_ext_cfg().
For now we're just initializing and populating it - next patch will use
it to determine if a certain extension was user set;
- cpu_add_multi_ext_prop() is a new helper that will replace the
qdev_property_add_static() calls that our macros are doing to populate
user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY()
for clarity. Note that the non-extension properties in
riscv_cpu_options[] still need to be declared via qdev().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 25aa6f7202d5403ac123abe5cd5ff08f2e003f77
https://github.com/qemu/qemu/commit/25aa6f7202d5403ac123abe5cd5ff08f2e003f77
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.
This means that, as is today, all extensions we're setting for the 'max'
CPU will be seen as user set in the future. Let's change set_bool() to
isa_ext_update_enabled() that will just enable/disable the flag on a
certain offset.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0a9eb9b497f3d349da77073e704c1a010cb788e5
https://github.com/qemu/qemu/commit/0a9eb9b497f3d349da77073e704c1a010cb788e5
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.
This will make us honor user choice instead of overwriting the values.
Users will then be informed whether they're using an incompatible set of
extensions instead of QEMU setting a magic value that works.
The reason why we're not implementing user choice for MISA extensions
right now is because, today, we do not silently change any MISA bit
during realize() time (we do warn when enabling bits if RVG is enabled).
We do that - a lot - with multi-letter extensions though, so we're
handling the most immediate concern first.
After this patch, we'll now error out if the user explicitly set 'zce' to true
and 'zca' to false:
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=true,zca=false -nographic
qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension
This didn't happen before because we were enabling 'zca' if 'zce' was enabled
regardless if the user set 'zca' to false.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 67f94b09ac4f64d4a0595d1224ba3a425e565043
https://github.com/qemu/qemu/commit/67f94b09ac4f64d4a0595d1224ba3a425e565043
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: consider user option with RVG
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabling ifencei or icsr while enabling RVG will
result in error:
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false
--nographic
qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8633951530cc923f1e7a6cd250f670f24c0ed817
https://github.com/qemu/qemu/commit/8633951530cc923f1e7a6cd250f670f24c0ed817
Author: liguang.zhang <liguang.zhang@hexintek.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv: Clear CSR values at reset and sync MPSTATE with host
This patch fixes guest reboot errors when using KVM.
There are two issues when rebooting a guest using KVM
1. When the guest initiates a reboot the host is unable to stop the vcpu
2. When running a SMP guest the qemu monitor system_reset causes a vcpu crash
This can be fixed by clearing the CSR values at reset and syncing the
MPSTATE with the host.
Signed-off-by: liguang.zhang <liguang.zhang@hexintek.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230913091332.17355-1-18622748025@163.com>
[ Changes by AF
- Fixup commit message
- Fixup patch style
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cffa9954908830276c93b430681f66cc0e599aef
https://github.com/qemu/qemu/commit/cffa9954908830276c93b430681f66cc0e599aef
Author: Alvin Chang <vivahavey@gmail.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name().
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230907084500.328-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9c5180d7998b8e211ec038e5342b305e78e06e22
https://github.com/qemu/qemu/commit/9c5180d7998b8e211ec038e5342b305e78e06e22
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/meson.build
A target/riscv/tcg/meson.build
A target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get cluttered over time. Splitting
acceleration specific code from cpu.c to its own file will help to
declutter the existing code and it will also make it easier to support
KVM/TCG only builds in the future.
We'll start by adding a new subdir called 'tcg' and a new file called
'tcg-cpu.c'. This file will be used to introduce a new accelerator class
for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
code in its file instead of using 'cpu.c' for everything. This design is
inpired by the work Claudio Fontana did in x86 a few years ago in commit
f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
AccelCPUClass").
To avoid moving too much code at once we'll start by adding the new file
and TCG AccelCPUClass declaration. The 'class_init' from the accel class
will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
doing it.
'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
to deal with moving code and files around right now. We'll focus on
decoupling the realize() logic first.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9dcecbd724ebadd8c957356e629aab9d724e9889
https://github.com/qemu/qemu/commit/9dcecbd724ebadd8c957356e629aab9d724e9889
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
realize() path during the common riscv_cpu_realize(), making it a good
choice to start moving TCG exclusive code to tcg-cpu.c.
Rename it to tcg_cpu_realizefn() and assign it as a implementation of
accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
approach with KVM in the near future.
riscv_cpu_validate_set_extensions() is too big and with too many
dependencies to be moved in this same patch. We'll do that next.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230925175709.35696-3-dbarboza@ventanamicro.com>
[ Changes by AF:
- Renames to fix build failures after rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 36c1118d500b95d26d1f07deb93402f9d596cabf
https://github.com/qemu/qemu/commit/36c1118d500b95d26d1f07deb93402f9d596cabf
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/tcg/tcg-cpu.c
A target/riscv/tcg/tcg-cpu.h
Log Message:
-----------
target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
This function is the core of the RISC-V validations for TCG CPUs, and it
has a lot going on.
Functions in cpu.c were made public to allow them to be used by the KVM
accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
hard to move it to another file due to its dependency with isa_edata_arr[]
array, thus make it public and use it as is for now.
riscv_cpu_validate_set_extensions() is kept public because it's used by
csr.c in write_misa().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e7443334a87b1cc43d20daacd72db44b530b7a28
https://github.com/qemu/qemu/commit/e7443334a87b1cc43d20daacd72db44b530b7a28
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: move riscv_tcg_ops to tcg-cpu.c
Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 977bbb04525682fd7a2ed8d28c0590bc2873db06
https://github.com/qemu/qemu/commit/977bbb04525682fd7a2ed8d28c0590bc2873db06
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add .instance_post_init()
All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:
riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()
In the near future riscv_cpu_post_init() will call the init() function
of the current accelerator, providing a hook for KVM and TCG accel
classes to change the init() process of the CPU.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a7e87cd7bfd4580bc745cf12440f4e26329bc747
https://github.com/qemu/qemu/commit/a7e87cd7bfd4580bc745cf12440f4e26329bc747
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: move 'host' CPU declaration to kvm.c
This CPU only exists if we're compiling with KVM so move it to the kvm
specific file.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ec34cd732ce33af59a913444320f870c6309de51
https://github.com/qemu/qemu/commit/ec34cd732ce33af59a913444320f870c6309de51
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: mark extensions arrays as 'const'
We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now because they should not be modified at
runtime.
Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are changed via
qdev_property_add_static().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 32fa177604a8f0e3be331add04da91fef28bfbbd
https://github.com/qemu/qemu/commit/32fa177604a8f0e3be331add04da91fef28bfbbd
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
We'll introduce the KVM accelerator class with a 'cpu_instance_init'
implementation that is going to be invoked during the common
riscv_cpu_post_init() (via accel_cpu_instance_init()). This
instance_init will execute KVM exclusive code that TCG doesn't care
about, such as adding KVM specific properties, initing registers using a
KVM scratch CPU and so on.
The core of the forementioned cpu_instance_init impl is the current
riscv_cpu_add_kvm_properties() that is being used by the common code via
riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
will all the relevant artifacts, exporting and renaming it to
kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.
To make this work we'll need to export riscv_cpu_extensions,
riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
well. The TCG accelerator will also need to access those in the near
future so this export will benefit us in the long run.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7d0c302c53ce7508326092d3ed07497f82961ff7
https://github.com/qemu/qemu/commit/7d0c302c53ce7508326092d3ed07497f82961ff7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: make riscv_add_satp_mode_properties() public
This function is used for both accelerators. Make it public, and call it
from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
split KVM specific code for the KVM accelerator class in the next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5c67bc73be9f896809b8ab4eb64020faa66ed491
https://github.com/qemu/qemu/commit/5c67bc73be9f896809b8ab4eb64020faa66ed491
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
R target/riscv/kvm-stub.c
M target/riscv/meson.build
Log Message:
-----------
target/riscv: remove kvm-stub.c
This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
in non-KVM builds.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d86c25b292bf9685615cbb93d7b07f33a9b63104
https://github.com/qemu/qemu/commit/d86c25b292bf9685615cbb93d7b07f33a9b63104
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv: introduce KVM AccelCPUClass
Add a KVM accelerator class like we did with TCG. The difference is
that, at least for now, we won't be using a realize() implementation for
this accelerator.
We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
through the 'cpu_instance_init' impl of the current acceleration (if
available) and execute it. The end result is that the KVM initial setup,
i.e. starting registers and adding its specific properties, will be done
via this hook.
Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
calling riscv_cpu_add_user_properties() when running KVM. We'll remove
this condition when the TCG accel class get its own 'cpu_instance_init'
implementation.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fb80f33377df221728d6c3c298f19b0da7ba277a
https://github.com/qemu/qemu/commit/fb80f33377df221728d6c3c298f19b0da7ba277a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/riscv/virt.c
M target/riscv/cpu.c
R target/riscv/kvm.c
A target/riscv/kvm/kvm-cpu.c
A target/riscv/kvm/kvm_riscv.h
A target/riscv/kvm/meson.build
R target/riscv/kvm_riscv.h
M target/riscv/meson.build
Log Message:
-----------
target/riscv: move KVM only files to kvm subdir
Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: efa365b711075eee996a657ec4b399e27ec8fa4f
https://github.com/qemu/qemu/commit/efa365b711075eee996a657ec4b399e27ec8fa4f
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
riscv_cpu_add_misa_properties() is being used to fill the missing KVM
MISA properties but it is a TCG helper that was adapted to do so. We'll
move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
the remaining MISA properties on its own.
Do not use riscv_cpu_add_misa_properties(). Let's create a new array
with all available MISA bits we support that can be read by KVM. The
array is zero terminate to allow us to iterate through it without
knowing its size.
Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
MISA properties as usual and then use this array to add any missing MISA
properties with the riscv_cpu_add_kvm_unavail_prop() helper.
Note that we're creating misa_bits[], and not using the existing
'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
related functions and it doesn't have all MISA bits we support. Commit
0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
full context.
While we're at it, move both satp and the multi-letter extension
properties to kvm_riscv_add_cpu_user_properties() as well.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f51d03b01fac6cf2757d02efe1cc2679b1d133ac
https://github.com/qemu/qemu/commit/f51d03b01fac6cf2757d02efe1cc2679b1d133ac
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv/cpu.c: export set_misa()
We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
patch and set_misa() needs to be usable from there.
Rename it to riscv_cpu_set_misa() and make it public.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fce8bb5d088c655be18b1642e716489df608a0c4
https://github.com/qemu/qemu/commit/fce8bb5d088c655be18b1642e716489df608a0c4
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg: introduce tcg_cpu_instance_init()
tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
accelerator. It'll be called from within riscv_cpu_post_init(), via
accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
preserve behavior, the implementation will be similar to what
riscv_cpu_post_init() already does.
In this patch we'll move riscv_cpu_add_user_properties() and
riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
All multi-extension properties code was moved. The 'multi_ext_user_opts'
hash table was also moved to tcg-cpu.c since it's a TCG only structure,
meaning that we won't have to worry about initializing a TCG hash table
when running a KVM CPU anymore.
riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
much code it requires to be moved at the same time. We'll do that in the
next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1dbb6104ffb428f3a559855a49c28b91c8d3b401
https://github.com/qemu/qemu/commit/1dbb6104ffb428f3a559855a49c28b91c8d3b401
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
The array isn't marked as 'const' because we're initializing their
elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
fields.
In a closer look we can see that we're not using these 2 fields after
creating the MISA properties. And we can create the properties by using
riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
directly.
Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
and make misa_ext_cfgs[] a const array.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4de9151b20ad0b33ea975e84b437bc15a804375d
https://github.com/qemu/qemu/commit/4de9151b20ad0b33ea975e84b437bc15a804375d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
All code related to MISA TCG properties is also moved.
At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
properties handling is done in kvm-cpu.c.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7935e2c49c1ecb7b106d62bd91791cc02eea71ef
https://github.com/qemu/qemu/commit/7935e2c49c1ecb7b106d62bd91791cc02eea71ef
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv/cpu.c: export isa_edata_arr[]
This array will be read by the TCG accel class, allowing it to handle
priv spec verifications on its own. The array will remain here in cpu.c
because it's also used by the riscv,isa string function.
To export it we'll finish it with an empty element since ARRAY_SIZE()
won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
alleviate the changes for the next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 31778448f2c39565062014ae89ca8c2f82522fe5
https://github.com/qemu/qemu/commit/31778448f2c39565062014ae89ca8c2f82522fe5
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/cpu: move priv spec functions to tcg-cpu.c
Priv spec validation is TCG specific. Move it to the TCG accel class.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230925175709.35696-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b933720be22442e6847629fe0dcf24b95cef3d56
https://github.com/qemu/qemu/commit/b933720be22442e6847629fe0dcf24b95cef3d56
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: add riscv_cpu_get_name()
We'll introduce generic errors that will output a CPU type name via its
RISCVCPU pointer. Create a helper for that.
Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host'
CPU name.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230926183109.165878-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eb992b609159212c55ed26971dde7743c956cb7a
https://github.com/qemu/qemu/commit/eb992b609159212c55ed26971dde7743c956cb7a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg-cpu.c: add extension properties for all cpus
At this moment we do not expose extension properties for vendor CPUs
because that would allow users to change them via command line. The
drawback is that if we were to add an API that shows all CPU properties,
e.g. qmp-query-cpu-model-expansion, we won't be able to show extensions
state of vendor CPUs.
We have the required machinery to create extension properties for vendor
CPUs while not allowing users to enable extensions. Disabling existing
extensions is allowed since it can be useful for debugging.
Change the set() callback cpu_set_multi_ext_cfg() to allow enabling
extensions only for generic CPUs. In cpu_add_multi_ext_prop() let's not
set the default values for the properties if we're not dealing with
generic CPUs, otherwise the values set in cpu_init() of vendor CPUs will
be overwritten. And finally, in tcg_cpu_instance_init(), add cpu user
properties for all CPUs.
For the veyron-v1 CPU, we're now able to disable existing extensions
like smstateen:
$ ./build/qemu-system-riscv64 --nographic -M virt \
-cpu veyron-v1,smstateen=false
But setting extensions that the CPU didn't set during cpu_init(), like
V, is not allowed:
$ ./build/qemu-system-riscv64 --nographic -M virt \
-cpu veyron-v1,v=true
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.v=true:
'veyron-v1' CPU does not allow enabling extensions
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230926183109.165878-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0386f39b46a28da87647075f0fc20da4ba1f6478
https://github.com/qemu/qemu/commit/0386f39b46a28da87647075f0fc20da4ba1f6478
Author: Clément Chigot <chigot@adacore.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M include/sysemu/runstate.h
M system/runstate.c
Log Message:
-----------
softmmu: add means to pass an exit code when requesting a shutdown
As of now, the exit code was either EXIT_FAILURE when a panic shutdown
was requested or EXIT_SUCCESS otherwise.
However, some hardware could want to pass more complex exit codes. Thus,
introduce a new shutdown request function allowing that.
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-2-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 66bbe3e9b46112ec2fe35a7d6e79d8a9bb39d14a
https://github.com/qemu/qemu/commit/66bbe3e9b46112ec2fe35a7d6e79d8a9bb39d14a
Author: Clément Chigot <chigot@adacore.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M include/sysemu/sysemu.h
M system/main.c
M system/runstate.c
Log Message:
-----------
softmmu: pass the main loop status to gdb "Wxx" packet
gdb_exit function aims to close gdb sessions and sends the exit code of
the current execution. It's being called by qemu_cleanup once the main
loop is over.
Until now, the exit code sent was always 0. Now that hardware can
shutdown this main loop with custom exit codes, these codes must be
transfered to gdb as well.
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-3-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 215128e44bd3095b254e2f3d8ff067eadf166a1d
https://github.com/qemu/qemu/commit/215128e44bd3095b254e2f3d8ff067eadf166a1d
Author: Clément Chigot <chigot@adacore.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M hw/misc/sifive_test.c
Log Message:
-----------
hw/misc/sifive_test.c: replace exit calls with proper shutdown
This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Otherwise, some connections like gdb could be broken
before its final packet ("Wxx") is being sent. This part, being done
inside qemu_cleanup function, can be reached only when the main loop
exits after a shutdown request.
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-4-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 354c96069c4b6af176c03b046087e971ac621177
https://github.com/qemu/qemu/commit/354c96069c4b6af176c03b046087e971ac621177
Author: Clément Chigot <chigot@adacore.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char: riscv_htif: replace exit calls with proper shutdown
This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Otherwise, some connections like gdb could be broken
before its final packet ("Wxx") is being sent. This part, being done
inside qemu_cleanup function, can be reached only when the main loop
exits after a shutdown request.
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-5-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e216256ae9fc3d1988e3f1af3f644b4dafb79838
https://github.com/qemu/qemu/commit/e216256ae9fc3d1988e3f1af3f644b4dafb79838
Author: Clément Chigot <chigot@adacore.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M gdbstub/gdbstub.c
M gdbstub/system.c
M gdbstub/user.c
M include/gdbstub/syscalls.h
Log Message:
-----------
gdbstub: replace exit calls with proper shutdown for softmmu
This replaces the exit calls by shutdown requests, ensuring a proper
cleanup of Qemu. Features like net/vhost-vdpa.c are expecting
qemu_cleanup to be called to remove their last residuals.
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231003071427.188697-6-chigot@adacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 082e9e4a58ba80ec056220a2f762a1c6b9a3a96c
https://github.com/qemu/qemu/commit/082e9e4a58ba80ec056220a2f762a1c6b9a3a96c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: improve 'init_multiext_cfg' error msg
Our error message is returning the value of 'ret', which will be always
-1 in case of error, and will not be that useful:
qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error -1
Improve the error message by outputting 'errno' instead of 'ret'. Use
strerrorname_np() to output the error name instead of the error code.
This will give us what we need to know right away:
qemu-system-riscv64: Unable to read ISA_EXT KVM register ssaia, error code:
ENOENT
Given that we're going to exit(1) in this condition instead of
attempting to recover, remove the 'kvm_riscv_destroy_scratch_vcpu()'
call.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231003132148.797921-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 608bdebb6075b757e5505f6bbc60c45a54a1390b
https://github.com/qemu/qemu/commit/608bdebb6075b757e5505f6bbc60c45a54a1390b
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: support KVM_GET_REG_LIST
KVM for RISC-V started supporting KVM_GET_REG_LIST in Linux 6.6. It
consists of a KVM ioctl() that retrieves a list of all available regs
for get_one_reg/set_one_reg. Regs that aren't present in the list aren't
supported in the host.
This simplifies our lives when initing the KVM regs since we don't have
to always attempt a KVM_GET_ONE_REG for all regs QEMU knows. We'll only
attempt a get_one_reg() if we're sure the reg is supported, i.e. it was
retrieved by KVM_GET_REG_LIST. Any error in get_one_reg() will then
always considered fatal, instead of having to handle special error codes
that might indicate a non-fatal failure.
Start by moving the current kvm_riscv_init_multiext_cfg() logic into a
new kvm_riscv_read_multiext_legacy() helper. We'll prioritize using
KVM_GET_REG_LIST, so check if we have it available and, in case we
don't, use the legacy() logic.
Otherwise, retrieve the available reg list and use it to check if the
host supports our known KVM regs, doing the usual get_one_reg() for
the supported regs and setting cpu->cfg accordingly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003132148.797921-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9b9741c38f2a92eb99c74f2bf387fc7a12d7f8e2
https://github.com/qemu/qemu/commit/9b9741c38f2a92eb99c74f2bf387fc7a12d7f8e2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg: remove RVG warning
Vendor CPUs that set RVG are displaying user warnings about other
extensions that RVG must enable, one warning per CPU. E.g.:
$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
This happens because we decided a while ago that, for simplicity, vendor
CPUs could set RVG instead of setting each G extension individually in
their cpu_init(). Our warning isn't taking that into account, and we're
bugging users with a warning that we're causing ourselves.
In a closer look we conclude that this warning is not warranted in any
other circumstance since we're just following the ISA [1], which states
in chapter 24:
"One goal of the RISC-V project is that it be used as a stable software
development target. For this purpose, we define a combination of a base
ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for
the IMAFDZicsr Zifencei combination of instruction-set extensions."
With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly
enables 'G' is an expected behavior and the warning is unneeded. Any
user caught by surprise should refer to the ISA.
Remove the warning when handling RVG.
[1]
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
Reported-by: Paul A. Clarke <pclarke@ventanamicro.com>
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 614c9466a238641480332b707a7a20a3593bdfb7
https://github.com/qemu/qemu/commit/614c9466a238641480332b707a7a20a3593bdfb7
Author: Richard W.M. Jones <rjones@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Use env_archcpu for better performance
RISCV_CPU(cs) uses a checked cast. When QOM cast debugging is enabled
this adds about 5% total overhead when emulating RV64 on x86-64 host.
Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk
disk. The guest has a copy of the qemu source tree. The test
involves compiling the qemu source tree with 'make clean; time make -j16'.
Before making this change the compile step took 449 & 447 seconds over
two consecutive runs.
After making this change: 428 & 421 seconds.
The saving is over 5%.
Thanks: Paolo Bonzini
Thanks: Philippe Mathieu-Daudé
Signed-off-by: Richard W.M. Jones <rjones@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231009124859.3373696-2-rjones@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8043effd9b0368c626192cde36c8b83389a617f6
https://github.com/qemu/qemu/commit/8043effd9b0368c626192cde36c8b83389a617f6
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M docs/about/deprecated.rst
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: deprecate capital 'Z' CPU properties
At this moment there are eleven CPU extension properties that starts
with capital 'Z': Zifencei, Zicsr, Zihintntl, Zihintpause, Zawrs, Zfa,
Zfh, Zfhmin, Zve32f, Zve64f and Zve64d. All other extensions are named
with lower-case letters.
We want all properties to be named with lower-case letters since it's
consistent with the riscv-isa string that we create in the FDT. Having
these 11 properties to be exceptions can be confusing.
Deprecate all of them. Create their lower-case counterpart to be used as
maintained CPU properties. When trying to use any deprecated property a
warning message will be displayed, recommending users to switch to the
lower-case variant:
./build/qemu-system-riscv64 -M virt -cpu rv64,Zifencei=true --nographic
qemu-system-riscv64: warning: CPU property 'Zifencei' is deprecated. Please use
'zifencei' instead
This will give users some time to change their scripts before we remove
the capital 'Z' properties entirely.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231009112817.8896-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 837570cef237b634eb4c245363470deebea7089d
https://github.com/qemu/qemu/commit/837570cef237b634eb4c245363470deebea7089d
Author: Max Chou <max.chou@sifive.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix vfwmaccbf16.vf
The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
replaced by fwmaccbf16.
Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231005095734.567575-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4892e41e6ee238efb327835923ac943ec7449bc4
https://github.com/qemu/qemu/commit/4892e41e6ee238efb327835923ac943ec7449bc4
Author: Jeuk Kim <jeuk20.kim@samsung.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M hw/ufs/lu.c
M hw/ufs/ufs.c
M tests/qtest/ufs-test.c
Log Message:
-----------
hw/ufs: Fix code coverity issues
Fixed four ufs-related coverity issues.
The coverity issues and fixes are as follows
1. CID 1519042: Security issue with the rand() function
Changed to use a fixed value (0xab) instead of rand() as
the value for testing
2. CID 1519043: Dereference after null check
Removed useless (redundant) null checks
3. CID 1519050: Out-of-bounds access issue
Fix to pass an array type variable to find_first_bit and
find_next_bit using DECLARE_BITMAP()
4. CID 1519051: Out-of-bounds read issue
Fix incorrect range check for lun
Fix coverity CID: 1519042 1519043 1519050 1519051
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
Commit: 8466aa53d623377e114895c6563face25370d7da
https://github.com/qemu/qemu/commit/8466aa53d623377e114895c6563face25370d7da
Author: Jeuk Kim <jeuk20.kim@samsung.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M include/block/ufs.h
Log Message:
-----------
hw/ufs: Fix incorrect register fields
This patch fixes invalid ufs register fields.
This fixes an issue reported by Bin Meng that
caused ufs to fail over riscv.
Fixes: bc4e68d362ec ("hw/ufs: Initial commit for emulated
Universal-Flash-Storage")
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
Reported-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Commit: ab3ec1586a05036aa3bc2af314a917a17df85938
https://github.com/qemu/qemu/commit/ab3ec1586a05036aa3bc2af314a917a17df85938
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M qga/commands-win32.c
M qga/commands.c
M qga/qapi-schema.json
Log Message:
-----------
Merge tag 'qga-pull-2023-10-11' of https://github.com/kostyanf14/qemu into
staging
qga-pull-2023-10-11
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# gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign)
<kkostiuk@redhat.com>" [unknown]
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# Primary key fingerprint: C2C2 C109 EA43 C63C 1423 EB84 EF5D 5E81 61BA 84E7
* tag 'qga-pull-2023-10-11' of https://github.com/kostyanf14/qemu:
qapi: qga: Clarify when out-data and err-data are populated
qga: Fix memory leak when output stream is unused
qga: Remove platform GUID definitions
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 40886c4cf58fdadaa600dabb8c86c9b4394b9ac8
https://github.com/qemu/qemu/commit/40886c4cf58fdadaa600dabb8c86c9b4394b9ac8
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M MAINTAINERS
M docs/system/i386/amd-memory-encryption.rst
M include/sysemu/cpus.h
M roms/Makefile
M scripts/xml-preprocess.py
M subprojects/libvhost-user/libvhost-user.c
Log Message:
-----------
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2023-10-12
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# bXNrLnJ1AAoJEHAbT2saaT5ZBv8H/0MtWL6FqTzvz5yLn2WSbj2ng1RG1Deh36Sy
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# O8Ct8++MLPqnwgu6Rg6Z+Ie2yBtsQ5VABH/1q36T7+XHHh19bgEw6tW34/f2Ncxw
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# 7rSGvNM+Lm7mEgJSyyik+u0MshKjfRi+SrbvId9FIqACG1GCKeI=
# =rFns
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 11 Oct 2023 17:37:51 EDT
# gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg: issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full]
# gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full]
# gpg: aka "Michael Tokarev <mjt@debian.org>" [full]
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5
# Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59
* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu:
cpus: Remove unused smp_cores/smp_threads declarations
scripts/xml-preprocess: Make sure this script is invoked via the right Python
roms: use PYTHON to invoke python
MAINTAINERS: Add some unowned files to the SBSA-REF section
MAINTAINERS: Add section for overall sensors
MAINTAINERS: add standard-headers to Hosts/LINUX
MAINTAINERS: Add the CI-related doc files to the CI section
MAINTAINERS: Add include folder to the hw/char/ section
MAINTAINERS: Add unowned RISC-V related files to the right sections
MAINTAINERS: Add g364fb and ds1225y to the Jazz section
Fix compilation when UFFDIO_REGISTER is not set.
Update AMD memory encryption document links.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 63011373ad22c794a013da69663c03f1297a5c56
https://github.com/qemu/qemu/commit/63011373ad22c794a013da69663c03f1297a5c56
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M disas/riscv.c
M docs/about/deprecated.rst
M gdbstub/gdbstub.c
M gdbstub/system.c
M gdbstub/user.c
M hw/char/riscv_htif.c
M hw/intc/riscv_aplic.c
M hw/misc/sifive_test.c
M hw/riscv/virt.c
M include/gdbstub/syscalls.h
M include/sysemu/runstate.h
M include/sysemu/sysemu.h
M system/main.c
M system/runstate.c
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
R target/riscv/kvm-stub.c
R target/riscv/kvm.c
A target/riscv/kvm/kvm-cpu.c
A target/riscv/kvm/kvm_riscv.h
A target/riscv/kvm/meson.build
R target/riscv/kvm_riscv.h
M target/riscv/meson.build
A target/riscv/tcg/meson.build
A target/riscv/tcg/tcg-cpu.c
A target/riscv/tcg/tcg-cpu.h
M target/riscv/vector_helper.c
M tests/avocado/tuxrun_baselines.py
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20231012-1' of
https://github.com/alistair23/qemu into staging
Second RISC-V PR for 8.2
* Add support for the max CPU
* Detect user choice in TCG
* Clear CSR values at reset and sync MPSTATE with host
* Fix the typo of inverted order of pmpaddr13 and pmpaddr14
* Split TCG/KVM accelerators from cpu.c
* Add extension properties for all cpus
* Replace GDB exit calls with proper shutdown
* Support KVM_GET_REG_LIST
* Remove RVG warning
* Use env_archcpu for better performance
* Deprecate capital 'Z' CPU properties
* Fix vfwmaccbf16.vf
# -----BEGIN PGP SIGNATURE-----
#
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# hkJMsYROSRvk54RHITrD9Z+XFQ2TfC8wHLH0IwlyynQnc1sKvXaR6U1hZTAVtE4f
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 12 Oct 2023 00:09:36 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20231012-1' of https://github.com/alistair23/qemu:
(54 commits)
target/riscv: Fix vfwmaccbf16.vf
target/riscv: deprecate capital 'Z' CPU properties
target/riscv: Use env_archcpu for better performance
target/riscv/tcg: remove RVG warning
target/riscv/kvm: support KVM_GET_REG_LIST
target/riscv/kvm: improve 'init_multiext_cfg' error msg
gdbstub: replace exit calls with proper shutdown for softmmu
hw/char: riscv_htif: replace exit calls with proper shutdown
hw/misc/sifive_test.c: replace exit calls with proper shutdown
softmmu: pass the main loop status to gdb "Wxx" packet
softmmu: add means to pass an exit code when requesting a shutdown
target/riscv/tcg-cpu.c: add extension properties for all cpus
target/riscv: add riscv_cpu_get_name()
target/riscv/cpu: move priv spec functions to tcg-cpu.c
target/riscv/cpu.c: export isa_edata_arr[]
target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
target/riscv/tcg: introduce tcg_cpu_instance_init()
target/riscv/cpu.c: export set_misa()
target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 8d44786c5b56c0077b8f777d91e8be9c41f6a5ee
https://github.com/qemu/qemu/commit/8d44786c5b56c0077b8f777d91e8be9c41f6a5ee
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-10-12 (Thu, 12 Oct 2023)
Changed paths:
M hw/ufs/lu.c
M hw/ufs/ufs.c
M include/block/ufs.h
M tests/qtest/ufs-test.c
Log Message:
-----------
Merge tag 'pull-ufs-20231012' of https://gitlab.com/jeuk20.kim/qemu into
staging
hw/ufs: fixes
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 12 Oct 2023 02:07:58 EDT
# gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602
# gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown]
# gpg: aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602
* tag 'pull-ufs-20231012' of https://gitlab.com/jeuk20.kim/qemu:
hw/ufs: Fix incorrect register fields
hw/ufs: Fix code coverity issues
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/a51e5124a655...8d44786c5b56
- [Qemu-commits] [qemu/qemu] b31750: Update AMD memory encryption document links.,
Alex Bennée <=