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[Qemu-commits] [qemu/qemu] 8d6b2f: hw/gpio/nrf51: implement DETECT signa
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 8d6b2f: hw/gpio/nrf51: implement DETECT signal |
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Date: |
Thu, 24 Aug 2023 07:16:44 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 8d6b2f947d4d19b3ba22f836d203d6282107bc11
https://github.com/qemu/qemu/commit/8d6b2f947d4d19b3ba22f836d203d6282107bc11
Author: Chris Laplante <chris@laplante.io>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M hw/gpio/nrf51_gpio.c
M include/hw/gpio/nrf51_gpio.h
Log Message:
-----------
hw/gpio/nrf51: implement DETECT signal
Implement nRF51 DETECT signal in the GPIO peripheral.
The reference manual makes mention of a per-pin DETECT signal, but these
are not exposed to the user. See
https://devzone.nordicsemi.com/f/nordic-q-a/39858/gpio-per-pin-detect-signal-available
for more information. Currently, I don't see a reason to model these.
Signed-off-by: Chris Laplante <chris@laplante.io>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230728160324.1159090-2-chris@laplante.io
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7458dcf4e64249af961243cb1619858a242ec15e
https://github.com/qemu/qemu/commit/7458dcf4e64249af961243cb1619858a242ec15e
Author: Chris Laplante <chris@laplante.io>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M softmmu/qtest.c
Log Message:
-----------
qtest: factor out qtest_install_gpio_out_intercept
Signed-off-by: Chris Laplante <chris@laplante.io>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230728160324.1159090-3-chris@laplante.io
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a8610f8bd7465a9c30c206074d47dd3f387b5b9a
https://github.com/qemu/qemu/commit/a8610f8bd7465a9c30c206074d47dd3f387b5b9a
Author: Chris Laplante <chris@laplante.io>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M softmmu/qtest.c
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
qtest: implement named interception of out-GPIO
Adds qtest_irq_intercept_out_named method, which utilizes a new optional
name parameter to the irq_intercept_out qtest command.
Signed-off-by: Chris Laplante <chris@laplante.io>
Message-id: 20230728160324.1159090-4-chris@laplante.io
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fe692f7c8c477dd794a45b18148e248c3c327931
https://github.com/qemu/qemu/commit/fe692f7c8c477dd794a45b18148e248c3c327931
Author: Chris Laplante <chris@laplante.io>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M softmmu/qtest.c
Log Message:
-----------
qtest: bail from irq_intercept_in if name is specified
Named interception of in-GPIOs is not supported yet.
Signed-off-by: Chris Laplante <chris@laplante.io>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230728160324.1159090-5-chris@laplante.io
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c7bb6fa6afb427f9538bf2f95ea55e8a1ce8da60
https://github.com/qemu/qemu/commit/c7bb6fa6afb427f9538bf2f95ea55e8a1ce8da60
Author: Chris Laplante <chris@laplante.io>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M softmmu/qtest.c
Log Message:
-----------
qtest: irq_intercept_[out/in]: return FAIL if no intercepts are installed
This is much better than just silently failing with OK.
Signed-off-by: Chris Laplante <chris@laplante.io>
Message-id: 20230728160324.1159090-6-chris@laplante.io
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a9c9bbee855877293683012942d3485d50f286af
https://github.com/qemu/qemu/commit/a9c9bbee855877293683012942d3485d50f286af
Author: Chris Laplante <chris@laplante.io>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M tests/qtest/microbit-test.c
Log Message:
-----------
qtest: microbit-test: add tests for nRF51 DETECT
Exercise the DETECT mechanism of the GPIO peripheral.
Signed-off-by: Chris Laplante <chris@laplante.io>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230728160324.1159090-7-chris@laplante.io
[PMM: fixed coding style nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5e0d65909c6f335d578b90491e165440c99adf81
https://github.com/qemu/qemu/commit/5e0d65909c6f335d578b90491e165440c99adf81
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M accel/kvm/kvm-all.c
M hw/mips/loongson3_virt.c
M include/sysemu/kvm.h
M target/arm/kvm.c
M target/i386/kvm/kvm.c
M target/mips/kvm.c
M target/mips/kvm_mips.h
M target/ppc/kvm.c
M target/riscv/kvm.c
M target/s390x/kvm/kvm.c
Log Message:
-----------
kvm: Introduce kvm_arch_get_default_type hook
kvm_arch_get_default_type() returns the default KVM type. This hook is
particularly useful to derive a KVM type that is valid for "none"
machine model, which is used by libvirt to probe the availability of
KVM.
For MIPS, the existing mips_kvm_type() is reused. This function ensures
the availability of VZ which is mandatory to use KVM on the current
QEMU.
Cc: qemu-stable@nongnu.org
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230727073134.134102-2-akihiko.odaki@daynix.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added doc comment for new function]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1ab445af8cd99343f29032b5944023ad7d8edebf
https://github.com/qemu/qemu/commit/1ab445af8cd99343f29032b5944023ad7d8edebf
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/kvm.c
Log Message:
-----------
accel/kvm: Specify default IPA size for arm64
Before this change, the default KVM type, which is used for non-virt
machine models, was 0.
The kernel documentation says:
> On arm64, the physical address size for a VM (IPA Size limit) is
> limited to 40bits by default. The limit can be configured if the host
> supports the extension KVM_CAP_ARM_VM_IPA_SIZE. When supported, use
> KVM_VM_TYPE_ARM_IPA_SIZE(IPA_Bits) to set the size in the machine type
> identifier, where IPA_Bits is the maximum width of any physical
> address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
> machine type identifier.
>
> e.g, to configure a guest to use 48bit physical address size::
>
> vm_fd = ioctl(dev_fd, KVM_CREATE_VM, KVM_VM_TYPE_ARM_IPA_SIZE(48));
>
> The requested size (IPA_Bits) must be:
>
> == =========================================================
> 0 Implies default size, 40bits (for backward compatibility)
> N Implies N bits, where N is a positive integer such that,
> 32 <= N <= Host_IPA_Limit
> == =========================================================
> Host_IPA_Limit is the maximum possible value for IPA_Bits on the host
> and is dependent on the CPU capability and the kernel configuration.
> The limit can be retrieved using KVM_CAP_ARM_VM_IPA_SIZE of the
> KVM_CHECK_EXTENSION ioctl() at run-time.
>
> Creation of the VM will fail if the requested IPA size (whether it is
> implicit or explicit) is unsupported on the host.
https://docs.kernel.org/virt/kvm/api.html#kvm-create-vm
So if Host_IPA_Limit < 40, specifying 0 as the type will fail. This
actually confused libvirt, which uses "none" machine model to probe the
KVM availability, on M2 MacBook Air.
Fix this by using Host_IPA_Limit as the default type when
KVM_CAP_ARM_VM_IPA_SIZE is available.
Cc: qemu-stable@nongnu.org
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230727073134.134102-3-akihiko.odaki@daynix.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 875b3eb88f7d09c0bd650b3d5f0e642d55f199bc
https://github.com/qemu/qemu/commit/875b3eb88f7d09c0bd650b3d5f0e642d55f199bc
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/mips/kvm.c
Log Message:
-----------
mips: Report an error when KVM_VM_MIPS_VZ is unavailable
On MIPS, QEMU requires KVM_VM_MIPS_VZ type for KVM. Report an error in
such a case as other architectures do when an error occurred during KVM
type decision.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230727073134.134102-4-akihiko.odaki@daynix.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: bc3e41a0e8a3c932733dd363dfcfb38bf167b707
https://github.com/qemu/qemu/commit/bc3e41a0e8a3c932733dd363dfcfb38bf167b707
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M accel/kvm/kvm-all.c
M hw/arm/virt.c
M hw/ppc/spapr.c
Log Message:
-----------
accel/kvm: Use negative KVM type for error propagation
On MIPS, kvm_arch_get_default_type() returns a negative value when an
error occurred so handle the case. Also, let other machines return
negative values when errors occur and declare returning a negative
value as the correct way to propagate an error that happened when
determining KVM type.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230727073134.134102-5-akihiko.odaki@daynix.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4625742cd2aeb1400407889a2f7a5b4c75437818
https://github.com/qemu/qemu/commit/4625742cd2aeb1400407889a2f7a5b4c75437818
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: Free as when an error occurred
An error may occur after s->as is allocated, for example if the
KVM_CREATE_VM ioctl call fails.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230727073134.134102-6-akihiko.odaki@daynix.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 43a5e377f42d1d3ed12ea562196f723b354ce411
https://github.com/qemu/qemu/commit/43a5e377f42d1d3ed12ea562196f723b354ce411
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: Make kvm_dirty_ring_reaper_init() void
The returned value was always zero and had no meaning.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-id: 20230727073134.134102-7-akihiko.odaki@daynix.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: c986d860398ff44c32a612b3d8dfc9f89ffe5e52
https://github.com/qemu/qemu/commit/c986d860398ff44c32a612b3d8dfc9f89ffe5e52
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault
For an Unsupported Atomic Update fault where the stage 1 translation
table descriptor update can't be done because it's to an unsupported
memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This
means we should not set fi->s1ptw, because this will cause the code
in the get_phys_addr_lpae() error-exit path to mark it as stage 2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-2-peter.maydell@linaro.org
Commit: f6415660746fcf58d6baf8dd8da77cb08adb9970
https://github.com/qemu/qemu/commit/f6415660746fcf58d6baf8dd8da77cb08adb9970
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults
In S1_ptw_translate() we set up the ARMMMUFaultInfo if the attempt to
translate the page descriptor address into a physical address fails.
This used to only be possible if we are doing a stage 2 ptw for that
descriptor address, and so the code always sets fi->stage2 and
fi->s1ptw to true. However, with FEAT_RME it is also possible for
the lookup of the page descriptor address to fail because of a
Granule Protection Check fault. These should not be reported as
stage 2, otherwise arm_deliver_fault() will incorrectly set
HPFAR_EL2. Similarly the s1ptw bit should only be set for stage 2
faults on stage 1 translation table walks, i.e. not for GPC faults.
Add a comment to the the other place where we might detect a
stage2-fault-on-stage-1-ptw, in arm_casq_ptw(), noting why we know in
that case that it must really be a stage 2 fault and not a GPC fault.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-3-peter.maydell@linaro.org
Commit: 4f51edd3cd1746c0eee66eebafdfb642f8dd7e87
https://github.com/qemu/qemu/commit/4f51edd3cd1746c0eee66eebafdfb642f8dd7e87
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Set s1ns bit in fault info more consistently
The s1ns bit in ARMMMUFaultInfo is documented as "true if
we faulted on a non-secure IPA while in secure state". Both the
places which look at this bit only do so after having confirmed
that this is a stage 2 fault and we're dealing with Secure EL2,
which leaves the ptw.c code free to set the bit to any random
value in the other cases.
Instead of taking advantage of that freedom, consistently
make the bit be set to false for the "not a stage 2 fault
for Secure EL2" cases. This removes some cases where we
were using an 'is_secure' boolean and leaving the reader
guessing about whether that was the right thing for Realm
and Root cases.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-4-peter.maydell@linaro.org
Commit: a5637bec4c8989373f70c3d2841988c967fc4642
https://github.com/qemu/qemu/commit/a5637bec4c8989373f70c3d2841988c967fc4642
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and
get_phys_addr_disabled()
In commit 6d2654ffacea813916176 we created the S1Translate struct and
used it to plumb through various arguments that we were previously
passing one-at-a-time to get_phys_addr_v5(), get_phys_addr_v6(), and
get_phys_addr_lpae(). Extend that pattern to get_phys_addr_pmsav5(),
get_phys_addr_pmsav7(), get_phys_addr_pmsav8() and
get_phys_addr_disabled(), so that all the get_phys_addr_* functions
we call from get_phys_addr_nogpc() take the S1Translate struct rather
than the mmu_idx and is_secure bool.
(This refactoring is a prelude to having the called functions look
at ptw->is_space rather than using an is_secure boolean.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-5-peter.maydell@linaro.org
Commit: d1289140a009f17633a1badeeddcff5746c258c9
https://github.com/qemu/qemu/commit/d1289140a009f17633a1badeeddcff5746c258c9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled()
Plumb the ARMSecurityState through to regime_translation_disabled()
rather than just a bool is_secure.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-6-peter.maydell@linaro.org
Commit: 2d12bb96bdb8ccded608e56af8c644602b2bebf7
https://github.com/qemu/qemu/commit/2d12bb96bdb8ccded608e56af8c644602b2bebf7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate()
arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to
determine whether EL2 is enabled in the current security state.
With the advent of FEAT_RME this is no longer sufficient, because
EL2 can be enabled for Secure state but not for Root, and both
of those will pass 'secure == true' in the callsites in ptw.c.
As it happens in all of our callsites in ptw.c we either avoid making
the call or else avoid using the returned value if we're doing a
translation for Root, so this is not a behaviour change even if the
experimental FEAT_RME is enabled. But it is less confusing in the
ptw.c code if we avoid the use of a bool secure that duplicates some
of the information in the ArmSecuritySpace argument.
Make arm_hcr_el2_eff_secstate() take an ARMSecuritySpace argument
instead. Because we always want to know the HCR_EL2 for the
security state defined by the current effective value of
SCR_EL3.{NSE,NS}, it makes no sense to pass ARMSS_Root here,
and we assert that callers don't do that.
To avoid the assert(), we thus push the call to
arm_hcr_el2_eff_secstate() down into the cases in
regime_translation_disabled() that need it, rather than calling the
function and ignoring the result for the Root space translations.
All other calls to this function in ptw.c are already in places
where we have confirmed that the mmu_idx is a stage 2 translation
or that the regime EL is not 3.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-7-peter.maydell@linaro.org
Commit: 4477020d3811d0509241d0b752015f1ead2196bc
https://github.com/qemu/qemu/commit/4477020d3811d0509241d0b752015f1ead2196bc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate()
Pass an ARMSecuritySpace instead of a bool secure to
arm_is_el2_enabled_secstate(). This doesn't change behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-8-peter.maydell@linaro.org
Commit: b9c139dc581c793094b1889f304e049a75e2d455
https://github.com/qemu/qemu/commit/b9c139dc581c793094b1889f304e049a75e2d455
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Only fold in NSTable bit effects in Secure state
When we do a translation in Secure state, the NSTable bits in table
descriptors may downgrade us to NonSecure; we update ptw->in_secure
and ptw->in_space accordingly. We guard that check correctly with a
conditional that means it's only applied for Secure stage 1
translations. However, later on in get_phys_addr_lpae() we fold the
effects of the NSTable bits into the final descriptor attributes
bits, and there we do it unconditionally regardless of the CPU state.
That means that in Realm state (where in_secure is false) we will set
bit 5 in attrs, and later use it to decide to output to non-secure
space.
We don't in fact need to do this folding in at all any more (since
commit 2f1ff4e7b9f30c): if an NSTable bit was set then we have
already set ptw->in_space to ARMSS_NonSecure, and in that situation
we don't look at attrs bit 5. The only thing we still need to deal
with is the real NS bit in the final descriptor word, so we can just
drop the code that ORed in the NSTable bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-9-peter.maydell@linaro.org
Commit: cdbae5e7e1de104e2cc168a7938ed0c5b467a3e7
https://github.com/qemu/qemu/commit/cdbae5e7e1de104e2cc168a7938ed0c5b467a3e7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Remove last uses of ptw->in_secure
Replace the last uses of ptw->in_secure with appropriate
checks on ptw->in_space.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-10-peter.maydell@linaro.org
Commit: 6279f6dcdb08a45597536b546faa6a178a2c0f4a
https://github.com/qemu/qemu/commit/6279f6dcdb08a45597536b546faa6a178a2c0f4a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Remove S1Translate::in_secure
We no longer look at the in_secure field of the S1Translate struct
anyway, so we can remove it and all the code which sets it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-11-peter.maydell@linaro.org
Commit: b02f5e06bcc87a52b9955d1425faadc9ddc9d38e
https://github.com/qemu/qemu/commit/b02f5e06bcc87a52b9955d1425faadc9ddc9d38e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Drop S1Translate::out_secure
We only use S1Translate::out_secure in two places, where we are
setting up MemTxAttrs for a page table load. We can use
arm_space_is_secure(ptw->out_space) instead, which guarantees
that we're setting the MemTxAttrs secure and space fields
consistently, and allows us to drop the out_secure field in
S1Translate entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-12-peter.maydell@linaro.org
Commit: 3d9ca96221ba7212aacb27ec472f0be703e99a78
https://github.com/qemu/qemu/commit/3d9ca96221ba7212aacb27ec472f0be703e99a78
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Set attributes correctly for MMU disabled data accesses
When the MMU is disabled, data accesses should be Device nGnRnE,
Outer Shareable, Untagged. We handle the other cases from
AArch64.S1DisabledOutput() correctly but missed this one.
Device nGnRnE is memattr == 0, so the only part we were missing
was that shareability should be set to 2 for both insn fetches
and data accesses.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-13-peter.maydell@linaro.org
Commit: d53e25075bd9c89c81ab2bfc45ccbcdc92842b24
https://github.com/qemu/qemu/commit/d53e25075bd9c89c81ab2bfc45ccbcdc92842b24
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Check for block descriptors at invalid levels
The architecture doesn't permit block descriptors at any arbitrary
level of the page table walk; it depends on the granule size which
levels are permitted. We implemented only a partial version of this
check which assumes that block descriptors are valid at all levels
except level 3, which meant that we wouldn't deliver the Translation
fault for all cases of this sort of guest page table error.
Implement the logic corresponding to the pseudocode
AArch64.DecodeDescriptorType() and AArch64.BlockDescSupported().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-14-peter.maydell@linaro.org
Commit: a729d63642b01f2b7a3c1db468811a7b40b88f70
https://github.com/qemu/qemu/commit/a729d63642b01f2b7a3c1db468811a7b40b88f70
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw
When we report faults due to stage 2 faults during a stage 1
page table walk, the 'level' parameter should be the level
of the walk in stage 2 that faulted, not the level of the
walk in stage 1. Correct the reporting of these faults.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-15-peter.maydell@linaro.org
Commit: b17d86eb5ef745f393f3387b15df2b9b2aaae793
https://github.com/qemu/qemu/commit/b17d86eb5ef745f393f3387b15df2b9b2aaae793
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types
The PAR_EL1.SH field documents that for the cases of:
* Device memory
* Normal memory with both Inner and Outer Non-Cacheable
the field should be 0b10 rather than whatever was in the
translation table descriptor field. (In the pseudocode this
is handled by PAREncodeShareability().) Perform this
adjustment when assembling a PAR value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807141514.19075-16-peter.maydell@linaro.org
Commit: da64251e9317b3937cad54f71f606f5f9b837c8e
https://github.com/qemu/qemu/commit/da64251e9317b3937cad54f71f606f5f9b837c8e
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm/ptw: Load stage-2 tables from realm physical space
In realm state, stage-2 translation tables are fetched from the realm
physical address space (R_PGRQD).
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230809123706.1842548-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ceaa97465f58cf2b3b4fc07a3b1067eb6f48d2e3
https://github.com/qemu/qemu/commit/ceaa97465f58cf2b3b4fc07a3b1067eb6f48d2e3
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2*
When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0
translation regime, instead of the EL2 translation regime. The TLB VAE2*
instructions invalidate the regime that corresponds to the current value
of HCR_EL2.E2H.
At the moment we only invalidate the EL2 translation regime. This causes
problems with RMM, which issues TLBI VAE2IS instructions with
HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into
account.
Add vae2_tlbbits() as well, since the top-byte-ignore configuration is
different between the EL2&0 and EL2 regime.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230809123706.1842548-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f1269a98aaf8e2884cb067d09bce0d3056ede289
https://github.com/qemu/qemu/commit/f1269a98aaf8e2884cb067d09bce0d3056ede289
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Skip granule protection checks for AT instructions
GPC checks are not performed on the output address for AT instructions,
as stated by ARM DDI 0487J in D8.12.2:
When populating PAR_EL1 with the result of an address translation
instruction, granule protection checks are not performed on the final
output address of a successful translation.
Rename get_phys_addr_with_secure(), since it's only used to handle AT
instructions.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230809123706.1842548-4-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e1ee56ec2383fcc6c1bab613e783a0c190fc0ea7
https://github.com/qemu/qemu/commit/e1ee56ec2383fcc6c1bab613e783a0c190fc0ea7
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Pass security space rather than flag for AT instructions
At the moment we only handle Secure and Nonsecure security spaces for
the AT instructions. Add support for Realm and Root.
For AArch64, arm_security_space() gives the desired space. ARM DDI0487J
says (R_NYXTL):
If EL3 is implemented, then when an address translation instruction
that applies to an Exception level lower than EL3 is executed, the
Effective value of SCR_EL3.{NSE, NS} determines the target Security
state that the instruction applies to.
For AArch32, some instructions can access NonSecure space from Secure,
so we still need to pass the state explicitly to do_ats_write().
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230809123706.1842548-5-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1acd00ef14101434cd99df0b01b32f62255423a9
https://github.com/qemu/qemu/commit/1acd00ef14101434cd99df0b01b32f62255423a9
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions
The AT instruction is UNDEFINED if the {NSE,NS} configuration is
invalid. Add a function to check this on all AT instructions that apply
to an EL lower than 3.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230809123706.1842548-6-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f6fc36deef6abcee406211f3e2f11ff894b87fa4
https://github.com/qemu/qemu/commit/f6fc36deef6abcee406211f3e2f11ff894b87fa4
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/trace-events
Log Message:
-----------
target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK
When FEAT_RME is implemented, these bits override the value of
CNT[VP]_CTL_EL0.IMASK in Realm and Root state. Move the IRQ state update
into a new gt_update_irq() function and test those bits every time we
recompute the IRQ state.
Since we're removing the IRQ state from some trace events, add a new
trace event for gt_update_irq().
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230809123706.1842548-7-jean-philippe@linaro.org
[PMM: only register change hook if not USER_ONLY and if TCG]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4b3520fd93cd49cc56dfcab45d90735cc2e35af7
https://github.com/qemu/qemu/commit/4b3520fd93cd49cc56dfcab45d90735cc2e35af7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/tcg/sme_helper.c
Log Message:
-----------
target/arm: Fix SME ST1Q
A typo, noted in the bug report, resulting in an
incorrect write offset.
Cc: qemu-stable@nongnu.org
Fixes: 7390e0e9ab8 ("target/arm: Implement SME LD1, ST1")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1833
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230818214255.146905-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cd1e4db73646006039f25879af3bff55b2295ff3
https://github.com/qemu/qemu/commit/cd1e4db73646006039f25879af3bff55b2295ff3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-08-22 (Tue, 22 Aug 2023)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Fix 64-bit SSRA
Typo applied byte-wise shift instead of double-word shift.
Cc: qemu-stable@nongnu.org
Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230821022025.397682-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3da4004c217148b1662a6fa6a6198b1c5df1adbb
https://github.com/qemu/qemu/commit/3da4004c217148b1662a6fa6a6198b1c5df1adbb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Log I/O write accesses to CSR registers
Various CSR registers have Read/Write fields. We might
want to see guest trying to change such registers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230821125959.28666-2-philmd@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 3a4b64c702d72844c9e58f72e8175e402627f240
https://github.com/qemu/qemu/commit/3a4b64c702d72844c9e58f72e8175e402627f240
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Remove duplicated disas_set_info assignment
Commit 228021f05e ("target/loongarch: Add core definition") sets
disas_set_info to loongarch_cpu_disas_set_info. Probably due to
a failed git-rebase, commit ca61e75071 ("target/loongarch: Add gdb
support") also sets it to the same value. Remove the duplication.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230821125959.28666-3-philmd@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 0b36072786c1972d4876ff799ef611be153dfaa3
https://github.com/qemu/qemu/commit/0b36072786c1972d4876ff799ef611be153dfaa3
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230817093121.1053890-11-gaosong@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230821125959.28666-4-philmd@linaro.org>
Commit: 146f2354b58aaa7b223e0394d889f83138911d9f
https://github.com/qemu/qemu/commit/146f2354b58aaa7b223e0394d889f83138911d9f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU
In preparation of introducing TYPE_LOONGARCH32_CPU, introduce
an abstract TYPE_LOONGARCH64_CPU.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230821125959.28666-5-philmd@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: e389358e569628dec1e3be6210621d64335f0c90
https://github.com/qemu/qemu/commit/e389358e569628dec1e3be6210621d64335f0c90
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init
Extract loongarch64 specific code from loongarch_cpu_class_init()
to a new loongarch64_cpu_class_init().
In preparation of supporting loongarch32 cores, rename these
functions using the '64' suffix.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230821125959.28666-6-philmd@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 19f82a4a6ae6da44fb8167bd3b415025d914f428
https://github.com/qemu/qemu/commit/19f82a4a6ae6da44fb8167bd3b415025d914f428
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: Add function to check current arch
Add is_la64 function to check if the current cpucfg[1].arch equals to
2(LA64).
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230817093121.1053890-2-gaosong@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230821125959.28666-7-philmd@linaro.org>
Commit: 6cbba3e9eb3e55353f23cbd567e508d01b7677e0
https://github.com/qemu/qemu/commit/6cbba3e9eb3e55353f23cbd567e508d01b7677e0
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: Add new object class for loongarch32 cpus
Add object class stub for future loongarch32 cpus.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230817093121.1053890-3-gaosong@loongson.cn>
[Rebased on TYPE_LOONGARCH64_CPU introduction]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230821125959.28666-8-philmd@linaro.org>
Commit: ebda3036e18b84d3e4280f05ac71ad462593e8ac
https://github.com/qemu/qemu/commit/ebda3036e18b84d3e4280f05ac71ad462593e8ac
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M configs/targets/loongarch64-softmmu.mak
A gdb-xml/loongarch-base32.xml
M target/loongarch/cpu.c
M target/loongarch/gdbstub.c
Log Message:
-----------
target/loongarch: Add GDB support for loongarch32 mode
GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230817093121.1053890-4-gaosong@loongson.cn>
[PMD: Rebased, set gdb_num_core_regs]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230821125959.28666-9-philmd@linaro.org>
Commit: e70bb6fb9afd0c560b3200b569d9d47239448c30
https://github.com/qemu/qemu/commit/e70bb6fb9afd0c560b3200b569d9d47239448c30
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/tlb_helper.c
Log Message:
-----------
target/loongarch: Support LoongArch32 TLB entry
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-2-philmd@linaro.org>
Commit: eece5764092063f3f7a091a8b42935e9cb1a37ff
https://github.com/qemu/qemu/commit/eece5764092063f3f7a091a8b42935e9cb1a37ff
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/tlb_helper.c
Log Message:
-----------
target/loongarch: Support LoongArch32 DMW
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-3-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-3-philmd@linaro.org>
Commit: 50fffcc49b0e68f53de5c1eaf21ec07819540d5a
https://github.com/qemu/qemu/commit/50fffcc49b0e68f53de5c1eaf21ec07819540d5a
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/tlb_helper.c
Log Message:
-----------
target/loongarch: Support LoongArch32 VPPN
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-4-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-4-philmd@linaro.org>
Commit: 3966582099b0c94b45a2ea0fd8afb0dcac8ad292
https://github.com/qemu/qemu/commit/3966582099b0c94b45a2ea0fd8afb0dcac8ad292
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/translate.c
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add LA64 & VA32 to DisasContext
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the
translator to reject doubleword instructions in LA32 mode for example.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-5-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-5-philmd@linaro.org>
Commit: 34423c01941928974f4854bc23a949789154fee7
https://github.com/qemu/qemu/commit/34423c01941928974f4854bc23a949789154fee7
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_fmemory.c.inc
M target/loongarch/insn_trans/trans_lsx.c.inc
M target/loongarch/insn_trans/trans_memory.c.inc
M target/loongarch/translate.c
Log Message:
-----------
target/loongarch: Extract make_address_x() helper
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230822071405.35386-6-philmd@linaro.org>
Commit: c5af6628f4be5d30800233e59ba3842ca19a12e6
https://github.com/qemu/qemu/commit/c5af6628f4be5d30800233e59ba3842ca19a12e6
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_atomic.c.inc
M target/loongarch/insn_trans/trans_branch.c.inc
M target/loongarch/insn_trans/trans_fmemory.c.inc
M target/loongarch/insn_trans/trans_lsx.c.inc
M target/loongarch/insn_trans/trans_memory.c.inc
M target/loongarch/translate.c
Log Message:
-----------
target/loongarch: Extract make_address_i() helper
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230822071405.35386-7-philmd@linaro.org>
Commit: 5a7ce25d0db050b8ddd62dc91c56f4af46e9cf3c
https://github.com/qemu/qemu/commit/5a7ce25d0db050b8ddd62dc91c56f4af46e9cf3c
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_arith.c.inc
M target/loongarch/insn_trans/trans_branch.c.inc
M target/loongarch/translate.c
Log Message:
-----------
target/loongarch: Extract make_address_pc() helper
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230822071405.35386-8-philmd@linaro.org>
Commit: 2f6478ffad1770a474460b7692588bae7f031da3
https://github.com/qemu/qemu/commit/2f6478ffad1770a474460b7692588bae7f031da3
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/gdbstub.c
M target/loongarch/op_helper.c
Log Message:
-----------
target/loongarch: Extract set_pc() helper
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230822071405.35386-9-philmd@linaro.org>
Commit: 7033c0e6dd36cd2bfa9a323c3a51ecb0b55903fc
https://github.com/qemu/qemu/commit/7033c0e6dd36cd2bfa9a323c3a51ecb0b55903fc
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/translate.c
Log Message:
-----------
target/loongarch: Truncate high 32 bits of address in VA32 mode
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-10-philmd@linaro.org>
Commit: 6496269d7e0b7f0d42499d7e4dde19c8b6c759c9
https://github.com/qemu/qemu/commit/6496269d7e0b7f0d42499d7e4dde19c8b6c759c9
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/translate.c
Log Message:
-----------
target/loongarch: Sign extend results in VA32 mode
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-1-philmd@linaro.org>
Commit: ec3a951891b00b2382bca29266c28f7ed021b0e5
https://github.com/qemu/qemu/commit/ec3a951891b00b2382bca29266c28f7ed021b0e5
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_arith.c.inc
M target/loongarch/insn_trans/trans_atomic.c.inc
M target/loongarch/insn_trans/trans_bit.c.inc
M target/loongarch/insn_trans/trans_branch.c.inc
M target/loongarch/insn_trans/trans_extra.c.inc
M target/loongarch/insn_trans/trans_farith.c.inc
M target/loongarch/insn_trans/trans_fcnv.c.inc
M target/loongarch/insn_trans/trans_fmemory.c.inc
M target/loongarch/insn_trans/trans_fmov.c.inc
M target/loongarch/insn_trans/trans_lsx.c.inc
M target/loongarch/insn_trans/trans_memory.c.inc
M target/loongarch/insn_trans/trans_privileged.c.inc
M target/loongarch/insn_trans/trans_shift.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add a check parameter to the TRANS macro
The default check parmeter is ALL.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-8-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-2-philmd@linaro.org>
Commit: c0c0461e3a06c8e854b8666a2610b1b619d0d1f8
https://github.com/qemu/qemu/commit/c0c0461e3a06c8e854b8666a2610b1b619d0d1f8
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_arith.c.inc
M target/loongarch/insn_trans/trans_atomic.c.inc
M target/loongarch/insn_trans/trans_bit.c.inc
M target/loongarch/insn_trans/trans_branch.c.inc
M target/loongarch/insn_trans/trans_extra.c.inc
M target/loongarch/insn_trans/trans_fmov.c.inc
M target/loongarch/insn_trans/trans_memory.c.inc
M target/loongarch/insn_trans/trans_shift.c.inc
M target/loongarch/translate.c
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add avail_64 to check la64-only instructions
The la32 instructions listed in Table 2 at
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions
Co-authored-by: Jiajie Chen <c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-3-philmd@linaro.org>
Commit: bb8710cf0a637c4af189675f234639ce9e90a27d
https://github.com/qemu/qemu/commit/bb8710cf0a637c4af189675f234639ce9e90a27d
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Add LoongArch32 cpu la132
Add LoongArch32 cpu la132.
Due to lack of public documentation of la132, it is currently a
synthetic LoongArch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie Chen <c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-10-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-4-philmd@linaro.org>
Commit: 3055122ff6d5d96e5394f495de3d512f1d6e94cf
https://github.com/qemu/qemu/commit/3055122ff6d5d96e5394f495de3d512f1d6e94cf
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch: Remove restriction of la464 cores in the virt machine
Allow virt machine to be used with la132 instead of la464.
Co-authored-by: Jiajie Chen <c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-11-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-5-philmd@linaro.org>
Commit: 95e2ca240739fc1a917102710d79a09f055f4d79
https://github.com/qemu/qemu/commit/95e2ca240739fc1a917102710d79a09f055f4d79
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_farith.c.inc
M target/loongarch/insn_trans/trans_fcmp.c.inc
M target/loongarch/insn_trans/trans_fcnv.c.inc
M target/loongarch/insn_trans/trans_fmemory.c.inc
M target/loongarch/insn_trans/trans_fmov.c.inc
M target/loongarch/translate.c
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-12-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-6-philmd@linaro.org>
Commit: 70c8d5eaaaf1b39b13af942a359d35a3aedd0803
https://github.com/qemu/qemu/commit/70c8d5eaaaf1b39b13af942a359d35a3aedd0803
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_privileged.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add avail_LSPW to check LSPW instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-13-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-7-philmd@linaro.org>
Commit: b139ddf1e944e395def788193232088cd6caf946
https://github.com/qemu/qemu/commit/b139ddf1e944e395def788193232088cd6caf946
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_atomic.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add avail_LAM to check atomic instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-14-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-8-philmd@linaro.org>
Commit: ebf288b410a38316dd6d6d15a9453222fff13d92
https://github.com/qemu/qemu/commit/ebf288b410a38316dd6d6d15a9453222fff13d92
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_lsx.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add avail_LSX to check LSX instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-15-gaosong@loongson.cn>
Message-Id: <20230822073026.35776-1-philmd@linaro.org>
Commit: a380c6f11fd9f1ca96f204c4ae26c79e483ede8a
https://github.com/qemu/qemu/commit/a380c6f11fd9f1ca96f204c4ae26c79e483ede8a
Author: Song Gao <gaosong@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M target/loongarch/insn_trans/trans_privileged.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add avail_IOCSR to check iocsr instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-16-gaosong@loongson.cn>
Message-Id: <20230822072219.35719-1-philmd@linaro.org>
Commit: 14f21f673a01cf3efa22a70256947fb9b6bbfdfa
https://github.com/qemu/qemu/commit/14f21f673a01cf3efa22a70256947fb9b6bbfdfa
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M hw/loongarch/virt.c
M target/loongarch/cpu.c
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: cpu: Implement get_arch_id callback
Implement the callback for getting the architecture-dependent CPU
ID, the cpu ID is physical id described in ACPI MADT table, this
will be used for cpu hotplug.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230824005007.2000525-1-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 2948c1fb6b8d806d92394ec358e6ed727e946df9
https://github.com/qemu/qemu/commit/2948c1fb6b8d806d92394ec358e6ed727e946df9
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M hw/intc/loongarch_pch_pic.c
Log Message:
-----------
hw/intc/loongarch_pch: fix edge triggered irq handling
For edge triggered irq, qemu_irq_pulse is used to inject irq. It will
set irq with high level and low level soon to simluate pulse irq.
For edge triggered irq, irq is injected and set as pending at rising
level, do not clear irq at lowering level. LoongArch pch interrupt will
clear irq for lowering level irq, there will be problem. ACPI ged deivce
is edge-triggered irq, it is used for cpu/memory hotplug.
This patch fixes memory hotplug issue on LoongArch virt machine.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230707091557.1474790-1-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 17ffe331a923c9015887917b27212ab39ff1d8ea
https://github.com/qemu/qemu/commit/17ffe331a923c9015887917b27212ab39ff1d8ea
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M gdb-xml/loongarch-fpu.xml
M target/loongarch/gdbstub.c
Log Message:
-----------
target/loongarch: Split fcc register to fcc0-7 in gdbstub
Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use
fcc0-7 instead of fcc register. This commit partially reverts commit
2f149c759 (`target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()`)
to match the behavior of GDB.
Note that it is a breaking change for GDB 13.0 or earlier, but it is
also required for GDB 13.1 or later to work.
Signed-off-by: Jiajie Chen <c@jia.je>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230808054315.3391465-1-c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 3f6bec4a9f7c159d32d49f6df5c2c3d587b953b9
https://github.com/qemu/qemu/commit/3f6bec4a9f7c159d32d49f6df5c2c3d587b953b9
Author: Jiajie Chen <c@jia.je>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M hw/loongarch/acpi-build.c
Log Message:
-----------
hw/loongarch: Fix ACPI processor id off-by-one error
In hw/acpi/aml-build.c:build_pptt() function, the code assumes that the
ACPI processor id equals to the cpu index, for example if we have 8
cpus, then the ACPI processor id should be in range 0-7.
However, in hw/loongarch/acpi-build.c:build_madt() function we broke the
assumption. If we have 8 cpus again, the ACPI processor id in MADT table
would be in range 1-8. It violates the following description taken from
ACPI spec 6.4 table 5.138:
If the processor structure represents an actual processor, this field
must match the value of ACPI processor ID field in the processor’s entry
in the MADT.
It will break the latest Linux 6.5-rc6 with the
following error message:
ACPI PPTT: PPTT table found, but unable to locate core 7 (8)
Invalid BIOS PPTT
Here 7 is the last cpu index, 8 is the ACPI processor id learned from
MADT.
With this patch, Linux can properly detect SMT threads when "-smp
8,sockets=1,cores=4,threads=2" is passed:
Thread(s) per core: 2
Core(s) per socket: 2
Socket(s): 2
The detection of number of sockets is still wrong, but that is out of
scope of the commit.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20230820105658.99123-2-c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 6030ef9d416d740eed9c0beaf7eef83d27eaf4eb
https://github.com/qemu/qemu/commit/6030ef9d416d740eed9c0beaf7eef83d27eaf4eb
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M configs/targets/loongarch64-softmmu.mak
A gdb-xml/loongarch-base32.xml
M gdb-xml/loongarch-fpu.xml
M hw/intc/loongarch_pch_pic.c
M hw/loongarch/acpi-build.c
M hw/loongarch/virt.c
M target/loongarch/cpu-csr.h
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/gdbstub.c
M target/loongarch/insn_trans/trans_arith.c.inc
M target/loongarch/insn_trans/trans_atomic.c.inc
M target/loongarch/insn_trans/trans_bit.c.inc
M target/loongarch/insn_trans/trans_branch.c.inc
M target/loongarch/insn_trans/trans_extra.c.inc
M target/loongarch/insn_trans/trans_farith.c.inc
M target/loongarch/insn_trans/trans_fcmp.c.inc
M target/loongarch/insn_trans/trans_fcnv.c.inc
M target/loongarch/insn_trans/trans_fmemory.c.inc
M target/loongarch/insn_trans/trans_fmov.c.inc
M target/loongarch/insn_trans/trans_lsx.c.inc
M target/loongarch/insn_trans/trans_memory.c.inc
M target/loongarch/insn_trans/trans_privileged.c.inc
M target/loongarch/insn_trans/trans_shift.c.inc
M target/loongarch/op_helper.c
M target/loongarch/tlb_helper.c
M target/loongarch/translate.c
M target/loongarch/translate.h
Log Message:
-----------
Merge tag 'pull-loongarch-20230824' of https://gitlab.com/gaosong/qemu into
staging
pull-loongarch-20230824
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# gpg: Signature made Thu 24 Aug 2023 05:04:03 EDT
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20230824' of https://gitlab.com/gaosong/qemu: (31 commits)
hw/loongarch: Fix ACPI processor id off-by-one error
target/loongarch: Split fcc register to fcc0-7 in gdbstub
hw/intc/loongarch_pch: fix edge triggered irq handling
target/loongarch: cpu: Implement get_arch_id callback
target/loongarch: Add avail_IOCSR to check iocsr instructions
target/loongarch: Add avail_LSX to check LSX instructions
target/loongarch: Add avail_LAM to check atomic instructions
target/loongarch: Add avail_LSPW to check LSPW instructions
target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions
hw/loongarch: Remove restriction of la464 cores in the virt machine
target/loongarch: Add LoongArch32 cpu la132
target/loongarch: Add avail_64 to check la64-only instructions
target/loongarch: Add a check parameter to the TRANS macro
target/loongarch: Sign extend results in VA32 mode
target/loongarch: Truncate high 32 bits of address in VA32 mode
target/loongarch: Extract set_pc() helper
target/loongarch: Extract make_address_pc() helper
target/loongarch: Extract make_address_i() helper
target/loongarch: Extract make_address_x() helper
target/loongarch: Add LA64 & VA32 to DisasContext
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4
https://github.com/qemu/qemu/commit/50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-08-24 (Thu, 24 Aug 2023)
Changed paths:
M accel/kvm/kvm-all.c
M hw/arm/virt.c
M hw/gpio/nrf51_gpio.c
M hw/mips/loongson3_virt.c
M hw/ppc/spapr.c
M include/hw/gpio/nrf51_gpio.h
M include/sysemu/kvm.h
M softmmu/qtest.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm.c
M target/arm/ptw.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/translate.c
M target/arm/trace-events
M target/i386/kvm/kvm.c
M target/mips/kvm.c
M target/mips/kvm_mips.h
M target/ppc/kvm.c
M target/riscv/kvm.c
M target/s390x/kvm/kvm.c
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
M tests/qtest/microbit-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20230824' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/gpio/nrf51: implement DETECT signal
* accel/kvm: Specify default IPA size for arm64
* ptw: refactor, fix some FEAT_RME bugs
* target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types
* target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK
* Fix SME ST1Q
* Fix 64-bit SSRA
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Aug 2023 05:27:33 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230824' of
https://git.linaro.org/people/pmaydell/qemu-arm: (35 commits)
target/arm: Fix 64-bit SSRA
target/arm: Fix SME ST1Q
target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK
target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions
target/arm: Pass security space rather than flag for AT instructions
target/arm: Skip granule protection checks for AT instructions
target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2*
target/arm/ptw: Load stage-2 tables from realm physical space
target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types
target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw
target/arm/ptw: Check for block descriptors at invalid levels
target/arm/ptw: Set attributes correctly for MMU disabled data accesses
target/arm/ptw: Drop S1Translate::out_secure
target/arm/ptw: Remove S1Translate::in_secure
target/arm/ptw: Remove last uses of ptw->in_secure
target/arm/ptw: Only fold in NSTable bit effects in Secure state
target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate()
target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate()
target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled()
target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and
get_phys_addr_disabled()
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/92e1d39f9897...50e7a40af372
- [Qemu-commits] [qemu/qemu] 8d6b2f: hw/gpio/nrf51: implement DETECT signal,
Alex Bennée <=