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[Qemu-commits] [qemu/qemu] b26368: target/mips: Rework cp0_timer with cl
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] b26368: target/mips: Rework cp0_timer with clock API |
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Date: |
Tue, 11 Jul 2023 01:32:45 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: b263688d236bc07266ce393fdce8c9b6bfd9d8d8
https://github.com/qemu/qemu/commit/b263688d236bc07266ce393fdce8c9b6bfd9d8d8
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/sysemu/cp0_timer.c
Log Message:
-----------
target/mips: Rework cp0_timer with clock API
Previous implementation of MIPS cp0_timer computes a
cp0_count_ns based on input clock. However rounding
error of cp0_count_ns can affect precision of cp0_timer.
Using clock API and a divider for cp0_timer, so we can
use clock_ns_to_ticks/clock_ns_to_ticks to avoid rounding
issue.
Also workaround the situation that in such handler flow:
count = read_c0_count()
write_c0_compare(count)
If timer had not progressed when compare was written, the
interrupt would trigger again.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230521110037.90049-1-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 03afdc28b3ffb9315f9612052b2b1c250370c344
https://github.com/qemu/qemu/commit/03afdc28b3ffb9315f9612052b2b1c250370c344
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/helper.h
M target/mips/internal.h
A target/mips/tcg/lcsr.decode
A target/mips/tcg/lcsr_translate.c
M target/mips/tcg/meson.build
M target/mips/tcg/op_helper.c
A target/mips/tcg/sysemu/lcsr_helper.c
M target/mips/tcg/sysemu/meson.build
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
Log Message:
-----------
target/mips: Implement Loongson CSR instructions
Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.
Unfortunately we don't have much document about those instructions,
bit fields of CPUCFG instructions and IOCSR registers can be found
at 3A4000's user manual, while instruction encodings can be found
at arch/mips/include/asm/mach-loongson64/loongson_regs.h from
Linux Kernel.
Our predefined CPUCFG bits are differ from actual 3A4000, since
we can't emulate all CPUCFG features present in 3A4000 for now,
we just enable bits for what we have in TCG.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com>
[JY: Fixed typo in ase_lcsr_available(),
retrict GEN_FALSE_TRANS]
[PMD: Fix meson's mips_softmmu_ss -> mips_system_ss,
restrict AddressSpace/MemoryRegion to SysEmu]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 99eff13120c8695f5d14b2edfe24739dd13b982f
https://github.com/qemu/qemu/commit/99eff13120c8695f5d14b2edfe24739dd13b982f
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M hw/mips/loongson3_virt.c
Log Message:
-----------
hw/mips/loongson3_virt: Relax CPU restrictions for TCG
After implemented CPUCFG and CSR, we are now able to boot Linux
kernel with Loongson-3A4000 CPU, so there is no point to restrict
CPU type to 3A1000 only, instead we just check for presence of
INSN_LOONGSON3A.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-3-jiaxun.yang@flygoat.com>
[JY: Check for cpu_type_supports_isa(INSN_LOONGSON3A)]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 59db94656d21e17a365af2e3b8f7e66b60e22810
https://github.com/qemu/qemu/commit/59db94656d21e17a365af2e3b8f7e66b60e22810
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips: Add emulation of MXU instructions for 32-bit load/store
Add support for emulating:
- S32LDDV and S32LDDVR
- S32STD and S32STDR
- S32STDV and S32STDVR
MXU instructions.
Add support for emulating MXU instructions with address register
post-modify counterparts:
- S32LDI and S32LDIR
- S32LDIV and S32LDIVR
- S32SDI and S32SDIR
- S32SDIV and S32SDIVR
Refactor support for emulating the S32LDD and S32LDDR instructions.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-2-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1980fa0a58ec8deada197e399a1c3c3b78c39e09
https://github.com/qemu/qemu/commit/1980fa0a58ec8deada197e399a1c3c3b78c39e09
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/cpu-defs.c.inc
Log Message:
-----------
target/mips: Add support of two XBurst CPUs
XBurstR1 - is the MIPS32R1 CPU which aims to cover all Ingenic SoCs
older than JZ4770 and some newer.
XBurstR2 - is the MIPS32R2 CPU which aims to cover all Ingenic SoCs
starting from to JZ4770.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-3-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 73c260c1a63cabe81676a28e957df10ea2395443
https://github.com/qemu/qemu/commit/73c260c1a63cabe81676a28e957df10ea2395443
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions
These instructions used to load from memory to GPR via indexed address
divided by base and index parts in GPR registers.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-4-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 199fc7d2790ce07f054fc2773dce8ae9e9fc3046
https://github.com/qemu/qemu/commit/199fc7d2790ce07f054fc2773dce8ae9e9fc3046
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions
These instructions used to multiply 2x32-bit GPR sources & accumulate
result into 64-bit pair of XRF registers.
These instructions stain HI/LO registers with the final result.
Their opcode is close to the MIPS32R1 MADD[U]/MSUB[U], so it have to
call decode_opc_special2_legacy when failing to find MXU opcode.
Moreover, it solves issue with reinventing MUL and malfunction
MULU/CLZ/CLO instructions.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-5-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4051f035e057b3ceb728573ac75ae45c44ecd16b
https://github.com/qemu/qemu/commit/4051f035e057b3ceb728573ac75ae45c44ecd16b
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q8SLT Q8SLTU instructions
These instructions are used to set bits depending on
comparison result in each byte respectively.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-6-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: fc34c76f365a110977234ddcaaba4198dcd4c397
https://github.com/qemu/qemu/commit/fc34c76f365a110977234ddcaaba4198dcd4c397
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions
These instructions were designed that they overwrite source
register during partial storing of result.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-7-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: ff7936f0093fab939bf4a8bff316b2cbd7f9f35f
https://github.com/qemu/qemu/commit/ff7936f0093fab939bf4a8bff316b2cbd7f9f35f
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns
These instructions are part of pool1, see the grand tree above
in the file. Q8ADD is part of pool1 too but belong to another
category of instructions, thus will be made in later patches.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-8-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: bf1df65f0ae9a13c8677b3e63d77f0bd6320846c
https://github.com/qemu/qemu/commit/bf1df65f0ae9a13c8677b3e63d77f0bd6320846c
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q8ADD instruction
This instruction is used to add/subtract quadruple
8-bit values to another quadruple in parallel.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-9-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f1e6547cfc5dbf4a3c397ca61dfcb83ba588b97c
https://github.com/qemu/qemu/commit/f1e6547cfc5dbf4a3c397ca61dfcb83ba588b97c
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns
These instructions are part of pool2, see the grand tree above
in the file.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-10-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 27dc0e289cf3e8f175a6e68921925302e1816fef
https://github.com/qemu/qemu/commit/27dc0e289cf3e8f175a6e68921925302e1816fef
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D16MULF D16MULE instructions
These instructions are part of pool3, see the grand tree above
in the file.
The instructions are close to D16MUL so common generation function
provided.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-11-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2ebc66e4156b5c176994c738a2a1ae70be5c611c
https://github.com/qemu/qemu/commit/2ebc66e4156b5c176994c738a2a1ae70be5c611c
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D16MACF D16MACE instructions
These instructions are close to D16MAC so common generation function
provided.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-12-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 15830fa2a196d18493415d1c9a6476949d3b9aa6
https://github.com/qemu/qemu/commit/15830fa2a196d18493415d1c9a6476949d3b9aa6
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D16MADL instruction
The instruction is similar to multiply and accumulate
but works with MXU registers set.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-13-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e722e680f737c8813bbb7cb7642830158cbebbdc
https://github.com/qemu/qemu/commit/e722e680f737c8813bbb7cb7642830158cbebbdc
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S16MAD instruction
The instruction is similar to multiply and accumulate
but works with MXU registers set.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-14-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a9bfd80bd48f43ce333e8668f1b26b5cfd2d1ac2
https://github.com/qemu/qemu/commit/a9bfd80bd48f43ce333e8668f1b26b5cfd2d1ac2
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q16ADD instruction
The instruction adds/subtracts four 16-bit packed in XRb and XRc.
Placing packed 16-bit results in XRa and XRd.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-15-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 9e51e0cd4bac9dd94f593d66497f635edd871d2e
https://github.com/qemu/qemu/commit/9e51e0cd4bac9dd94f593d66497f635edd871d2e
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D32ADD instruction
The instruction adds/subtracts two 32-bit values in XRb and XRc.
Placing results in XRa and XRd and updates carry bits for each
path in the MXU control register.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-16-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 98db7a585eb402579d2e5a7ec2b04fa22d12490a
https://github.com/qemu/qemu/commit/98db7a585eb402579d2e5a7ec2b04fa22d12490a
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions
These instructions are all dual 32-bit addition/subtraction in
various combinations. The instructions are grouped in pool12,
see the opcode organization in the file.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-17-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 513cfdae7a45a705f2fb2919ad95c82f66169c6e
https://github.com/qemu/qemu/commit/513cfdae7a45a705f2fb2919ad95c82f66169c6e
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D32ADDC instruction
The instruction adds two 32-bit values with respect
to corresponding carry flags in MXU_CR.
XRa += XRb + LeftCarry flag;
XRd += XRc + RightCarry flag;
Suddenly, it doesn't modify carry flags as a result of addition.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-18-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 6191a807fb865804c08b60b06393f25673f2fb64
https://github.com/qemu/qemu/commit/6191a807fb865804c08b60b06393f25673f2fb64
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions
These instructions are all dual 16-bit addition/subtraction in
various combinations. The instructions are grouped in pool13,
see the opcode organization in the file.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-19-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: eb79951ab638ba84ef424a8f7c0929cd4a5ea53d
https://github.com/qemu/qemu/commit/eb79951ab638ba84ef424a8f7c0929cd4a5ea53d
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions
These instructions are all dual 8-bit addition/subtraction in
various combinations. Most instructions are grouped in pool14,
see the opcode organization in the file.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-20-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 3f0e94c1348d29451db94fb0ebdbaf6fdda1c730
https://github.com/qemu/qemu/commit/3f0e94c1348d29451db94fb0ebdbaf6fdda1c730
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S8STD S8LDI S8SDI instructions
These instructions are all load/store a byte from memory
and put it into/get it from MXU register in various combinations.
I-suffix instructions modify the base address GPR by offset provided.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-21-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 968045b6c773fa61e48e4ca303f1acc9b54e4270
https://github.com/qemu/qemu/commit/968045b6c773fa61e48e4ca303f1acc9b54e4270
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions
These instructions are all load/store a halfword from memory
and put it into/get it from MXU register in various combinations.
I-suffix instructions modify the base address GPR by offset provided.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-22-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 29059e72b0ddf6cddc94cccd61e0ef30063ff5be
https://github.com/qemu/qemu/commit/29059e72b0ddf6cddc94cccd61e0ef30063ff5be
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns
These instructions are part of pool15, see the grand opcode organization
tree on top of the file.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-23-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 5925963476d65ce1a74651bbf48865977ff0c1b0
https://github.com/qemu/qemu/commit/5925963476d65ce1a74651bbf48865977ff0c1b0
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S32ALN S32LUI insns
These instructions are part of pool16, see the grand opcode organization
tree on top of the file.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-24-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f900da7691db16b534d5b4abcab2fdb29673aaa9
https://github.com/qemu/qemu/commit/f900da7691db16b534d5b4abcab2fdb29673aaa9
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D32SARL D32SARW instructions
These instructions are dual 32-bit arithmetic shift right and
pack LSBs to 2x 16-bit into a MXU register.
The difference is the shift amount source: immediate or GP reg.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-25-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f1fb103822bf69e261ca0902cfa75ea9aca2a8b4
https://github.com/qemu/qemu/commit/f1fb103822bf69e261ca0902cfa75ea9aca2a8b4
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D32SLL D32SLR D32SAR instructions
These instructions are same data shift in various directions, thus one
generation function is implemented for all three.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-26-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 52fe25d4452f8b5d8151ffe65f35da34b7fc237e
https://github.com/qemu/qemu/commit/52fe25d4452f8b5d8151ffe65f35da34b7fc237e
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions
These instructions are same data shift in various directions, thus one
generation function is implemented for all three.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-27-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 07c92895d758a9d2f77d555b92ae18149c14680d
https://github.com/qemu/qemu/commit/07c92895d758a9d2f77d555b92ae18149c14680d
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions
These instructions are counterparts for D32/Q16-SLL/SLR/SAR with
difference that the shift amount placed into GPR.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-28-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: d1b6ded4f72bab624e6366121443a5f0a856ceda
https://github.com/qemu/qemu/commit/d1b6ded4f72bab624e6366121443a5f0a856ceda
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions
These instructions are:
- single 32-bit
- dual 16-bit packed
- quad 8-bit packed
conditional moves.
They are grouped in pool20 in the source code.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-29-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7bb1206ab916bac96c029de850faf8d3bb1a08a2
https://github.com/qemu/qemu/commit/7bb1206ab916bac96c029de850faf8d3bb1a08a2
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q8MAC Q8MACSU instructions
These instructions do parallel quad 8-bit multiply and accumulate.
They are close to existing Q8MUL Q8MULSU so the generation
function modified to support all of them.
Also the patch fixes decoding of Q8MULSU according to tests on
hardware.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-30-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 68a48804cc0e84533f456a5a4bc48a1e96aeab99
https://github.com/qemu/qemu/commit/68a48804cc0e84533f456a5a4bc48a1e96aeab99
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q16SCOP instruction
The instruction is used to determine sign of four 16-bit
packed data in parallel.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-31-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b72e2b3a1fe42c7e0d086cd31bf52b0cd7780ca5
https://github.com/qemu/qemu/commit/b72e2b3a1fe42c7e0d086cd31bf52b0cd7780ca5
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q8MADL instruction
The instruction is used to parallel multiply and accumulate
four 8-bit data.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-32-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4b9680d3380525c75663c34071c039ae435ad285
https://github.com/qemu/qemu/commit/4b9680d3380525c75663c34071c039ae435ad285
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add S32SFL instruction
The instruction shuffles 8 bytes in two registers by
one of 4 predefined patterns.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-33-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 8aedfb64cdcfa60a077c66e802f6c65a419631de
https://github.com/qemu/qemu/commit/8aedfb64cdcfa60a077c66e802f6c65a419631de
Author: Siarhei Volkau <lis8215@gmail.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/tcg/mxu_translate.c
Log Message:
-----------
target/mips/mxu: Add Q8SAD instruction
The instruction implements SAD (sum-absolute-difference) operation which
is used in motion estimation algorithms. The instruction handles four
8-bit data in parallel.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-34-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: baf21eebc3e1026d21d94fdf8ca470050e49968f
https://github.com/qemu/qemu/commit/baf21eebc3e1026d21d94fdf8ca470050e49968f
Author: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/mips/cpu-defs.c.inc
Log Message:
-----------
target/mips: enable GINVx support for I6400 and I6500
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
so indicate that properly in CP0.Config5 register bits [16:15].
Cc: qemu-stable@nongnu.org
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e2b84ee41671edcaf975f88367f793e96e84b7c2
https://github.com/qemu/qemu/commit/e2b84ee41671edcaf975f88367f793e96e84b7c2
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/ide/pci.c
Log Message:
-----------
hw/ide/pci: Expose legacy interrupts as named GPIOs
Exposing the legacy IDE interrupts as GPIOs allows them to be connected in the
parent device through qdev_connect_gpio_out(), i.e. without accessing private
data of TYPE_PCI_IDE.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230531211043.41724-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 68eadfa2c6ee0ff357aaf674cc4cf0702393bcd1
https://github.com/qemu/qemu/commit/68eadfa2c6ee0ff357aaf674cc4cf0702393bcd1
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/ide/via.c
M hw/isa/vt82c686.c
Log Message:
-----------
hw/ide/via: Wire up IDE legacy interrupts in host device
Resolves circular depencency between IDE function and south bridge.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230531211043.41724-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4e5a20b6da9b1f6d2e9621ed7eb8b239560104ae
https://github.com/qemu/qemu/commit/4e5a20b6da9b1f6d2e9621ed7eb8b239560104ae
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/isa/vt82c686.c
M include/hw/isa/vt82c686.h
Log Message:
-----------
hw/isa/vt82c686: Remove via_isa_set_irq()
Now that via_isa_set_irq() is unused it can be removed.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230531211043.41724-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: bf0576edd71cf4f70352cc8de1cc914b419b36ff
https://github.com/qemu/qemu/commit/bf0576edd71cf4f70352cc8de1cc914b419b36ff
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/ide/cmd646.c
M hw/ide/pci.c
M hw/ide/piix.c
M hw/ide/sii3112.c
M hw/ide/via.c
Log Message:
-----------
hw/ide: Extract IDEBus assignment into bmdma_init()
Every invocation of bmdma_init() is followed by `d->bmdma[i].bus = &d->bus[i]`.
Resolve this redundancy by extracting it into bmdma_init().
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230531211043.41724-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 5fe24213f0c17c3050a7c9e95db459198e27de0e
https://github.com/qemu/qemu/commit/5fe24213f0c17c3050a7c9e95db459198e27de0e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/ide/cmd646.c
M hw/ide/pci.c
M hw/ide/piix.c
M hw/ide/sii3112.c
M hw/ide/via.c
M include/hw/ide/pci.h
Log Message:
-----------
hw/ide: Extract bmdma_status_writeb()
Every TYPE_PCI_IDE device performs the same not-so-trivial bit manipulation by
copy'n'paste code. Extract this into bmdma_status_writeb(), mirroring
bmdma_cmd_writeb().
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20230531211043.41724-6-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 17d6a4a32589c54d16ecb27c5116c2e4aca1b742
https://github.com/qemu/qemu/commit/17d6a4a32589c54d16ecb27c5116c2e4aca1b742
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/ide/pci.c
Log Message:
-----------
hw/ide/pci: Replace some magic numbers by constants
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20230531211043.41724-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 752dfff5ecf35a38145c2dfbb842224177fd1afd
https://github.com/qemu/qemu/commit/752dfff5ecf35a38145c2dfbb842224177fd1afd
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/ide/piix.c
Log Message:
-----------
hw/ide/piix: Move registration of VMStateDescription to DeviceClass
The modern, declarative way to set up VM state handling is to assign to
DeviceClass::vmsd attribute.
There shouldn't be any change in behavior since dc->vmsd causes
vmstate_register_with_alias_id() to be called on the instance during
the instance init phase. vmstate_register() was also called during the
instance init phase which forwards to vmstate_register_with_alias_id()
internally. Checking the migration schema before and after this patch confirms:
before:
> qemu-system-x86_64 -S
> qemu > migrate -d exec:cat>before.mig
after:
> qemu-system-x86_64 -S
> qemu > migrate -d exec:cat>after.mig
> analyze-migration.py -d desc -f before.mig > before.json
> analyze-migration.py -d desc -f after.mig > after.json
> diff before.json after.json
-> empty
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20230531211043.41724-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 154e3b61ac9cfab9639e6d6207a96fff017040fe
https://github.com/qemu/qemu/commit/154e3b61ac9cfab9639e6d6207a96fff017040fe
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-11 (Tue, 11 Jul 2023)
Changed paths:
M hw/ide/cmd646.c
M hw/ide/pci.c
M hw/ide/piix.c
M hw/ide/sii3112.c
M hw/ide/via.c
M hw/isa/vt82c686.c
M hw/mips/loongson3_virt.c
M include/hw/ide/pci.h
M include/hw/isa/vt82c686.h
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/helper.h
M target/mips/internal.h
M target/mips/sysemu/cp0_timer.c
A target/mips/tcg/lcsr.decode
A target/mips/tcg/lcsr_translate.c
M target/mips/tcg/meson.build
M target/mips/tcg/mxu_translate.c
M target/mips/tcg/op_helper.c
A target/mips/tcg/sysemu/lcsr_helper.c
M target/mips/tcg/sysemu/meson.build
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/tcg/translate.c
M target/mips/tcg/translate.h
Log Message:
-----------
Merge tag 'mips-20230710' of https://github.com/philmd/qemu into staging
MIPS patches queue
- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
- Implement Loongson CSR instructions (Jiaxun)
- Implement Ingenic MXU ASE v1 rev2 (Siarhei)
- Enable GINVx support for I6400 and I6500 cores (Marcin)
- Generalize PCI IDE controller models (Bernhard)
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[full]
* tag 'mips-20230710' of https://github.com/philmd/qemu: (44 commits)
hw/ide/piix: Move registration of VMStateDescription to DeviceClass
hw/ide/pci: Replace some magic numbers by constants
hw/ide: Extract bmdma_status_writeb()
hw/ide: Extract IDEBus assignment into bmdma_init()
hw/isa/vt82c686: Remove via_isa_set_irq()
hw/ide/via: Wire up IDE legacy interrupts in host device
hw/ide/pci: Expose legacy interrupts as named GPIOs
target/mips: enable GINVx support for I6400 and I6500
target/mips/mxu: Add Q8SAD instruction
target/mips/mxu: Add S32SFL instruction
target/mips/mxu: Add Q8MADL instruction
target/mips/mxu: Add Q16SCOP instruction
target/mips/mxu: Add Q8MAC Q8MACSU instructions
target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions
target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions
target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions
target/mips/mxu: Add D32SLL D32SLR D32SAR instructions
target/mips/mxu: Add D32SARL D32SARW instructions
target/mips/mxu: Add S32ALN S32LUI insns
target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/adc97c4b808b...154e3b61ac9c