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[Qemu-commits] [qemu/qemu] 587f8b: target/arm: Add raw_writes ops for re
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 587f8b: target/arm: Add raw_writes ops for register whose ... |
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Date: |
Thu, 06 Jul 2023 08:19:51 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 587f8b333c8c66e8f3e54fe30ea8e88cc7d29d21
https://github.com/qemu/qemu/commit/587f8b333c8c66e8f3e54fe30ea8e88cc7d29d21
Author: Eric Auger <eric.auger@redhat.com>
Date: 2023-07-04 (Tue, 04 Jul 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add raw_writes ops for register whose write induce TLB maintenance
Some registers whose 'cooked' writefns induce TLB maintenance do
not have raw_writefn ops defined. If only the writefn ops is set
(ie. no raw_writefn is provided), it is assumed the cooked also
work as the raw one. For those registers it is not obvious the
tlb_flush works on KVM mode so better/safer setting the raw write.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 62c2b8760b8ec9316ea4f5f4c2ce2fdaed1359ee
https://github.com/qemu/qemu/commit/62c2b8760b8ec9316ea4f5f4c2ce2fdaed1359ee
Author: Yuquan Wang <wangyuquan1236@phytium.com.cn>
Date: 2023-07-04 (Tue, 04 Jul 2023)
Changed paths:
M docs/system/arm/sbsa.rst
M hw/arm/Kconfig
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: use XHCI to replace EHCI
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
We bump the platform version to 0.3 with this change. Although the
hardware at the USB controller address changes, the firmware and
Linux can both cope with this -- on an older non-XHCI-aware
firmware/kernel setup the probe routine simply fails and the guest
proceeds without any USB. (This isn't a loss of functionality,
because the old USB controller never worked in the first place.) So
we can call this a backwards-compatible change and only bump the
minor version.
Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn
[PMM: tweaked commit message; add line to docs about what
changes in platform version 0.3]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3dc2afeab2964b54848715b913b6c605f36be3e1
https://github.com/qemu/qemu/commit/3dc2afeab2964b54848715b913b6c605f36be3e1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M tests/tcg/aarch64/Makefile.target
M tests/tcg/aarch64/sysregs.c
Log Message:
-----------
tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and
id_aa64smfr0_el1
Some assemblers will complain about attempts to access
id_aa64zfr0_el1 and id_aa64smfr0_el1 by name if the test
binary isn't built for the right processor type:
/tmp/ccASXpLo.s:782: Error: selected processor does not support system
register name 'id_aa64zfr0_el1'
/tmp/ccASXpLo.s:829: Error: selected processor does not support system
register name 'id_aa64smfr0_el1'
However, these registers are in the ID space and are guaranteed to
read-as-zero on older CPUs, so the access is both safe and sensible.
Switch to using the S syntax, as we already do for ID_AA64ISAR2_EL1
and ID_AA64MMFR2_EL1. This allows us to drop the HAS_ARMV9_SME check
and the makefile machinery to adjust the CFLAGS for this test, so we
don't rely on having a sufficiently new compiler to be able to check
these registers.
This means we're actually testing the SME ID register: no released
GCC yet recognizes -march=armv9-a+sme, so that was always skipped.
It also avoids a future problem if we try to switch the "do we have
SME support in the toolchain" check from "in the compiler" to "in the
assembler" (at which point we would otherwise run into the above
errors).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a9d8407016ab9d2423a00d767cad90968ba21f99
https://github.com/qemu/qemu/commit/a9d8407016ab9d2423a00d767cad90968ba21f99
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Avoid splitting Zregs across lines in dump
Allow the line length to extend to 548 columns. While annoyingly wide,
it's still less confusing than the continuations we print. Also, the
default VL used by Linux (and max for A64FX) uses only 140 columns.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 270bea47a23b286c2ab3a76f720991c59680b8e6
https://github.com/qemu/qemu/commit/270bea47a23b286c2ab3a76f720991c59680b8e6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Dump ZA[] when active
Always print each matrix row whole, one per line, so that we
get the entire matrix in the proper shape.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1f51573f7925b80e79a29f87c7d9d6ead60960c0
https://github.com/qemu/qemu/commit/1f51573f7925b80e79a29f87c7d9d6ead60960c0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/arm/tcg/translate-sme.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/sme-outprod1.c
Log Message:
-----------
target/arm: Fix SME full tile indexing
For the outer product set of insns, which take an entire matrix
tile as output, the argument is not a combined tile+column.
Therefore using get_tile_rowcol was incorrect, as we extracted
the tile number from itself.
The test case relies only on assembler support for SME, since
no release of GCC recognizes -march=armv9-a+sme yet.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: dropped now-unneeded changes to sysregs CFLAGS]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9719f125b803f4e0fda834cd74a60dfa4ca398e2
https://github.com/qemu/qemu/commit/9719f125b803f4e0fda834cd74a60dfa4ca398e2
Author: John Högberg <john.hogberg@ericsson.com>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/arm/cpu.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle IC IVAU to improve compatibility with JITs
Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, requiring an instruction synchronization
barrier on every core that will execute the new code, and on many
models also the explicit use of cache management instructions.
While this is required to make JITs work on actual hardware, QEMU
has gotten away with not handling this since it does not emulate
caches, and unconditionally invalidates code whenever the softmmu
or the user-mode page protection logic detects that code has been
modified.
Unfortunately the latter does not work in the face of dual-mapped
code (a common W^X workaround), where one page is executable and
the other is writable: user-mode has no way to connect one with the
other as that is only known to the kernel and the emulated
application.
This commit works around the issue by telling software that
instruction cache invalidation is required by clearing the
CPR_EL0.DIC flag (regardless of whether the emulated processor
needs it), and then invalidating code in IC IVAU instructions.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: John Högberg <john.hogberg@ericsson.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht
[PMM: removed unnecessary AArch64 feature check; moved
"clear CTR_EL1.DIC" code up a bit so it's not in the middle
of the vfp/neon related tests]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b52aa865259f8e26125333a178c0a9364d8ae4da
https://github.com/qemu/qemu/commit/b52aa865259f8e26125333a178c0a9364d8ae4da
Author: Vikram Garhwal <vikram.garhwal@amd.com>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M tests/qtest/xlnx-canfd-test.c
Log Message:
-----------
tests/qtest: xlnx-canfd-test: Fix code coverity issues
Following are done to fix the coverity issues:
1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN)
2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE)
3. Replace rand() in generate_random_data() with g_rand_int()
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 893ca916c0b9432d46fc16f84c8d3b605a58c843
https://github.com/qemu/qemu/commit/893ca916c0b9432d46fc16f84c8d3b605a58c843
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/arm/gdbstub.c
Log Message:
-----------
target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
This code is only relevant when TCG is present in the build. Building
with --disable-tcg --enable-xen on an x86 host we get:
$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg
--enable-xen
$ make -j$(nproc)
...
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr':
../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr'
../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr'
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function
`arm_gdb_get_m_systemreg':
../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control'
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230628164821.16771-1-farosas@suse.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9057e5f7c9550d1ea419ce838ae6d0df96fb062e
https://github.com/qemu/qemu/commit/9057e5f7c9550d1ea419ce838ae6d0df96fb062e
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M hw/misc/allwinner-sramc.c
Log Message:
-----------
hw: arm: allwinner-sramc: Set class_size
AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
advertised accordingly.
Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for
R40")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ad18376b90c8101b8eed2fd571bdbb94636ccc2e
https://github.com/qemu/qemu/commit/ad18376b90c8101b8eed2fd571bdbb94636ccc2e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/xtensa/exc_helper.c
Log Message:
-----------
target/xtensa: Assert that interrupt level is within bounds
In handle_interrupt() we use level as an index into the interrupt_vector[]
array. This is safe because we have checked it against env->config->nlevel,
but Coverity can't see that (and it is only true because each CPU config
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
complains about a possible array overrun (CID 1507131)
Add an assert() which will make Coverity happy and catch the unlikely
case of a mis-set XCHAL_NUM_INTLEVELS in future.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org
Commit: 7d8c283e10dd818457e7c6a0f729fb03857253ac
https://github.com/qemu/qemu/commit/7d8c283e10dd818457e7c6a0f729fb03857253ac
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Suppress more TCG unimplemented features in ID registers
We already squash the ID register field for FEAT_SPE (the Statistical
Profiling Extension) because TCG does not implement it and if we
advertise it to the guest the guest will crash trying to look at
non-existent system registers. Do the same for some other features
which a real hardware Neoverse-V1 implements but which TCG doesn't:
* FEAT_TRF (Self-hosted Trace Extension)
* Trace Macrocell system register access
* Memory mapped trace
* FEAT_AMU (Activity Monitors Extension)
* FEAT_MPAM (Memory Partitioning and Monitoring Extension)
* FEAT_NV (Nested Virtualization)
Most of these, like FEAT_SPE, are "introspection/trace" type features
which QEMU is unlikely to ever implement. The odd-one-out here is
FEAT_NV -- we could implement that and at some point we probably
will.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230704130647.2842917-2-peter.maydell@linaro.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c74138c6c040b62e941326a4fbb25a93fdd35b72
https://github.com/qemu/qemu/commit/c74138c6c040b62e941326a4fbb25a93fdd35b72
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Define neoverse-v1
Now that we have implemented support for FEAT_LSE2, we can define
a CPU model for the Neoverse-V1, and enable it for the virt and
sbsa-ref boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230704130647.2842917-3-peter.maydell@linaro.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c41077235168140cdd4a34fce9bd95c3d30efe9c
https://github.com/qemu/qemu/commit/c41077235168140cdd4a34fce9bd95c3d30efe9c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case
If you build QEMU with the clang sanitizer enabled, you can see it
fire when running the arm-cpu-features test:
$ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64
./build/arm-clang/tests/qtest/arm-cpu-features
[...]
../../target/arm/cpu64.c:125:19: runtime error: shift exponent 64 is too large
for 64-bit type 'unsigned long long'
[...]
This happens because the user can specify some incorrect SVE
properties that result in our calculating a max_vq of 0. We catch
this and error out, but before we do that we calculate
vq_mask = MAKE_64BIT_MASK(0, max_vq);$
and the MAKE_64BIT_MASK() call is only valid for lengths that are
greater than zero, so we hit the undefined behaviour.
Change the logic so that if max_vq is 0 we specifically set vq_mask
to 0 without going via MAKE_64BIT_MASK(). This lets us drop the
max_vq check from the error-exit logic, because if max_vq is 0 then
vq_map must now be 0.
The UB only happens in the case where the user passed us an incorrect
set of SVE properties, so it's not a big problem in practice.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230704154332.3014896-1-peter.maydell@linaro.org
Commit: 822cb97cefe2416ce61fe8007ad69904bbe24502
https://github.com/qemu/qemu/commit/822cb97cefe2416ce61fe8007ad69904bbe24502
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-06 (Thu, 06 Jul 2023)
Changed paths:
M docs/system/arm/sbsa.rst
M docs/system/arm/virt.rst
M hw/arm/Kconfig
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M hw/misc/allwinner-sramc.c
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/gdbstub.c
M target/arm/helper.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/translate-sme.c
M target/xtensa/exc_helper.c
M tests/qtest/xlnx-canfd-test.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/sme-outprod1.c
M tests/tcg/aarch64/sysregs.c
Log Message:
-----------
Merge tag 'pull-target-arm-20230706' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Add raw_writes ops for register whose write induce TLB maintenance
* hw/arm/sbsa-ref: use XHCI to replace EHCI
* Avoid splitting Zregs across lines in dump
* Dump ZA[] when active
* Fix SME full tile indexing
* Handle IC IVAU to improve compatibility with JITs
* xlnx-canfd-test: Fix code coverity issues
* gdbstub: Guard M-profile code with CONFIG_TCG
* allwinner-sramc: Set class_size
* target/xtensa: Assert that interrupt level is within bounds
* Avoid over-length shift in arm_cpu_sve_finalize() error case
* Define new 'neoverse-v1' CPU type
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# lqFyvEIYNJZ9klf7XKnX2w==
# =/MkB
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 06 Jul 2023 02:23:13 PM BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20230706' of
https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case
target/arm: Define neoverse-v1
target/arm: Suppress more TCG unimplemented features in ID registers
target/xtensa: Assert that interrupt level is within bounds
hw: arm: allwinner-sramc: Set class_size
target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
tests/qtest: xlnx-canfd-test: Fix code coverity issues
target/arm: Handle IC IVAU to improve compatibility with JITs
target/arm: Fix SME full tile indexing
target/arm: Dump ZA[] when active
target/arm: Avoid splitting Zregs across lines in dump
tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and
id_aa64smfr0_el1
hw/arm/sbsa-ref: use XHCI to replace EHCI
target/arm: Add raw_writes ops for register whose write induce TLB maintenance
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/0618e72d64e4...822cb97cefe2