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[Qemu-commits] [qemu/qemu] 587f8b: target/arm: Add raw_writes ops for re

From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 587f8b: target/arm: Add raw_writes ops for register whose ...
Date: Tue, 04 Jul 2023 09:41:13 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 587f8b333c8c66e8f3e54fe30ea8e88cc7d29d21
      
https://github.com/qemu/qemu/commit/587f8b333c8c66e8f3e54fe30ea8e88cc7d29d21
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add raw_writes ops for register whose write induce TLB maintenance

Some registers whose 'cooked' writefns induce TLB maintenance do
not have raw_writefn ops defined. If only the writefn ops is set
(ie. no raw_writefn is provided), it is assumed the cooked also
work as the raw one. For those registers it is not obvious the
tlb_flush works on KVM mode so better/safer setting the raw write.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 62c2b8760b8ec9316ea4f5f4c2ce2fdaed1359ee
      
https://github.com/qemu/qemu/commit/62c2b8760b8ec9316ea4f5f4c2ce2fdaed1359ee
  Author: Yuquan Wang <wangyuquan1236@phytium.com.cn>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M docs/system/arm/sbsa.rst
    M hw/arm/Kconfig
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm/sbsa-ref: use XHCI to replace EHCI

The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.

We bump the platform version to 0.3 with this change.  Although the
hardware at the USB controller address changes, the firmware and
Linux can both cope with this -- on an older non-XHCI-aware
firmware/kernel setup the probe routine simply fails and the guest
proceeds without any USB.  (This isn't a loss of functionality,
because the old USB controller never worked in the first place.) So
we can call this a backwards-compatible change and only bump the
minor version.

Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn
[PMM: tweaked commit message; add line to docs about what
 changes in platform version 0.3]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: aef771af7abe93aef5323c28709079d880fcb796
      
https://github.com/qemu/qemu/commit/aef771af7abe93aef5323c28709079d880fcb796
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Avoid splitting Zregs across lines in dump

Allow the line length to extend to 548 columns.  While annoyingly wide,
it's still less confusing than the continuations we print.  Also, the
default VL used by Linux (and max for A64FX) uses only 140 columns.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dfa27d1643a51699ed6f9fe984bfedc4bdbc86f1
      
https://github.com/qemu/qemu/commit/dfa27d1643a51699ed6f9fe984bfedc4bdbc86f1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Dump ZA[] when active

Always print each matrix row whole, one per line, so that we
get the entire matrix in the proper shape.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fc34f4cae09d3348bc835c579baf306b15012e2c
      
https://github.com/qemu/qemu/commit/fc34f4cae09d3348bc835c579baf306b15012e2c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M target/arm/tcg/translate-sme.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/sme-outprod1.c

  Log Message:
  -----------
  target/arm: Fix SME full tile indexing

For the outer product set of insns, which take an entire matrix
tile as output, the argument is not a combined tile+column.
Therefore using get_tile_rowcol was incorrect, as we extracted
the tile number from itself.

The test case relies only on assembler support for SME, since
no release of GCC recognizes -march=armv9-a+sme yet.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 286a6586a660425d09eed6e0fa46c3607fd7831b
      
https://github.com/qemu/qemu/commit/286a6586a660425d09eed6e0fa46c3607fd7831b
  Author: John Högberg <john.hogberg@ericsson.com>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Handle IC IVAU to improve compatibility with JITs

Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, requiring an instruction synchronization
barrier on every core that will execute the new code, and on many
models also the explicit use of cache management instructions.

While this is required to make JITs work on actual hardware, QEMU
has gotten away with not handling this since it does not emulate
caches, and unconditionally invalidates code whenever the softmmu
or the user-mode page protection logic detects that code has been
modified.

Unfortunately the latter does not work in the face of dual-mapped
code (a common W^X workaround), where one page is executable and
the other is writable: user-mode has no way to connect one with the
other as that is only known to the kernel and the emulated
application.

This commit works around the issue by telling software that
instruction cache invalidation is required by clearing the
CPR_EL0.DIC flag (regardless of whether the emulated processor
needs it), and then invalidating code in IC IVAU instructions.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034

Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: John Högberg <john.hogberg@ericsson.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht
[PMM: removed unnecessary AArch64 feature check; moved
 "clear CTR_EL1.DIC" code up a bit so it's not in the middle
 of the vfp/neon related tests]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a3b3b92d1f6132d8cb00d21f03a1909f422aa5c5
      
https://github.com/qemu/qemu/commit/a3b3b92d1f6132d8cb00d21f03a1909f422aa5c5
  Author: John Högberg <john.hogberg@ericsson.com>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/icivau.c

  Log Message:
  -----------
  tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code

https://gitlab.com/qemu-project/qemu/-/issues/1034

Signed-off-by: John Högberg <john.hogberg@ericsson.com>
Message-id: 168778890374.24232.3402138851538068785-2@git.sr.ht
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed typo in comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3d7552aed48b14d7fc6f68a6f7af5cbb5529eb35
      
https://github.com/qemu/qemu/commit/3d7552aed48b14d7fc6f68a6f7af5cbb5529eb35
  Author: Vikram Garhwal <vikram.garhwal@amd.com>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M tests/qtest/xlnx-canfd-test.c

  Log Message:
  -----------
  tests/qtest: xlnx-canfd-test: Fix code coverity issues

Following are done to fix the coverity issues:
1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN)
2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE)
3. Replace rand() in generate_random_data() with g_rand_int()

Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ef37898d275305513bc0ccbdeeba2adbe620a510
      
https://github.com/qemu/qemu/commit/ef37898d275305513bc0ccbdeeba2adbe620a510
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M target/arm/gdbstub.c

  Log Message:
  -----------
  target/arm: gdbstub: Guard M-profile code with CONFIG_TCG

This code is only relevant when TCG is present in the build. Building
with --disable-tcg --enable-xen on an x86 host we get:

$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg 
--enable-xen
$ make -j$(nproc)
...
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr':
 ../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr'
 ../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr'

libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function 
`arm_gdb_get_m_systemreg':
../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control'

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230628164821.16771-1-farosas@suse.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7812aaa191eb2f2e3dc13507a4708e0c85017495
      
https://github.com/qemu/qemu/commit/7812aaa191eb2f2e3dc13507a4708e0c85017495
  Author: Akihiko Odaki <akihiko.odaki@daynix.com>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M hw/misc/allwinner-sramc.c

  Log Message:
  -----------
  hw: arm: allwinner-sramc: Set class_size

AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
advertised accordingly.

Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for 
R40")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 86a78272f094857b4eda79d721c116e93942aa9a
      
https://github.com/qemu/qemu/commit/86a78272f094857b4eda79d721c116e93942aa9a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M target/xtensa/exc_helper.c

  Log Message:
  -----------
  target/xtensa: Assert that interrupt level is within bounds

In handle_interrupt() we use level as an index into the interrupt_vector[]
array. This is safe because we have checked it against env->config->nlevel,
but Coverity can't see that (and it is only true because each CPU config
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
complains about a possible array overrun (CID 1507131)

Add an assert() which will make Coverity happy and catch the unlikely
case of a mis-set XCHAL_NUM_INTLEVELS in future.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org


  Commit: c21eae1ccc782440f320accb6f90c66cb8f45ee9
      
https://github.com/qemu/qemu/commit/c21eae1ccc782440f320accb6f90c66cb8f45ee9
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M block/blkio.c

  Log Message:
  -----------
  block/blkio: fix module_block.py parsing

When QEMU is built with --enable-modules, the module_block.py script
parses block/*.c to find block drivers that are built as modules. The
script generates a table of block drivers called block_driver_modules[].
This table is used for block driver module loading.

The blkio.c driver uses macros to define its BlockDriver structs. This
was done to avoid code duplication but the module_block.py script is
unable to parse the macro. The result is that libblkio-based block
drivers can be built as modules but will not be found at runtime.

One fix is to make the module_block.py script or build system fancier so
it can parse C macros (e.g. by parsing the preprocessed source code). I
chose not to do this because it raises the complexity of the build,
making future issues harder to debug.

Keep things simple: use the macro to avoid duplicating BlockDriver
function pointers but define .format_name and .protocol_name manually
for each BlockDriver. This way the module_block.py is able to parse the
code.

Also get rid of the block driver name macros (e.g. DRIVER_IO_URING)
because module_block.py cannot parse them either.

Fixes: fd66dbd424f5 ("blkio: add libblkio block driver")
Reported-by: Qing Wang <qinwang@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-id: 20230704123436.187761-1-stefanha@redhat.com
Cc: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: 0618e72d64e434dd6f1bc38b107670474c49fb86
      
https://github.com/qemu/qemu/commit/0618e72d64e434dd6f1bc38b107670474c49fb86
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M block/blkio.c

  Log Message:
  -----------
  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into 
staging

Pull request

Fix --enable-modules with the blkio block driver.

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# gpg:                using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full]
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>" [full]

* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
  block/blkio: fix module_block.py parsing

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 726e2ade360f918ab41b5c2231b51ec6505e268c
      
https://github.com/qemu/qemu/commit/726e2ade360f918ab41b5c2231b51ec6505e268c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-07-04 (Tue, 04 Jul 2023)

  Changed paths:
    M docs/system/arm/sbsa.rst
    M hw/arm/Kconfig
    M hw/arm/sbsa-ref.c
    M hw/misc/allwinner-sramc.c
    M target/arm/cpu.c
    M target/arm/gdbstub.c
    M target/arm/helper.c
    M target/arm/tcg/translate-sme.c
    M target/xtensa/exc_helper.c
    M tests/qtest/xlnx-canfd-test.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/icivau.c
    A tests/tcg/aarch64/sme-outprod1.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230704' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Add raw_writes ops for register whose write induce TLB maintenance
 * hw/arm/sbsa-ref: use XHCI to replace EHCI
 * Avoid splitting Zregs across lines in dump
 * Dump ZA[] when active
 * Fix SME full tile indexing
 * Handle IC IVAU to improve compatibility with JITs
 * xlnx-canfd-test: Fix code coverity issues
 * gdbstub: Guard M-profile code with CONFIG_TCG
 * allwinner-sramc: Set class_size
 * target/xtensa: Assert that interrupt level is within bounds

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# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20230704' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  target/xtensa: Assert that interrupt level is within bounds
  hw: arm: allwinner-sramc: Set class_size
  target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
  tests/qtest: xlnx-canfd-test: Fix code coverity issues
  tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code
  target/arm: Handle IC IVAU to improve compatibility with JITs
  target/arm: Fix SME full tile indexing
  target/arm: Dump ZA[] when active
  target/arm: Avoid splitting Zregs across lines in dump
  hw/arm/sbsa-ref: use XHCI to replace EHCI
  target/arm: Add raw_writes ops for register whose write induce TLB maintenance

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/2a6ae6915454...726e2ade360f
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