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[Qemu-commits] [qemu/qemu] 148fad: Hexagon (target/hexagon) Add support
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 148fad: Hexagon (target/hexagon) Add support for v68/v69/v... |
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Date: |
Sat, 13 May 2023 01:41:47 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 148fad4e14a97e2a4fc0b704596c55feab6c4b56
https://github.com/qemu/qemu/commit/148fad4e14a97e2a4fc0b704596c55feab6c4b56
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M configure
M linux-user/hexagon/target_elf.h
M target/hexagon/README
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M tests/tcg/hexagon/Makefile.target
M tests/tcg/hexagon/misc.c
Log Message:
-----------
Hexagon (target/hexagon) Add support for v68/v69/v71/v73
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com>
Commit: f43c017cdcb3f1b75c1cd9225057367af2763bcb
https://github.com/qemu/qemu/commit/f43c017cdcb3f1b75c1cd9225057367af2763bcb
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg.h
M target/hexagon/imported/encode_pp.def
M target/hexagon/imported/ldst.idef
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Add v68 scalar instructions
The following instructions are added
L2_loadw_aq
L4_loadd_aq
R6_release_at_vi
R6_release_st_vi
S2_storew_rl_at_vi
S4_stored_rl_at_vi
S2_storew_rl_st_vi
S4_stored_rl_st_vi
The release instructions are nop's in qemu. The others behave as
loads/stores.
The encodings for these instructions changed some "don't care" bits
L2_loadw_locked
L4_loadd_locked
S2_storew_locked
S4_stored_locked
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-3-tsimpson@quicinc.com>
Commit: 5ff06ff4fe51398bd7ca9419ed79684b6259d6fd
https://github.com/qemu/qemu/commit/5ff06ff4fe51398bd7ca9419ed79684b6259d6fd
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v68_scalar.c
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v68 scalar tests
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-4-tsimpson@quicinc.com>
Commit: 29ebaf696e8bec78a212c017c8b2e3229ffd0c6e
https://github.com/qemu/qemu/commit/29ebaf696e8bec78a212c017c8b2e3229ffd0c6e
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/imported/mmvec/encode_ext.def
M target/hexagon/imported/mmvec/ext.idef
M target/hexagon/mmvec/macros.h
Log Message:
-----------
Hexagon (target/hexagon) Add v68 HVX instructions
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-5-tsimpson@quicinc.com>
Commit: 65e9cbe8ee9f9a0d04aee1a6770e66b372a9e125
https://github.com/qemu/qemu/commit/65e9cbe8ee9f9a0d04aee1a6770e66b372a9e125
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v68_hvx.c
A tests/tcg/hexagon/v6mpy_ref.c.inc
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v68 HVX tests
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-6-tsimpson@quicinc.com>
Commit: 99ee997ce20962e89f3784b92ccacbf0afaf5199
https://github.com/qemu/qemu/commit/99ee997ce20962e89f3784b92ccacbf0afaf5199
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_tcg_hvx.h
M target/hexagon/imported/mmvec/encode_ext.def
M target/hexagon/imported/mmvec/ext.idef
Log Message:
-----------
Hexagon (target/hexagon) Add v69 HVX instructions
The following instructions are added
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-7-tsimpson@quicinc.com>
Commit: 97ed3e1ef90588d1d2fb45e0ceb02d7e7e6a6131
https://github.com/qemu/qemu/commit/97ed3e1ef90588d1d2fb45e0ceb02d7e7e6a6131
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v69_hvx.c
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v69 HVX tests
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-8-tsimpson@quicinc.com>
Commit: 460fb94ce9cb8e0099c40e6b081bf68d6adfc0ab
https://github.com/qemu/qemu/commit/460fb94ce9cb8e0099c40e6b081bf68d6adfc0ab
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_tcg.h
M target/hexagon/imported/branch.idef
M target/hexagon/imported/encode_pp.def
Log Message:
-----------
Hexagon (target/hexagon) Add v73 scalar instructions
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-9-tsimpson@quicinc.com>
Commit: 29eda8830877239ed9834b4feb23daa64745d7fc
https://github.com/qemu/qemu/commit/29eda8830877239ed9834b4feb23daa64745d7fc
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/v73_scalar.c
Log Message:
-----------
Hexagon (tests/tcg/hexagon) Add v73 scalar tests
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-10-tsimpson@quicinc.com>
Commit: 54095ffc9aa3e1613b2e26a477fa694beff3a96c
https://github.com/qemu/qemu/commit/54095ffc9aa3e1613b2e26a477fa694beff3a96c
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M meson.build
Log Message:
-----------
meson.build Add CONFIG_HEXAGON_IDEF_PARSER
Enable conditional compilation depending on whether idef-parser
is configured
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-2-tsimpson@quicinc.com>
Commit: 11d4ed1169166db854bf401413010663b1a96f23
https://github.com/qemu/qemu/commit/11d4ed1169166db854bf401413010663b1a96f23
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/README
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/idef-parser/parser-helpers.c
Log Message:
-----------
Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-3-tsimpson@quicinc.com>
Commit: 640ef6a1dd556bc773b907c4613f08cfb2e29d99
https://github.com/qemu/qemu/commit/640ef6a1dd556bc773b907c4613f08cfb2e29d99
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for loop setup instructions
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-4-tsimpson@quicinc.com>
Commit: edadfbc6deeaca78c8a762bf9c9ce619d075397a
https://github.com/qemu/qemu/commit/edadfbc6deeaca78c8a762bf9c9ce619d075397a
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for allocframe/deallocframe
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-5-tsimpson@quicinc.com>
Commit: 6467ba10cd197c102e3ef1f3e2cc7605b345f89f
https://github.com/qemu/qemu/commit/6467ba10cd197c102e3ef1f3e2cc7605b345f89f
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/macros.h
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for clr[tf]new
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-6-tsimpson@quicinc.com>
Commit: 9305fa6d169fefc7bd3f54bbb8d5fc22464b157d
https://github.com/qemu/qemu/commit/9305fa6d169fefc7bd3f54bbb8d5fc22464b157d
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/op_helper.h
Log Message:
-----------
Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch]
With the overrides added in prior commits, this function is not used
Remove references in macros.h
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-7-tsimpson@quicinc.com>
Commit: ff105ccfe168f4ed6664f71c132a1c53fc4d2896
https://github.com/qemu/qemu/commit/ff105ccfe168f4ed6664f71c132a1c53fc4d2896
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/macros.h
M target/hexagon/op_helper.c
Log Message:
-----------
Hexagon (target/hexagon) Eliminate uses of log_pred_write function
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
The following instructions are overriden
S2_cabacdecbin
SA1_cmpeqi
Remove the log_pred_write function from op_helper.c
Remove references in macros.h
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-8-tsimpson@quicinc.com>
Commit: 779df5f0dc558666771ce1a35998085d7ab51520
https://github.com/qemu/qemu/commit/779df5f0dc558666771ce1a35998085d7ab51520
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/genptr.c
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Clean up pred_written usage
Only endloop instructions will conditionally write to a predicate.
When there is an endloop instruction, we preload the values into
new_pred_value.
The only place pred_written is needed is when HEX_DEBUG is on.
We remove the last use of check_for_attrib. However, new uses will be
introduced later in this series, so we mark it with G_GNUC_UNUSED.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-9-tsimpson@quicinc.com>
Commit: 5c9f694aee932009a9d634e7b710af73d4978191
https://github.com/qemu/qemu/commit/5c9f694aee932009a9d634e7b710af73d4978191
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/genptr.c
Log Message:
-----------
Hexagon (target/hexagon) Don't overlap dest writes with source reads
When generating TCG, make sure we have read all the operand registers
before writing to the destination registers.
This is a prerequesite for short-circuiting where the source and dest
operands could be the same.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-10-tsimpson@quicinc.com>
Commit: 8be30db42deedc46c3d2560718bf51687bb21ca0
https://github.com/qemu/qemu/commit/8be30db42deedc46c3d2560718bf51687bb21ca0
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/hex_common.py
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Mark registers as read during packet analysis
Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-11-tsimpson@quicinc.com>
Commit: d1c631eab5ef4fa4d40d5cce0dd618eed4df2c3b
https://github.com/qemu/qemu/commit/d1c631eab5ef4fa4d40d5cce0dd618eed4df2c3b
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/arch.c
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_helper_protos.py
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/helper.h
M target/hexagon/hex_common.py
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
Commit: d78a9da3dafb4ff4717ae3ef7be9b87dd9c2c714
https://github.com/qemu/qemu/commit/d78a9da3dafb4ff4717ae3ef7be9b87dd9c2c714
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit packet predicate writes
In certain cases, we can avoid the overhead of writing to hex_new_pred_value
and write directly to hex_pred. We consider predicate reads/writes when
computing ctx->need_commit. The get_result_pred() function uses this
field to decide between hex_new_pred_value and hex_pred. Then, we can
early-exit from gen_pred_writes.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-13-tsimpson@quicinc.com>
Commit: c796d4e83966fa5002a05187f5d10045ba97d936
https://github.com/qemu/qemu/commit/c796d4e83966fa5002a05187f5d10045ba97d936
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/genptr.c
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit packet HVX writes
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-14-tsimpson@quicinc.com>
Commit: 7b62ed2201313a3f318529fb1af1e27e83bbd545
https://github.com/qemu/qemu/commit/7b62ed2201313a3f318529fb1af1e27e83bbd545
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_tcg_hvx.h
M target/hexagon/translate.c
M target/hexagon/translate.h
M tests/tcg/hexagon/hvx_misc.c
Log Message:
-----------
Hexagon (target/hexagon) Short-circuit more HVX single instruction packets
The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap. The instructions with
overrides are OK because they use tcg_gen_gvec_*.
We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction is an HVX instruction with a
generated helper.
We add an override for V6_vcombine so that it can be short-circuited
along with a test case in tests/tcg/hexagon/hvx_misc.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>
Commit: 72068e6a230167953f8e30c51343440ef5535e8f
https://github.com/qemu/qemu/commit/72068e6a230167953f8e30c51343440ef5535e8f
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_tcg.h
M target/hexagon/genptr.c
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/read_write_overlap.c
Log Message:
-----------
Hexagon (target/hexagon) Add overrides for disabled idef-parser insns
The following have overrides
S2_insert
S2_insert_rp
S2_asr_r_svw_trun
A2_swiz
These instructions have semantics that write to the destination
before all the operand reads have been completed. Therefore,
the idef-parser versions were disabled with the short-circuit patch.
Test cases added to tests/tcg/hexagon/read_write_overlap.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-16-tsimpson@quicinc.com>
Commit: 83d2e01564b3c1faf0b9bacbcb1983b29fc1331e
https://github.com/qemu/qemu/commit/83d2e01564b3c1faf0b9bacbcb1983b29fc1331e
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/README
M target/hexagon/cpu.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/macros.h
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Make special new_value for USR
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will
set it's value
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-17-tsimpson@quicinc.com>
Commit: 043954225a9bdd9b3efffe7e438d20358767e5a4
https://github.com/qemu/qemu/commit/043954225a9bdd9b3efffe7e438d20358767e5a4
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/genptr.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move new_value to DisasContext
The new_value array in the CPUHexagonState is only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-18-tsimpson@quicinc.com>
Commit: c3c75e4ae8bebcb27d4316b1d69f2fdc60cec6b4
https://github.com/qemu/qemu/commit/c3c75e4ae8bebcb27d4316b1d69f2fdc60cec6b4
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/idef-parser/parser-helpers.c
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move new_pred_value to DisasContext
The new_pred_value array in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-19-tsimpson@quicinc.com>
Commit: 4b1e35decb5a2e6d41d153039b15341289dab48a
https://github.com/qemu/qemu/commit/4b1e35decb5a2e6d41d153039b15341289dab48a
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move pred_written to DisasContext
The pred_written variable in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-20-tsimpson@quicinc.com>
Commit: 759162593789a8b42cd5aa435a07d8193b75d59d
https://github.com/qemu/qemu/commit/759162593789a8b42cd5aa435a07d8193b75d59d
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/cpu.h
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/hex_common.py
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/op_helper.h
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext
The pkt_has_store_s1 field is only used for bookkeeping helpers with
a load. With recent changes that eliminate the need to free TCGv
variables, it makes more sense to make this transient.
These helpers already take the instruction slot as an argument. We
combine the slot and pkt_has_store_s1 into a single argument called
slotval.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-21-tsimpson@quicinc.com>
Commit: 2ad88d36af3e5805e8b5275af19a2553ec23bf36
https://github.com/qemu/qemu/commit/2ad88d36af3e5805e8b5275af19a2553ec23bf36
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/README
M target/hexagon/cpu.h
M target/hexagon/genptr.c
M target/hexagon/helper.h
M target/hexagon/macros.h
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hexagon/translate.h
Log Message:
-----------
Hexagon (target/hexagon) Move items to DisasContext
The following items in the CPUHexagonState are only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
The following items are moved
dczero_addr
branch_taken
this_PC
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-22-tsimpson@quicinc.com>
Commit: 1ca869b58ee7fc547e8d7a0df6d4d2d4afe47e03
https://github.com/qemu/qemu/commit/1ca869b58ee7fc547e8d7a0df6d4d2d4afe47e03
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/idef-parser/idef-parser.lex
M target/hexagon/idef-parser/idef-parser.y
M target/hexagon/idef-parser/parser-helpers.c
M target/hexagon/idef-parser/parser-helpers.h
M tests/tcg/hexagon/fpstuff.c
M tests/tcg/hexagon/misc.c
Log Message:
-----------
Hexagon (target/hexagon) Additional instructions handled by idef-parser
**** Changes in v3 ****
Fix bugs exposed by dpmpyss_rnd_s0 instruction
Set correct size/signedness for constants
Test cases added to tests/tcg/hexagon/misc.c
**** Changes in v2 ****
Fix bug in imm_print identified in clang build
Currently, idef-parser skips all floating point instructions. However,
there are some floating point instructions that can be handled.
The following instructions are now parsed
F2_sfimm_p
F2_sfimm_n
F2_dfimm_p
F2_dfimm_n
F2_dfmpyll
F2_dfmpylh
To make these instructions work, we fix some bugs in parser-helpers.c
gen_rvalue_extend
gen_cast_op
imm_print
lexer properly sets size/signedness of constants
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230501203125.4025991-1-tsimpson@quicinc.com>
Commit: 29e874d197d10bce445c22bddb8f620ce7444744
https://github.com/qemu/qemu/commit/29e874d197d10bce445c22bddb8f620ce7444744
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/idef-parser/idef-parser.y
M target/hexagon/idef-parser/parser-helpers.c
Log Message:
-----------
target/hexagon: fix = vs. == mishap
**** Changes in v2 ****
Fix yyassert's for sign and zero extends
Coverity reports a parameter that is "set but never used". This is caused
by an assignment operator being used instead of equality.
Co-authored-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Tested-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230428204411.1400931-1-tsimpson@quicinc.com>
Commit: cd2c443a272298ebf60f29fdbb43c572283f8c9f
https://github.com/qemu/qemu/commit/cd2c443a272298ebf60f29fdbb43c572283f8c9f
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_helper_protos.py
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/hex_common.py
Log Message:
-----------
Hexagon (target/hexagon/*.py): raise exception on reg parsing error
Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a register. Let's
make the compilation properly fail in such cases by rasing an exception
instead of just printing a warning message, which might get lost in the
output.
This patch was generated with:
git grep -l "Bad register" *hexagon* | \
xargs sed -i "" -e 's/print("Bad register parse: "[,
]*\([^)]*\))/hex_common.bad_register(\1)/g'
Plus the bad_register() helper added to hex_common.py.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<1f5dbd92f68fdd89e2647e4ba527a2c32cf0f070.1683217043.git.quic_mathbern@quicinc.com>
Commit: 23b3c1ce6c6e3c0239e2c94dad6bf0b842dc462a
https://github.com/qemu/qemu/commit/23b3c1ce6c6e3c0239e2c94dad6bf0b842dc462a
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/cpu.c
M target/hexagon/cpu.h
Log Message:
-----------
Hexagon: list available CPUs with `-cpu help`
Currently, qemu-hexagon only models the v67 cpu. Nonetheless if we try
to get this information with `-cpu help`, qemu just exists with an error
code and no output. Let's correct that.
The code is basically a copy from target/alpha/cpu.h, but we strip the
"-hexagon-cpu" suffix before printing. This is to avoid confusing
situations like the following:
$ qemu-hexagon -cpu help
Available CPUs:
v67-hexagon-cpu
$ qemu-hexagon -cpu v67-hexagon-cpu ./prog
qemu-hexagon: unable to find CPU model 'v67-hexagon-cpu'
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<b946e17c7e17eed9095700b54c5ead36e5d55dfa.1683225804.git.quic_mathbern@quicinc.com>
Commit: 6c97e0310986d1ec8a842d3f3f2d743f48821999
https://github.com/qemu/qemu/commit/6c97e0310986d1ec8a842d3f3f2d743f48821999
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M linux-user/hexagon/target_elf.h
Log Message:
-----------
Hexagon: append eflags to unknown cpu model string
Running qemu-hexagon with a binary that was compiled for an arch version
unknown by qemu can produce a somewhat confusing message:
qemu-hexagon: unable to find CPU model 'unknown'
Let's give a bit more info by appending the eflags so that the message
becomes:
qemu-hexagon: unable to find CPU model 'unknown (0x69)'
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<8a8d013cc619b94fd4fb577ae6a8df26cedb972b.1683225804.git.quic_mathbern@quicinc.com>
Commit: f0166ec79dda18cc170c6cd6b594a1796ea78714
https://github.com/qemu/qemu/commit/f0166ec79dda18cc170c6cd6b594a1796ea78714
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/iclass.c
Log Message:
-----------
Hexagon (iclass): update J4_hintjumpr slot constraints
The Hexagon PRM says that "The assembler automatically encodes
instructions in the packet in the proper order. In the binary encoding
of a packet, the instructions must be ordered from Slot 3 down to
Slot 0."
Prior to the architecture version v73, the slot constraints from
instruction "hintjr" only allowed it to be executed at slot 2.
With that in mind, consider the packet:
{
hintjr(r0)
nop
nop
if (!p0) memd(r1+#0) = r1:0
}
To satisfy the ordering rule quoted from the PRM, the assembler would,
thus, move one of the nops to the first position, so that it can be
assigned to slot 3 and the subsequent hintjr to slot 2.
However, since v73, hintjr can be executed at either slot 2 or 3. So
there is no need to reorder that packet and the assembler will encode it
as is. When QEMU tries to execute it, however, we end up hitting a
"misaliged store" exception because both the store and the hintjr will
be assigned to store 0, and some functions like `slot_is_predicated()`
expect the decode machinery to assign only one instruction per slot. In
particular, the mentioned function will traverse the packet until it
finds the first instruction at the desired slot which, for slot 0, will
be hintjr. Since hintjr is not predicated, the result is that we try to
execute the store regardless of the predicate. And because the predicate
is false, we had not previously loaded hex_store_addr[0] or
hex_store_width[0]. As a result, the store will decide de width based on
trash memory, causing it to be misaligned.
Update the slot constraints for hintjr so that QEMU can properly handle
such encodings.
Note: to avoid similar-but-not-identical issues in the future, we should
look for multiple instructions at the same slot during decoding time and
throw an invalid packet exception. That will be done in the subsequent
commit.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<0fcd8293642c6324119fbbab44741164bcbd04fb.1673616964.git.quic_mathbern@quicinc.com>
Commit: 04726e38aed0cf5587471ec170f2f7714bb22910
https://github.com/qemu/qemu/commit/04726e38aed0cf5587471ec170f2f7714bb22910
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/decode.c
M tests/tcg/hexagon/Makefile.target
A tests/tcg/hexagon/invalid-slots.c
Log Message:
-----------
Hexagon (decode): look for pkts with multiple insns at the same slot
Each slot in a packet can be assigned to at most one instruction.
Although the assembler generally ought to enforce this rule, we better
be safe than sorry and also do some check to properly throw an "invalid
packet" exception on wrong slot assignments.
This should also make it easier to debug possible future errors caused
by missing updates to `find_iclass_slots()` rules in
target/hexagon/iclass.c.
Co-authored-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<f8b829443523568823d062adf8bf6659bc6d4a3f.1683552984.git.quic_mathbern@quicinc.com>
Commit: 26e061f239f38cf0cb2903b4367981d4b51481e1
https://github.com/qemu/qemu/commit/26e061f239f38cf0cb2903b4367981d4b51481e1
Author: Marco Liebel <quic_mliebel@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M tests/tcg/hexagon/hvx_misc.c
Log Message:
-----------
Remove test_vshuff from hvx_misc tests
test_vshuff checks that the vshuff instruction works correctly when
both vector registers are the same. Using vshuff in this way is
undefined and will be rejected by the compiler in a future version of
the toolchain.
Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230509184231.2467626-1-quic_mliebel@quicinc.com>
Commit: da27249d3e3a92f9528317dde82f3ba79f86c2e3
https://github.com/qemu/qemu/commit/da27249d3e3a92f9528317dde82f3ba79f86c2e3
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M gdbstub/gdbstub.c
M gdbstub/internals.h
M gdbstub/softmmu.c
M gdbstub/user.c
Log Message:
-----------
gdbstub: only send stop-reply packets when allowed to
GDB's remote serial protocol allows stop-reply messages to be sent by
the stub either as a notification packet or as a reply to a GDB command
(provided that the cmd accepts such a response). QEMU currently does not
implement notification packets, so it should only send stop-replies
synchronously and when requested. Nevertheless, it still issues
unsolicited stop messages through gdb_vm_state_change().
Although this behavior doesn't seem to cause problems with GDB itself
(the messages are just ignored), it can impact other debuggers that
implement the GDB remote serial protocol, like hexagon-lldb. Let's
change the gdbstub to send stop messages only as a response to a
previous GDB command that accepts such a reply.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<a49c0897fc22a6a7827c8dfc32aef2e1d933ec6b.1683214375.git.quic_mathbern@quicinc.com>
Commit: ffec4ff049fc89878d84a9545c72c10a23f89049
https://github.com/qemu/qemu/commit/ffec4ff049fc89878d84a9545c72c10a23f89049
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M tests/guest-debug/run-test.py
M tests/tcg/multiarch/system/Makefile.softmmu-target
Log Message:
-----------
gdbstub: add test for untimely stop-reply packets
In the previous commit, we modified gdbstub.c to only send stop-reply
packets as a response to GDB commands that accept it. Now, let's add a
test for this intended behavior. Running this test before the fix from
the previous commit fails as QEMU sends a stop-reply packet
asynchronously, when GDB was in fact waiting an ACK.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<a30d93b9a8d66e9d9294354cfa2fc3af35f00202.1683214375.git.quic_mathbern@quicinc.com>
Commit: 3801b476114fd06ca52523337ffcd41ad0797696
https://github.com/qemu/qemu/commit/3801b476114fd06ca52523337ffcd41ad0797696
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M MAINTAINERS
M configs/targets/hexagon-linux-user.mak
A gdb-xml/hexagon-core.xml
M target/hexagon/cpu.c
Log Message:
-----------
Hexagon: add core gdbstub xml data for LLDB
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<d25a3a79334d81f0e1ecfb438b6ee82585d02dc4.1683214375.git.quic_mathbern@quicinc.com>
Commit: de2ac12c64c7950fb75171bce0f26e46d731f724
https://github.com/qemu/qemu/commit/de2ac12c64c7950fb75171bce0f26e46d731f724
Author: Brian Cain <bcain@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M target/hexagon/gdbstub.c
Log Message:
-----------
Hexagon (gdbstub): fix p3:0 read and write via stub
Signed-off-by: Brian Cain <bcain@quicinc.com>
Co-authored-by: Sid Manning <sidneym@quicinc.com>
Signed-off-by: Sid Manning <sidneym@quicinc.com>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<32e7de567cdae184a6781644454bbb19916c955b.1683214375.git.quic_mathbern@quicinc.com>
Commit: a93e92dadc04133e75f1b38dfb22387960b44f98
https://github.com/qemu/qemu/commit/a93e92dadc04133e75f1b38dfb22387960b44f98
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M configs/targets/hexagon-linux-user.mak
A gdb-xml/hexagon-hvx.xml
M target/hexagon/cpu.c
M target/hexagon/gdbstub.c
M target/hexagon/internal.h
Log Message:
-----------
Hexagon (gdbstub): add HVX support
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Co-authored-by: Brian Cain <bcain@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id:
<17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathbern@quicinc.com>
Commit: a1c042e1cc4c1da209f7c3e04aec5e622c7bcdc0
https://github.com/qemu/qemu/commit/a1c042e1cc4c1da209f7c3e04aec5e622c7bcdc0
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2023-05-12 (Fri, 12 May 2023)
Changed paths:
M linux-user/hexagon/cpu_loop.c
Log Message:
-----------
Hexagon (linux-user/hexagon): handle breakpoints
This enables LLDB to work with hexagon linux-user mode through the GDB
remote protocol.
Helped-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<c287a129dcbe7d974d8b7608e8672d34a3c91c04.1683214375.git.quic_mathbern@quicinc.com>
Commit: 76189e34eb11b5b0f57df466c1ad6f43e04521c1
https://github.com/qemu/qemu/commit/76189e34eb11b5b0f57df466c1ad6f43e04521c1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-13 (Sat, 13 May 2023)
Changed paths:
M MAINTAINERS
M configs/targets/hexagon-linux-user.mak
M configure
A gdb-xml/hexagon-core.xml
A gdb-xml/hexagon-hvx.xml
M gdbstub/gdbstub.c
M gdbstub/internals.h
M gdbstub/softmmu.c
M gdbstub/user.c
M linux-user/hexagon/cpu_loop.c
M linux-user/hexagon/target_elf.h
M meson.build
M target/hexagon/README
M target/hexagon/arch.c
M target/hexagon/attribs_def.h.inc
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hexagon/decode.c
M target/hexagon/gdbstub.c
M target/hexagon/gen_analyze_funcs.py
M target/hexagon/gen_helper_funcs.py
M target/hexagon/gen_helper_protos.py
M target/hexagon/gen_idef_parser_funcs.py
M target/hexagon/gen_tcg.h
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/gen_tcg_hvx.h
M target/hexagon/genptr.c
M target/hexagon/genptr.h
M target/hexagon/helper.h
M target/hexagon/hex_common.py
M target/hexagon/iclass.c
M target/hexagon/idef-parser/idef-parser.lex
M target/hexagon/idef-parser/idef-parser.y
M target/hexagon/idef-parser/parser-helpers.c
M target/hexagon/idef-parser/parser-helpers.h
M target/hexagon/imported/branch.idef
M target/hexagon/imported/encode_pp.def
M target/hexagon/imported/ldst.idef
M target/hexagon/imported/mmvec/encode_ext.def
M target/hexagon/imported/mmvec/ext.idef
M target/hexagon/internal.h
M target/hexagon/macros.h
M target/hexagon/mmvec/macros.h
M target/hexagon/op_helper.c
M target/hexagon/op_helper.h
M target/hexagon/translate.c
M target/hexagon/translate.h
M tests/guest-debug/run-test.py
M tests/tcg/hexagon/Makefile.target
M tests/tcg/hexagon/fpstuff.c
M tests/tcg/hexagon/hvx_misc.c
A tests/tcg/hexagon/invalid-slots.c
M tests/tcg/hexagon/misc.c
A tests/tcg/hexagon/read_write_overlap.c
A tests/tcg/hexagon/v68_hvx.c
A tests/tcg/hexagon/v68_scalar.c
A tests/tcg/hexagon/v69_hvx.c
A tests/tcg/hexagon/v6mpy_ref.c.inc
A tests/tcg/hexagon/v73_scalar.c
M tests/tcg/multiarch/system/Makefile.softmmu-target
Log Message:
-----------
Merge tag 'pull-hex-20230512-1' of https://github.com/quic/qemu into staging
Hexagon update
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# gpg: Signature made Fri 12 May 2023 10:44:11 PM BST
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20230512-1' of https://github.com/quic/qemu: (44 commits)
Hexagon (linux-user/hexagon): handle breakpoints
Hexagon (gdbstub): add HVX support
Hexagon (gdbstub): fix p3:0 read and write via stub
Hexagon: add core gdbstub xml data for LLDB
gdbstub: add test for untimely stop-reply packets
gdbstub: only send stop-reply packets when allowed to
Remove test_vshuff from hvx_misc tests
Hexagon (decode): look for pkts with multiple insns at the same slot
Hexagon (iclass): update J4_hintjumpr slot constraints
Hexagon: append eflags to unknown cpu model string
Hexagon: list available CPUs with `-cpu help`
Hexagon (target/hexagon/*.py): raise exception on reg parsing error
target/hexagon: fix = vs. == mishap
Hexagon (target/hexagon) Additional instructions handled by idef-parser
Hexagon (target/hexagon) Move items to DisasContext
Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext
Hexagon (target/hexagon) Move pred_written to DisasContext
Hexagon (target/hexagon) Move new_pred_value to DisasContext
Hexagon (target/hexagon) Move new_value to DisasContext
Hexagon (target/hexagon) Make special new_value for USR
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/debca86cad28...76189e34eb11
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