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[Qemu-commits] [qemu/qemu] 798a81: qapi, i386/sev: Change the reduced-ph
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 798a81: qapi, i386/sev: Change the reduced-phys-bits value... |
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Date: |
Sun, 30 Apr 2023 00:10:10 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 798a818f50a9bfc01e8b5943090de458863b897b
https://github.com/qemu/qemu/commit/798a818f50a9bfc01e8b5943090de458863b897b
Author: Tom Lendacky <thomas.lendacky@amd.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M qapi/misc-target.json
Log Message:
-----------
qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1
A guest only ever experiences, at most, 1 bit of reduced physical
addressing. Change the query-sev-capabilities json comment to use 1.
Fixes: 31dd67f684 ("sev/i386: qmp: add query-sev-capabilities command")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id:
<cb96d8e09154533af4b4e6988469bc0b32390b65.1664550870.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 326e3015c4c6f3197157ea0bb00826ae740e2fad
https://github.com/qemu/qemu/commit/326e3015c4c6f3197157ea0bb00826ae740e2fad
Author: Tom Lendacky <thomas.lendacky@amd.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options.hx: Update the reduced-phys-bits documentation
A guest only ever experiences, at most, 1 bit of reduced physical
addressing. Update the documentation to reflect this as well as change
the example value on the reduced-phys-bits option.
Fixes: a9b4942f48 ("target/i386: add Secure Encrypted Virtualization (SEV)
object")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id:
<13a62ced1808546c1d398e2025cf85f4c94ae123.1664550870.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8168fed9f84e3128f7628969ae78af49433d5ce7
https://github.com/qemu/qemu/commit/8168fed9f84e3128f7628969ae78af49433d5ce7
Author: Tom Lendacky <thomas.lendacky@amd.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/sev.c
Log Message:
-----------
i386/sev: Update checks and information related to reduced-phys-bits
The value of the reduced-phys-bits parameter is propogated to the CPUID
information exposed to the guest. Update the current validation check to
account for the size of the CPUID field (6-bits), ensuring the value is
in the range of 1 to 63.
Maintain backward compatibility, to an extent, by allowing a value greater
than 1 (so that the previously documented value of 5 still works), but not
allowing anything over 63.
Fixes: d8575c6c02 ("sev/i386: add command to initialize the memory encryption
context")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id:
<cca5341a95ac73f904e6300f10b04f9c62e4e8ff.1664550870.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: fb6bbafc0f19385fb257ee073ed13dcaf613f2f8
https://github.com/qemu/qemu/commit/fb6bbafc0f19385fb257ee073ed13dcaf613f2f8
Author: Tom Lendacky <thomas.lendacky@amd.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
i386/cpu: Update how the EBX register of CPUID 0x8000001F is set
Update the setting of CPUID 0x8000001F EBX to clearly document the ranges
associated with fields being set.
Fixes: 6cb8f2a663 ("cpu/i386: populate CPUID 0x8000_001F when SEV is active")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id:
<5822fd7d02b575121380e1f493a8f6d9eba2b11a.1664550870.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a9ce107fd0f2017af84255a9cf6542fa3eb3e214
https://github.com/qemu/qemu/commit/a9ce107fd0f2017af84255a9cf6542fa3eb3e214
Author: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add support for CMPCCXADD in CPUID enumeration
CMPccXADD is a new set of instructions in the latest Intel platform
Sierra Forest. This new instruction set includes a semaphore operation
that can compare and add the operands if condition is met, which can
improve database performance.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 7]
Add CPUID definition for CMPCCXADD.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-2-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5
https://github.com/qemu/qemu/commit/99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5
Author: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add support for AMX-FP16 in CPUID enumeration
Latest Intel platform Granite Rapids has introduced a new instruction -
AMX-FP16, which performs dot-products of two FP16 tiles and accumulates
the results into a packed single precision tile. AMX-FP16 adds FP16
capability and allows a FP16 GPU trained model to run faster without
loss of accuracy or added SW overhead.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 21]
Add CPUID definition for AMX-FP16.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-3-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a957a88416ecbec51e147cba9fe89b93f6646b3b
https://github.com/qemu/qemu/commit/a957a88416ecbec51e147cba9fe89b93f6646b3b
Author: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add support for AVX-IFMA in CPUID enumeration
AVX-IFMA is a new instruction in the latest Intel platform Sierra
Forest. This instruction packed multiplies unsigned 52-bit integers and
adds the low/high 52-bit products to Qword Accumulators.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 23]
Add CPUID definition for AVX-IFMA.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-4-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: eaaa197d5b112ea2758b54df58881a2626de3af5
https://github.com/qemu/qemu/commit/eaaa197d5b112ea2758b54df58881a2626de3af5
Author: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration
AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform
Sierra Forest, aims for the platform to have superior AI capabilities.
This instruction multiplies the individual bytes of two unsigned or
unsigned source operands, then adds and accumulates the results into the
destination dword element size operand.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 4]
AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word
FEAT_7_1_EDX for this leaf.
Add CPUID definition for AVX-VNNI-INT8.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-5-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ecd2e6ca037d7bf3673c5478590d686d5cd6135a
https://github.com/qemu/qemu/commit/ecd2e6ca037d7bf3673c5478590d686d5cd6135a
Author: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration
AVX-NE-CONVERT is a new set of instructions which can convert low
precision floating point like BF16/FP16 to high precision floating point
FP32, as well as convert FP32 elements to BF16. This instruction allows
the platform to have improved AI capabilities and better compatibility.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 5]
Add CPUID definition for AVX-NE-CONVERT.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-6-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d1a1111514333e46a98b136235f71eef90d610fa
https://github.com/qemu/qemu/commit/d1a1111514333e46a98b136235f71eef90d610fa
Author: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration
Latest Intel platform Granite Rapids has introduced a new instruction -
PREFETCHIT0/1, which moves code to memory (cache) closer to the
processor depending on specific hints.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 14]
Add CPUID definition for PREFETCHIT0/1.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-7-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 193ba660af14fc20cddaa04c20bb79ed05d1dbf0
https://github.com/qemu/qemu/commit/193ba660af14fc20cddaa04c20bb79ed05d1dbf0
Author: David 'Digit' Turner <digit@google.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M subprojects/libvhost-user/libvhost-user.c
Log Message:
-----------
Fix libvhost-user.c compilation.
The source file uses VIRTIO_F_VERSION_1 which is
not defined by <linux/virtio_config.h> on Debian 10.
The system-provided <linux/virtio_config.h> which
does not include the macro definition is included
through <linux/vhost.h>, so fix the issue by including
the standard-headers version before that.
Signed-off-by: David 'Digit' Turner <digit@google.com>
Message-Id: <20230405125920.2951721-2-digit@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9fc7dd234f527f411b08e6a266a5ab8e7b79f64f
https://github.com/qemu/qemu/commit/9fc7dd234f527f411b08e6a266a5ab8e7b79f64f
Author: David 'Digit' Turner <digit@google.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M scripts/update-linux-headers.sh
Log Message:
-----------
update-linux-headers.sh: Add missing kernel headers.
Add <linux/memfd.h>, used by hw/display/virtio-gpu-udmabuf.c
Add <linux/nvme_ioctl.h>, used by qga/commands-posix.c
Add <linux/const.h> used by kvm-all.c, which requires
the _BITUL() macro definition to be available.
Without these, QEMU will not compile on Debian 10 systems.
Signed-off-by: David 'Digit' Turner <digit@google.com>
Message-Id: <20230405172109.3081788-3-digit@google.com>
[Add <linux/stddef.h> for __DECLARE_FLEX_ARRAY. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c5c0fdbe39aa2f65fecd93ab3082b1b8a7e2a318
https://github.com/qemu/qemu/commit/c5c0fdbe39aa2f65fecd93ab3082b1b8a7e2a318
Author: David 'Digit' Turner <digit@google.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M include/standard-headers/drm/drm_fourcc.h
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/fuse.h
M include/standard-headers/linux/pci_regs.h
M include/standard-headers/linux/vhost_types.h
M include/standard-headers/linux/virtio_blk.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-x86/kvm.h
A linux-headers/linux/const.h
M linux-headers/linux/kvm.h
A linux-headers/linux/memfd.h
A linux-headers/linux/nvme_ioctl.h
A linux-headers/linux/stddef.h
M linux-headers/linux/vfio.h
M linux-headers/linux/vhost.h
Log Message:
-----------
Update linux headers to v6.3rc5
commit 7e364e56293bb98cae1b55fd835f5991c4e96e7d
Signed-off-by: David 'Digit' Turner <digit@google.com>
Message-Id: <20230405172109.3081788-4-digit@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9260993e27cdbbd2e829d405cc63b1faefec6088
https://github.com/qemu/qemu/commit/9260993e27cdbbd2e829d405cc63b1faefec6088
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M tests/qtest/vhost-user-test.c
Log Message:
-----------
tests: vhost-user-test: release mutex on protocol violation
chr_read() is printing an error message and returning with s->data_mutex taken.
This can potentially cause a hang. Reported by Coverity.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d66ba6dc1cce914673bd8a89fca30a7715ea70d1
https://github.com/qemu/qemu/commit/d66ba6dc1cce914673bd8a89fca30a7715ea70d1
Author: Cédric Le Goater <clg@redhat.com>
Date: 2023-04-29 (Sat, 29 Apr 2023)
Changed paths:
M util/async.c
Log Message:
-----------
async: Suppress GCC13 false positive in aio_bh_poll()
GCC13 reports an error :
../util/async.c: In function ‘aio_bh_poll’:
include/qemu/queue.h:303:22: error: storing the address of local variable
‘slice’ in ‘*ctx.bh_slice_list.sqh_last’ [-Werror=dangling-pointer=]
303 | (head)->sqh_last = &(elm)->field.sqe_next;
\
| ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
../util/async.c:169:5: note: in expansion of macro ‘QSIMPLEQ_INSERT_TAIL’
169 | QSIMPLEQ_INSERT_TAIL(&ctx->bh_slice_list, &slice, next);
| ^~~~~~~~~~~~~~~~~~~~
../util/async.c:161:17: note: ‘slice’ declared here
161 | BHListSlice slice;
| ^~~~~
../util/async.c:161:17: note: ‘ctx’ declared here
But the local variable 'slice' is removed from the global context list
in following loop of the same routine. Add a pragma to silent GCC.
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230420202939.1982044-1-clg@kaod.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 42abcc584174166342297421209932a87bdb85f1
https://github.com/qemu/qemu/commit/42abcc584174166342297421209932a87bdb85f1
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-04-29 (Sat, 29 Apr 2023)
Changed paths:
M cpus-common.c
Log Message:
-----------
cpus-common: stop using mb_set/mb_read
Use a store-release at the end of the work item, and a load-acquire when
waiting for the item to be completed. This is the standard message passing
pattern and is both enough and clearer than mb_read/mb_set.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7c18f2d663521f1b31b821a13358ce38075eaf7d
https://github.com/qemu/qemu/commit/7c18f2d663521f1b31b821a13358ce38075eaf7d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-04-29 (Sat, 29 Apr 2023)
Changed paths:
M cpus-common.c
M include/standard-headers/drm/drm_fourcc.h
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/fuse.h
M include/standard-headers/linux/pci_regs.h
M include/standard-headers/linux/vhost_types.h
M include/standard-headers/linux/virtio_blk.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-x86/kvm.h
A linux-headers/linux/const.h
M linux-headers/linux/kvm.h
A linux-headers/linux/memfd.h
A linux-headers/linux/nvme_ioctl.h
A linux-headers/linux/stddef.h
M linux-headers/linux/vfio.h
M linux-headers/linux/vhost.h
M qapi/misc-target.json
M qemu-options.hx
M scripts/update-linux-headers.sh
M subprojects/libvhost-user/libvhost-user.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/sev.c
M util/async.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Fix compilation issues under Debian 10
* Update kernel headers to 6.3rc5
* Suppress GCC13 false positive in aio_bh_poll()
* Add new x86 feature bits
* Coverity fixes
* More steps towards removing qatomic_mb_set/read
* Fix reduced-phys-bits value for AMD SEV
# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmRNC0IUHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroNo0wgArWNGKZpbmQ0e5L6ajMvaaPmg4mVL
# a2SJGU0TwTp0fUgZr14z2iwzIpSqQrsqhzTIAzOTs0OICDBPBuNvnRucMa+SVQGO
# Tc89YAwBVDo66dAKhWi+WR9tx7sTFCso0nbsBfczzdnwAw3g1MJ87Ueqc5tlPGBK
# E7YSAD6l4UuogoN5BLU7bSsG/X7bwcyzeUXRB4ik+Z9abWd4DH9qiROnBKLMmBLK
# nAi47h8b8MltWORpO+wf6HtkMKi37SAzl9VLHVuHcRhIdY/JhWCRhYSo0HXhgX66
# JLVkyxFpIndT0dUW/xnqATGez92FRZyTxHbxbAcWM0SoC1jOVfUXB+7Gdw==
# =vxou
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 29 Apr 2023 01:19:14 PM BST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
cpus-common: stop using mb_set/mb_read
async: Suppress GCC13 false positive in aio_bh_poll()
tests: vhost-user-test: release mutex on protocol violation
Update linux headers to v6.3rc5
update-linux-headers.sh: Add missing kernel headers.
Fix libvhost-user.c compilation.
target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration
target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration
target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration
target/i386: Add support for AVX-IFMA in CPUID enumeration
target/i386: Add support for AMX-FP16 in CPUID enumeration
target/i386: Add support for CMPCCXADD in CPUID enumeration
i386/cpu: Update how the EBX register of CPUID 0x8000001F is set
i386/sev: Update checks and information related to reduced-phys-bits
qemu-options.hx: Update the reduced-phys-bits documentation
qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/9b112b1b79f0...7c18f2d66352