[Qemu-commits] [qemu/qemu] 3de1fb: target/riscv: update disas.c for xnor

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[Qemu-commits] [qemu/qemu] 3de1fb: target/riscv: update disas.c for xnor

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 3de1fb: target/riscv: update disas.c for xnor/orn/andn and...
Date:	Tue, 07 Feb 2023 12:12:51 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 3de1fb712a072992d72bc99c2b70978132ee44d0
      
https://github.com/qemu/qemu/commit/3de1fb712a072992d72bc99c2b70978132ee44d0
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  target/riscv: update disas.c for xnor/orn/andn and slli.uw

The decoding of the following instructions from Zb[abcs] currently
contains decoding/printing errors:
 * xnor,orn,andn: the rs2 operand is not being printed
 * slli.uw: decodes and prints the immediate shift-amount as a
            register (e.g. 'shift-by-2' becomes 'sp') instead of
            interpreting this as an immediate

This commit updates the instruction descriptions to use the
appropriate decoding/printing formats.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7ae714628745e28e0f1e2d5ad0f95b27a40ff5c2
      
https://github.com/qemu/qemu/commit/7ae714628745e28e0f1e2d5ad0f95b27a40ff5c2
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  include/hw/riscv/opentitan: update opentitan IRQs

Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.

OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47

Memory layout as per [1]

[1] 
https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 32c435a1ae9be183a309fb102d0fc38a4d2cd669
      
https://github.com/qemu/qemu/commit/32c435a1ae9be183a309fb102d0fc38a4d2cd669
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv: boot: Don't use CSRs if they are disabled

If the CSRs and CSR instructions are disabled because the Zicsr
extension isn't enabled then we want to make sure we don't run any CSR
instructions in the boot ROM.

This patches removes the CSR instructions from the reset-vec if the
extension isn't enabled. We replace the instruction with a NOP instead.

Note that we don't do this for the SiFive U machine, as we are modelling
the hardware in that case.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230123035754.75553-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2cfb3b6c9b78fd9d47a2934ba53293c73c680406
      
https://github.com/qemu/qemu/commit/2cfb3b6c9b78fd9d47a2934ba53293c73c680406
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Update VS timer whenever htimedelta changes

The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 14cb78bfaf4f99283252d9683ea4c0d97274ddea
      
https://github.com/qemu/qemu/commit/14cb78bfaf4f99283252d9683ea4c0d97274ddea
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/time_helper.c

  Log Message:
  -----------
  target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP

Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ae0edf2188b3e4346b3e72bb69c75e70869e0c7f
      
https://github.com/qemu/qemu/commit/ae0edf2188b3e4346b3e72bb69c75e70869e0c7f
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/time_helper.c

  Log Message:
  -----------
  target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX

The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-4-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f008a2d218d17b9be998be0045a7a3c229a3376d
      
https://github.com/qemu/qemu/commit/f008a2d218d17b9be998be0045a7a3c229a3376d
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/insn_trans/trans_svinval.c.inc

  Log Message:
  -----------
  target/riscv: Ensure opcode is saved for all relevant instructions

We should call decode_save_opc() for all relevant instructions which
can potentially generate a virtual instruction fault or a guest page
fault because generating transformed instruction upon guest page fault
expects opcode to be available. Without this, hypervisor will see
transformed instruction as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.

Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2967f37d448b86cc5b9a89d83a4e0f4ec01856be
      
https://github.com/qemu/qemu/commit/2967f37d448b86cc5b9a89d83a4e0f4ec01856be
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()

riscv_socket_count() returns either ms->numa_state->num_nodes or 1
depending on NUMA support. In any case the value can be retrieved only
once and used in the rest of the function.

This will also alleviate the rename we're going to do next by reducing
the instances of MachineState 'mc' inside hw/riscv/virt.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230124212234.412630-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 568e0614d0979e0431a8d9dc0503a63b8b0f2d81
      
https://github.com/qemu/qemu/commit/568e0614d0979e0431a8d9dc0503a63b8b0f2d81
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'

We have a convention in other QEMU boards/archs to name MachineState
pointers as either 'machine' or 'ms'. MachineClass pointers are usually
called 'mc'.

The 'virt' RISC-V machine has a lot of instances where MachineState
pointers are named 'mc'. There is nothing wrong with that, but we gain
more compatibility with the rest of the QEMU code base, and easier
reviews, if we follow QEMU conventions.

Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious
and mechanical patch that was produced by doing the following:

- find/replace all 'MachineState *mc' to 'MachineState *ms';
- find/replace all 'mc->fdt' to 'ms->fdt';
- find/replace all 'mc->smp.cpus' to 'ms->smp.cpus';
- replace any remaining occurrences of 'mc' that the compiler complained
about.

Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230124212234.412630-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 606a2439babb7d676af32e15232e94159d67bbeb
      
https://github.com/qemu/qemu/commit/606a2439babb7d676af32e15232e94159d67bbeb
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/spike.c

  Log Message:
  -----------
  hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'

Follow the QEMU convention of naming MachineState pointers as 'ms' by
renaming the instances where we're calling it 'mc'.

Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230124212234.412630-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 26934f9a95264221ed8e6d603b8099508fbd2a5e
      
https://github.com/qemu/qemu/commit/26934f9a95264221ed8e6d603b8099508fbd2a5e
  Author: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/debug.c

  Log Message:
  -----------
  target/riscv: set tval for triggered watchpoints

According to privileged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is triggered by hardware watchpoint.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131170955.752743-1-geomatsi@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 909f7da60472b82668d2b2abdb19eba53603b408
      
https://github.com/qemu/qemu/commit/909f7da60472b82668d2b2abdb19eba53603b408
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv/boot.c: calculate fdt size after fdt_pack()

fdt_pack() can change the fdt size, meaning that fdt_totalsize() can
contain a now deprecated (bigger) value.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230201171212.1219375-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bc2c01535317ebfd994668bb04a040c452247be3
      
https://github.com/qemu/qemu/commit/bc2c01535317ebfd994668bb04a040c452247be3
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: split fdt address calculation from fdt load

A common trend in other archs is to calculate the fdt address, which is
usually straightforward, and then calling a function that loads the
fdt/dtb by using that address.

riscv_load_fdt() is doing a bit too much in comparison. It's calculating
the fdt address via an elaborated heuristic to put the FDT at the bottom
of DRAM, and "bottom of DRAM" will vary across boards and
configurations, then it's actually loading the fdt, and finally it's
returning the fdt address used to the caller.

Reduce the existing complexity of riscv_load_fdt() by splitting its code
into a new function, riscv_compute_fdt_addr(), that will take care of
all fdt address logic. riscv_load_fdt() can then be a simple function
that just loads a fdt at the given fdt address.

We're also taken the opportunity to clarify the intentions and
assumptions made by these functions. riscv_load_fdt() is now receiving a
hwaddr as fdt_addr because there is no restriction of having to load the
fdt in higher addresses that doesn't fit in an uint32_t.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230201171212.1219375-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4b402886ac89732f903094004612039d0fd5b4cb
      
https://github.com/qemu/qemu/commit/4b402886ac89732f903094004612039d0fd5b4cb
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: change riscv_compute_fdt_addr() semantics

As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a
mem_size (which is defaulted to MachineState::ram_size in all boards)
and the FDT pointer. And it makes a very important assumption: the DRAM
interval dram_base + mem_size is contiguous. This is indeed the case for
most boards that use a FDT.

The Icicle Kit board works with 2 distinct RAM banks that are separated
by a gap. We have a lower bank with 1GiB size, a gap follows, then at
64GiB the high memory starts. MachineClass::default_ram_size for this
board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM
size, meaning that there we'll always have at least 512 MiB in the Hi
RAM area.

Using riscv_compute_fdt_addr() in this board is weird because not only
the board has sparse RAM, and it's calling it using the base address of
the Lo RAM area, but it's also using a mem_size that we have guarantees
that it will go up to the Hi RAM. All the function assumptions doesn't
work for this board.

In fact, what makes the function works at all in this case is a
coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT,
down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For
the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000
(2 Gb) and it has a 1Gb size, so it will fall in the conditions to put
the FDT under a 3Gb address, which happens to be exactly at the end of
DRAM_LO. If the base address of the Lo area started later than 3Gb this
function would be unusable by the board. Changing any assumptions inside
riscv_compute_fdt_addr() can also break it by accident as well.

Let's change riscv_compute_fdt_addr() semantics to be appropriate to the
Icicle Kit board and for future boards that might have sparse RAM
topologies to worry about:

- relieve the condition that the dram_base + mem_size area is contiguous,
since this is already not the case today;

- receive an extra 'dram_size' size attribute that refers to a contiguous
RAM block that the board wants the FDT to reside on.

Together with 'mem_size' and 'fdt', which are now now being consumed by a
MachineState pointer, we're able to make clear assumptions based on the
DRAM block and total mem_size available to ensure that the FDT will be put
in a valid RAM address.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230201171212.1219375-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 49a7f3aabba99e06768cbaf6c9429f514a9c7444
      
https://github.com/qemu/qemu/commit/49a7f3aabba99e06768cbaf6c9429f514a9c7444
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    A target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/meson.build
    M target/riscv/translate.c
    A target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding XTheadCmo ISA extension

This patch adds support for the XTheadCmo ISA extension.
To avoid interfering with standard extensions, decoder and translation
are in its own xthead* specific files.
Future patches should be able to easily add additional T-Head extension.

The implementation does not have much functionality (besides accepting
the instructions and not qualifying them as illegal instructions if
the hart executes in the required privilege level for the instruction),
as QEMU does not model CPU caches and instructions are documented
to not raise any exceptions.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 134c3ffa34d005861f37cf6258b09df229e7be22
      
https://github.com/qemu/qemu/commit/134c3ffa34d005861f37cf6258b09df229e7be22
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/helper.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/op_helper.c
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding XTheadSync ISA extension

This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.

The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c9410a689f9f8c79378bd6d806bac3495b1eb856
      
https://github.com/qemu/qemu/commit/c9410a689f9f8c79378bd6d806bac3495b1eb856
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding XTheadBa ISA extension

This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 426c049196efcdfc57511f779ec0416dd95a9cce
      
https://github.com/qemu/qemu/commit/426c049196efcdfc57511f779ec0416dd95a9cce
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding XTheadBb ISA extension

This patch adds support for the XTheadBb ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-5-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fa134585462897fc70a01d7b585fbc60371a7d17
      
https://github.com/qemu/qemu/commit/fa134585462897fc70a01d7b585fbc60371a7d17
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding XTheadBs ISA extension

This patch adds support for the XTheadBs ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3290933853c2c8a4a50a990cc395471097f0a173
      
https://github.com/qemu/qemu/commit/3290933853c2c8a4a50a990cc395471097f0a173
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding XTheadCondMov ISA extension

This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b8a5832b87fb513725cd6d960cae6476f3a515c7
      
https://github.com/qemu/qemu/commit/b8a5832b87fb513725cd6d960cae6476f3a515c7
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding T-Head multiply-accumulate instructions

This patch adds support for the T-Head MAC instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: af99aa72ef4576693208b827c975fac57c8b6fde
      
https://github.com/qemu/qemu/commit/af99aa72ef4576693208b827c975fac57c8b6fde
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding T-Head MemPair extension

This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 45f9df86db487573dc9a5e12e2afdb219d399a42
      
https://github.com/qemu/qemu/commit/45f9df86db487573dc9a5e12e2afdb219d399a42
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding T-Head MemIdx extension

This patch adds support for the T-Head MemIdx instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-10-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d4d901157e9fd323a155fdaf4d938afcafd7b857
      
https://github.com/qemu/qemu/commit/d4d901157e9fd323a155fdaf4d938afcafd7b857
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding T-Head FMemIdx extension

This patch adds support for the T-Head FMemIdx instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-11-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7ad2878cfd8356e1b9c1097edae367507c182066
      
https://github.com/qemu/qemu/commit/7ad2878cfd8356e1b9c1097edae367507c182066
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  RISC-V: Set minimum priv version for Zfh to 1.11

There are no differences for floating point instructions in priv version 1.11
and 1.12. There is also no dependency for Zfh to priv version 1.12.
Therefore allow Zfh to be enabled for priv version 1.11.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-12-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 95bd8daaafdff905ee4fa0620c097ad4eb2e8a13
      
https://github.com/qemu/qemu/commit/95bd8daaafdff905ee4fa0620c097ad4eb2e8a13
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    A target/riscv/cpu_vendorid.h

  Log Message:
  -----------
  RISC-V: Add initial support for T-Head C906

This patch adds the T-Head C906 to the list of known CPUs.
Selecting this CPUs will automatically enable the available
ISA extensions of the CPUs (incl. vendor extensions).

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 578086ba2ffe4afb24b94975d75dfc02f8be1ee4
      
https://github.com/qemu/qemu/commit/578086ba2ffe4afb24b94975d75dfc02f8be1ee4
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/translate.c
    M target/riscv/xthead.decode

  Log Message:
  -----------
  RISC-V: Adding XTheadFmv ISA extension

This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 179d9e2911f26088360a1d663767cf6612f96f44
      
https://github.com/qemu/qemu/commit/179d9e2911f26088360a1d663767cf6612f96f44
  Author: Christoph Müllner <christoph.muellner@vrull.eu>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  target/riscv: add a MAINTAINERS entry for XThead* extension support

The XThead* extensions are maintained by T-Head and VRULL.
Adding a point of contact from both companies.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-15-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 506c6698fbe53e88fba3160fc3842e5d41a9ee25
      
https://github.com/qemu/qemu/commit/506c6698fbe53e88fba3160fc3842e5d41a9ee25
  Author: Deepak Gupta <debug@rivosinc.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: fix for virtual instr exception

commit fb3f3730e4 added mechanism to generate virtual instruction
exception during instruction decode when virt is enabled.

However in some situations, illegal instruction exception can be raised
due to state of CPU. One such situation is implementing branch tracking.
[1] An indirect branch if doesn't land on a landing pad instruction, then
cpu must raise an illegal instruction exception.
Implementation would raise such expcetion due to missing landing pad inst
and not due to decode. Thus DisasContext must have `virt_inst_excp`
initialized to false during DisasContxt initialization for TB.

[1] - https://github.com/riscv/riscv-cfi

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230127191758.755844-1-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5fc0fc8788e08f151f5d0c47d205e009aeb33844
      
https://github.com/qemu/qemu/commit/5fc0fc8788e08f151f5d0c47d205e009aeb33844
  Author: Vladimir Isaev <vladimir.isaev@syntacore.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/insn_trans/trans_rvb.c.inc

  Log Message:
  -----------
  target/riscv: fix ctzw behavior

According to spec, ctzw should work with 32-bit register, not 64.

For example, previous implementation returns 33 for (1<<33) input
when the new one returns 32.

Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230204082312.43557-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 947bf7fe9f0831cb6944334a06ff0b84926612b8
      
https://github.com/qemu/qemu/commit/947bf7fe9f0831cb6944334a06ff0b84926612b8
  Author: Vladimir Isaev <vladimir.isaev@syntacore.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M target/riscv/kvm.c

  Log Message:
  -----------
  target/riscv: fix SBI getchar handler for KVM

Character must be returned via ret[0] field (copied to a0 by KVM).

Return value should be set to 0 to indicate successful processing.

Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230203135155.12449-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c
      
https://github.com/qemu/qemu/commit/5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Simplify virt_{get,set}_aclint()

There is no need to declare an intermediate "MachineState *ms".

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230206085007.3618715-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5c71a911267f742a71e2c7725dd3164347c61738
      
https://github.com/qemu/qemu/commit/5c71a911267f742a71e2c7725dd3164347c61738
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M MAINTAINERS
    M disas/riscv.c
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    M include/hw/riscv/opentitan.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    A target/riscv/cpu_vendorid.h
    M target/riscv/csr.c
    M target/riscv/debug.c
    M target/riscv/helper.h
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/insn_trans/trans_svinval.c.inc
    A target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/kvm.c
    M target/riscv/meson.build
    M target/riscv/op_helper.c
    M target/riscv/time_helper.c
    M target/riscv/translate.c
    A target/riscv/xthead.decode

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20230207' of 
https://github.com/alistair23/qemu into staging

Third RISC-V PR for QEMU 8.0

* Update disas for xnor/orn/andn and slli.uw
* Update opentitan IRQs
* Fix rom code when Zicsr is disabled
* Update VS timer whenever htimedelta changes
* A collection of fixes for virtulisation
* Set tval for triggered watchpoints
* Cleanups for board and FDT creation
* Add support for the T-Head vendor extensions
* A fix for virtual instr exception
* Fix ctzw behavior
* Fix SBI getchar handler for KVM

# -----BEGIN PGP SIGNATURE-----
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# =XLpK
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Feb 2023 07:08:52 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20230207' of https://github.com/alistair23/qemu: (32 
commits)
  hw/riscv: virt: Simplify virt_{get,set}_aclint()
  target/riscv: fix SBI getchar handler for KVM
  target/riscv: fix ctzw behavior
  target/riscv: fix for virtual instr exception
  target/riscv: add a MAINTAINERS entry for XThead* extension support
  RISC-V: Adding XTheadFmv ISA extension
  RISC-V: Add initial support for T-Head C906
  RISC-V: Set minimum priv version for Zfh to 1.11
  RISC-V: Adding T-Head FMemIdx extension
  RISC-V: Adding T-Head MemIdx extension
  RISC-V: Adding T-Head MemPair extension
  RISC-V: Adding T-Head multiply-accumulate instructions
  RISC-V: Adding XTheadCondMov ISA extension
  RISC-V: Adding XTheadBs ISA extension
  RISC-V: Adding XTheadBb ISA extension
  RISC-V: Adding XTheadBa ISA extension
  RISC-V: Adding XTheadSync ISA extension
  RISC-V: Adding XTheadCmo ISA extension
  hw/riscv: change riscv_compute_fdt_addr() semantics
  hw/riscv: split fdt address calculation from fdt load
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/b86307ecef92...5c71a911267f
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