[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 99ab4d: accel/tcg: Test CPUJumpCache in tb_jm
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 99ab4d: accel/tcg: Test CPUJumpCache in tb_jmp_cache_clear... |
|
Date: |
Sun, 05 Feb 2023 16:48:50 +0000 (UTC) |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 99ab4d500af638ba3ebb20e8aa89d72201b70860
https://github.com/qemu/qemu/commit/99ab4d500af638ba3ebb20e8aa89d72201b70860
Author: Eric Auger <eric.auger@redhat.com>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Test CPUJumpCache in tb_jmp_cache_clear_page
After commit 4e4fa6c12d ("accel/tcg: Complete cpu initialization
before registration"), it looks the CPUJumpCache pointer can be NULL.
This causes a SIGSEV when running debug-wp-migration kvm unit test.
At the first place it should be clarified why this TCG code is called
with KVM acceleration. This may hide another bug.
Fixes: 4e4fa6c12d ("accel/tcg: Complete cpu initialization before registration")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <20230203171510.2867451-1-eric.auger@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e1e646524437072e466313b04a2f8326dd7b8e77
https://github.com/qemu/qemu/commit/e1e646524437072e466313b04a2f8326dd7b8e77
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Init temp_subindex in liveness_pass_2
Correctly handle large types while lowering.
Fixes: fac87bd2a49b ("tcg: Add temp_subindex to TCGTemp")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ecbea3ec1ce5f4499ef6acbc696ec5d6a1c69165
https://github.com/qemu/qemu/commit/ecbea3ec1ce5f4499ef6acbc696ec5d6a1c69165
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M include/exec/helper-head.h
M include/tcg/tcg.h
Log Message:
-----------
tcg: Define TCG_TYPE_I128 and related helper macros
Begin staging in support for TCGv_i128 with Int128.
Define the type enumerator, the typedef, and the
helper-head.h macros.
This cannot yet be used, because you can't allocate
temporaries of this new type.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 466d37596010845eb61fbb8b5cd7daa407286342
https://github.com/qemu/qemu/commit/466d37596010845eb61fbb8b5cd7daa407286342
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Handle dh_typecode_i128 with TCG_CALL_{RET,ARG}_NORMAL
Many hosts pass and return 128-bit quantities like sequential
64-bit quantities. Treat this just like we currently break
down 64-bit quantities for a 32-bit host.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 273eb50c0fed6696d4600d9cf26f1b2dfcccab0c
https://github.com/qemu/qemu/commit/273eb50c0fed6696d4600d9cf26f1b2dfcccab0c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Allocate objects contiguously in temp_allocate_frame
When allocating a temp to the stack frame, consider the
base type and allocate all parts at once.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6a6d772e30d62e209587ef341df243e9789f5a9f
https://github.com/qemu/qemu/commit/6a6d772e30d62e209587ef341df243e9789f5a9f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Introduce tcg_out_addi_ptr
Implement the function for arm, i386, and s390x, which will use it.
Add stubs for all other backends.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 313bdea84d2912fdbb139e746bd9346b3d85ebdc
https://github.com/qemu/qemu/commit/313bdea84d2912fdbb139e746bd9346b3d85ebdc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/tcg-internal.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add TCG_CALL_{RET,ARG}_BY_REF
These will be used by some hosts, both 32 and 64-bit, to pass and
return i128. Not yet used, because allocation is not yet enabled.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5e3d0c199f4edf4ecdf8100464da441c60ce36e3
https://github.com/qemu/qemu/commit/5e3d0c199f4edf4ecdf8100464da441c60ce36e3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Introduce tcg_target_call_oarg_reg
Replace the flat array tcg_target_call_oarg_regs[] with
a function call including the TCGCallReturnKind.
Extend the set of registers for ARM to r0-r3 to match the ABI:
https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#result-return
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c6556aa0c8de8718813fea0ca61232632bf33c42
https://github.com/qemu/qemu/commit/c6556aa0c8de8718813fea0ca61232632bf33c42
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/tcg-internal.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add TCG_CALL_RET_BY_VEC
This will be used by _WIN64 to return i128. Not yet used,
because allocation is not yet enabled.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b959822c94e6d32b36fad038e79c14f841e585c1
https://github.com/qemu/qemu/commit/b959822c94e6d32b36fad038e79c14f841e585c1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M include/qemu/atomic128.h
M include/qemu/int128.h
M util/int128.c
Log Message:
-----------
include/qemu/int128: Use Int128 structure for TCI
We are about to allow passing Int128 to/from tcg helper functions,
but libffi doesn't support __int128_t, so use the structure.
In order for atomic128.h to continue working, we must provide
a mechanism to frob between real __int128_t and the structure.
Provide a new union, Int128Alias, for this. We cannot modify
Int128 itself, as any changed alignment would also break libffi.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c4f4a00ac7d947c9b100e3cb62755a9a157df1fa
https://github.com/qemu/qemu/commit/c4f4a00ac7d947c9b100e3cb62755a9a157df1fa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
Log Message:
-----------
tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128
Fill in the parameters for the host ABI for Int128.
Adjust tcg_target_call_oarg_reg for _WIN64, and
tcg_out_call for i386 sysv. Allow TCG_TYPE_V128
stores without AVX enabled.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 896c76e6ba5d9a3444fb8528fdc407747ecc82f2
https://github.com/qemu/qemu/commit/896c76e6ba5d9a3444fb8528fdc407747ecc82f2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Fix big-endian return register ordering
We expect the backend to require register pairs in
host-endian ordering, thus for big-endian the first
register of a pair contains the high part.
We were forcing R0 to contain the low part for calls.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e9709e17ac88f16c60004c4160c9a131d36ed564
https://github.com/qemu/qemu/commit/e9709e17ac88f16c60004c4160c9a131d36ed564
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128
Fill in the parameters for libffi for Int128.
Adjust the interpreter to allow for 16-byte return values.
Adjust tcg_out_call to record the return value length.
Call parameters are no longer all the same size, so we
cannot reuse the same call_slots array for every function.
Compute it each time now, but only fill in slots required
for the call we're about to make.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5427a9a76041029730775292995e87c3edd06515
https://github.com/qemu/qemu/commit/5427a9a76041029730775292995e87c3edd06515
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128
Fill in the parameters for the host ABI for Int128 for
those backends which require no extra modification.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 43eef72f41093ae4a94ffddc94aeef80a2fb5c69
https://github.com/qemu/qemu/commit/43eef72f41093ae4a94ffddc94aeef80a2fb5c69
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add temp allocation for TCGv_i128
This enables allocation of i128. The type is not yet
usable, as we have not yet added data movement ops.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4771e71c28eb0cece2a17a2d891bbd724bdc158d
https://github.com/qemu/qemu/commit/4771e71c28eb0cece2a17a2d891bbd724bdc158d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M include/tcg/tcg-op.h
M tcg/tcg-internal.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Add basic data movement for TCGv_i128
Add code generation functions for data movement between
TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract).
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cb48f3654e290ee5d7cbf1fb31888463fa2a180c
https://github.com/qemu/qemu/commit/cb48f3654e290ee5d7cbf1fb31888463fa2a180c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M include/exec/cpu_ldst.h
M include/tcg/tcg-op.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Add guest load/store primitives for TCGv_i128
These are not yet considering atomicity of the 16-byte value;
this is a direct replacement for the current target code which
uses a pair of 8-byte operations.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 123ae5683c9e7815857304fd2f21664621c90a13
https://github.com/qemu/qemu/commit/123ae5683c9e7815857304fd2f21664621c90a13
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M accel/tcg/atomic_common.c.inc
M accel/tcg/tcg-runtime.h
M include/tcg/tcg-op.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Add tcg_gen_{non}atomic_cmpxchg_i128
This will allow targets to avoid rolling their own.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d1beee4da1dbbc0ce1bc42b38752366eed4babec
https://github.com/qemu/qemu/commit/d1beee4da1dbbc0ce1bc42b38752366eed4babec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M include/tcg/tcg-op.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64}
Normally this is automatically handled by the CF_PARALLEL checks
with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special
case of !PREFIX_LOCK where it always wants the non-atomic version.
Split these out so that x86 does not have to roll its own.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 546789c7df8866c55cae8d3195e8e58328a35d51
https://github.com/qemu/qemu/commit/546789c7df8866c55cae8d3195e8e58328a35d51
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/arm/helper-a64.c
M target/arm/helper-a64.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20221112042555.2622152-2-richard.henderson@linaro.org>
Commit: 9c32396debee91a87867abc562bb8e2b458c958a
https://github.com/qemu/qemu/commit/9c32396debee91a87867abc562bb8e2b458c958a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/arm/helper-a64.c
M target/arm/helper-a64.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20221112042555.2622152-3-richard.henderson@linaro.org>
Commit: 894448ae7dce4269c4b3c152a7091520317ea397
https://github.com/qemu/qemu/commit/894448ae7dce4269c4b3c152a7091520317ea397
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/ppc/helper.h
M target/ppc/mem_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX
Note that the previous direct reference to reserve_val,
- tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
- ? offsetof(CPUPPCState, reserve_val2)
- : offsetof(CPUPPCState, reserve_val)));
was incorrect because all references should have gone through
cpu_reserve_val. Create a cpu_reserve_val2 tcg temp to fix this.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221112061122.2720163-2-richard.henderson@linaro.org>
Commit: 29b8de001f8ea2f36d4de5a250d1150492311529
https://github.com/qemu/qemu/commit/29b8de001f8ea2f36d4de5a250d1150492311529
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/div.c
Log Message:
-----------
tests/tcg/s390x: Add div.c
Add a basic test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20221101111300.2539919-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c432198ab09205d06ba9cf53cb4610d5fae22aa7
https://github.com/qemu/qemu/commit/c432198ab09205d06ba9cf53cb4610d5fae22aa7
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/clst.c
Log Message:
-----------
tests/tcg/s390x: Add clst.c
Add a basic test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20221025213008.2209006-2-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 521d38ec9b4da82576dfcd3c5b6a2172cda25736
https://github.com/qemu/qemu/commit/521d38ec9b4da82576dfcd3c5b6a2172cda25736
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/long-double.c
Log Message:
-----------
tests/tcg/s390x: Add long-double.c
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 82f6584c9b1345489a6446b3bc4086e00e8d67d1
https://github.com/qemu/qemu/commit/82f6584c9b1345489a6446b3bc4086e00e8d67d1
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/cdsg.c
Log Message:
-----------
tests/tcg/s390x: Add cdsg.c
Add a simple test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20230201133257.3223115-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6d28ff406c71c2c6f8a79edb1ccfc17978aa95fb
https://github.com/qemu/qemu/commit/6d28ff406c71c2c6f8a79edb1ccfc17978aa95fb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/int_helper.c
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use a single return for helper_divs32/u32
Pack the quotient and remainder into a single uint64_t.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix operand ordering; use tcg_extr32_i64.
Commit: 4e5712f9037c34bbd9ffd78baa9d1ebea13a430d
https://github.com/qemu/qemu/commit/4e5712f9037c34bbd9ffd78baa9d1ebea13a430d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/int_helper.c
M target/s390x/tcg/translate.c
M tests/tcg/s390x/div.c
Log Message:
-----------
target/s390x: Use a single return for helper_divs64/u64
Pack the quotient and remainder into a single Int128.
Use the divu128 primitive to remove the cpu_abort on
32-bit hosts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Extended div test case to cover these insns.
Commit: b71dd2a51e898ee91bee3e23708e8d4d14ac6812
https://github.com/qemu/qemu/commit/b71dd2a51e898ee91bee3e23708e8d4d14ac6812
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use Int128 for return from CLST
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c91192245ac32c219ba698e3ca5e976cbed3359b
https://github.com/qemu/qemu/commit/c91192245ac32c219ba698e3ca5e976cbed3359b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use Int128 for return from CKSM
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ef45f5b998126205e0362c7af4c5d6ee65801450
https://github.com/qemu/qemu/commit/ef45f5b998126205e0362c7af4c5d6ee65801450
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use Int128 for return from TRE
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f4031d9664d6db63dc384e1bca38739b2cb50acd
https://github.com/qemu/qemu/commit/f4031d9664d6db63dc384e1bca38739b2cb50acd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/tcg/insn-data.h.inc
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Copy wout_x1 to wout_x1_P
Make a copy of wout_x1 before modifying it, as wout_x1_P
emphasizing that it operates on the out/out2 pair. The insns
that use x1_P are data movement that will not change to Int128.
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ee5e866fd2304a08172c3674dd7c7e7a97b046ed
https://github.com/qemu/qemu/commit/ee5e866fd2304a08172c3674dd7c7e7a97b046ed
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/fpu_helper.c
M target/s390x/tcg/insn-data.h.inc
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use Int128 for returning float128
Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Remove extraneous return_low128.
Commit: 2b91240f95fdb9acfa35ccac6cda2a42a16ac7f2
https://github.com/qemu/qemu/commit/2b91240f95fdb9acfa35ccac6cda2a42a16ac7f2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/fpu_helper.c
M target/s390x/tcg/insn-data.h.inc
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use Int128 for passing float128
Acked-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix SPEC_in1_x1.
Commit: 1fcd84fa0d610c1215cced54e64046a47148a388
https://github.com/qemu/qemu/commit/1fcd84fa0d610c1215cced54e64046a47148a388
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/helper.h
M target/s390x/tcg/insn-data.h.inc
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b5deff74d1b1cb33b65a6c8db44fc87e972b53f7
https://github.com/qemu/qemu/commit/b5deff74d1b1cb33b65a6c8db44fc87e972b53f7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Implement CC_OP_NZ in gen_op_calc_cc
This case is trivial to implement inline.
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6218c177afb341e5a64428fcc17decbc9d6247a6
https://github.com/qemu/qemu/commit/6218c177afb341e5a64428fcc17decbc9d6247a6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 326ad06cf5b2cf6f4ed7ca635269e89fd189e1a4
https://github.com/qemu/qemu/commit/326ad06cf5b2cf6f4ed7ca635269e89fd189e1a4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/i386/helper.h
M target/i386/tcg/mem_helper.c
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Inline cmpxchg8b
Use tcg_gen_atomic_cmpxchg_i64 for the atomic case,
and tcg_gen_nonatomic_cmpxchg_i64 otherwise.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5f0dd8cd33cb6c753ed4435e13bd0622a38a9967
https://github.com/qemu/qemu/commit/5f0dd8cd33cb6c753ed4435e13bd0622a38a9967
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M target/i386/helper.h
M target/i386/tcg/mem_helper.c
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Inline cmpxchg16b
Use tcg_gen_atomic_cmpxchg_i128 for the atomic case,
and tcg_gen_qemu_ld/st_i128 otherwise.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a2495ede07498ee36b18b03e7038ba30c9871bb2
https://github.com/qemu/qemu/commit/a2495ede07498ee36b18b03e7038ba30c9871bb2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target
'offset' should be bits [23:5] of LDR instruction, rather than [4:0].
Fixes: d59d83a1c388 ("tcg/aarch64: Reorg goto_tb implementation")
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b52388129bf0097954515c097e83e6112de1b579
https://github.com/qemu/qemu/commit/b52388129bf0097954515c097e83e6112de1b579
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-02-04 (Sat, 04 Feb 2023)
Changed paths:
M accel/tcg/atomic_common.c.inc
M accel/tcg/cputlb.c
M accel/tcg/tcg-runtime.h
M accel/tcg/user-exec.c
M include/exec/cpu_ldst.h
M include/exec/helper-head.h
M include/qemu/atomic128.h
M include/qemu/int128.h
M include/tcg/tcg-op.h
M include/tcg/tcg.h
M target/arm/helper-a64.c
M target/arm/helper-a64.h
M target/arm/translate-a64.c
M target/i386/helper.h
M target/i386/tcg/mem_helper.c
M target/i386/tcg/translate.c
M target/ppc/helper.h
M target/ppc/mem_helper.c
M target/ppc/translate.c
M target/s390x/helper.h
M target/s390x/tcg/fpu_helper.c
M target/s390x/tcg/insn-data.h.inc
M target/s390x/tcg/int_helper.c
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/translate.c
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
M tcg/tcg-internal.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/cdsg.c
A tests/tcg/s390x/clst.c
A tests/tcg/s390x/div.c
A tests/tcg/s390x/long-double.c
M util/int128.c
Log Message:
-----------
Merge tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu into staging
tcg: Add support for TCGv_i128 in parameters and returns.
tcg: Add support for TCGv_i128 in cmpxchg.
tcg: Test CPUJumpCache in tb_jmp_cache_clear_page
tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64}
tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target
target/arm: Use tcg_gen_atomic_cmpxchg_i128
target/i386: Use tcg_gen_atomic_cmpxchg_i128
target/i386: Use tcg_gen_nonatomic_cmpxchg_i{32,64}
target/s390x: Use tcg_gen_atomic_cmpxchg_i128
target/s390x: Use TCGv_i128 in passing and returning float128
target/s390x: Implement CC_OP_NZ in gen_op_calc_cc
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmPeiDYdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+hFQf+K1MkEK1wtpjnqrYD
# 4l36Uo3B7w8Yi6FxbCx9NP78dJNNTjTn0zqhtISRKSzI7TGUCGnmQs40iqYrRe5S
# 9x6LJgTJplI2dsANvtsTaWB5gNzhowPt5tlit+J6Q0POwvvwcBZAOumY8AYt1YP+
# dMsjBLw6HFaqSCU5IERZrB4kBwl61VTkTAtHL2utSZpdsOYoc3y2hzbJ/w3kLK2u
# YXnMvom+Gc1rvQTaSMgiPYFITyx/VtXDe+JQwNikpu7Na+RFjtu7cHmg/BtZFo6s
# 15AsAS8JlENKAunpJiX41UR7SxB8MdyQL5LyjVNWo5F7+YgQuuO1gqYKt6qUwd+A
# oH2uBA==
# =xjMy
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 04 Feb 2023 16:30:46 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu: (40 commits)
tcg/aarch64: Fix patching of LDR in tb_target_set_jmp_target
target/i386: Inline cmpxchg16b
target/i386: Inline cmpxchg8b
target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b
target/s390x: Implement CC_OP_NZ in gen_op_calc_cc
target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG
target/s390x: Use Int128 for passing float128
target/s390x: Use Int128 for returning float128
target/s390x: Copy wout_x1 to wout_x1_P
target/s390x: Use Int128 for return from TRE
target/s390x: Use Int128 for return from CKSM
target/s390x: Use Int128 for return from CLST
target/s390x: Use a single return for helper_divs64/u64
target/s390x: Use a single return for helper_divs32/u32
tests/tcg/s390x: Add cdsg.c
tests/tcg/s390x: Add long-double.c
tests/tcg/s390x: Add clst.c
tests/tcg/s390x: Add div.c
target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX
target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/ceabf6e50057...b52388129bf0